GaAs Low-Power Integrated Circuits for a High- Speed Digital Signal Processor

HAUSILA P. SINGH, SENIOR MEMBER, I I -FF, ROBERT A. SADLER. M I M B E R . i t I 1 ,

JAMES A. IRVINE, M E M B E R , I E E I - , A N D GRETA E GORDER

Ahstract-A high-speed 4-hit ALU, 4 x 4-hit multiplier, and 8 x 8-bit multiplieriaccumulator have been implemented in low-pobrer GaAs EiD direct-coupled PET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate hlESFET process. The 4-hit ALU perfornis at up to 1.2 GHz with only 131-mW power dissipation. The multiplication tinme for the 4 x 4-bit arraj mul- tiplier is 940 ps, which is the fastest multiplication time reported for an! semiconductor technologj. The 8 X 8-bit two’s complenment mul- tiplieriaccuniulator uses 4278 FET’s (1317 logic gates) and exhibits a multiplication time of 3.17 ns, the fastest jet reported for a multiplier of this tjpe. Yield on the hest wafer for the 4 x 4-bit and 8 x %bit circuits is 94 and 43 percent, respectively. A digital arithmetic suhsys- tenm has been demonstrated, consisting of seien GaAs IC’s: the 8 x &bit niultiplieriaccuniulator, two of the 4-bit ALti’s, three logical niultiple\ers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 31Hz.

I . INTROL~UCTION

IGH-SPEED and low-power digital IC’s are re- H quired for many high-performance military and com- mercial systems, including digital RF memories, digital signal processors, and fiber-optic communications. Nu- merous silicon-based technologies employing advanced processes are emerging [ 11-(41 and have significantly im- proved the performance of silicon devices. However, GaAs possesses inherent superiority in electron mobility and saturation velocity, high-temperature operation. and radiation hardness. In a research and development envi- ronment, GaAs digital circuits have clearly outperformed silicon circuits in power-delay performance, as exempli- fied by a GaAs D-type flip-flop that worked at up to 5.1 GHz and dissipated only 1.9-mW power 151. I n addition to offering outstanding performance, the gate complexity of the GaAs digital IC’s is increasing. A 16 x 16-bit mul- tiplier with 3168 gates [6] and a 16-kbit static RAM with 10’ devices [7] and 32-bit microprocessors [8] have been the largest GaAs logic and memory circuits reported to date. In recent years, the performance and yield of GaAs LSI circuits have increased drastically due to improved material quality and process technology [9]. GaAs IC’s

Manu\cript received August 8. 1988. H . P. Sinsh and R A . Sadlcr are w i t h the ITT Gallium Arsenide Tech-

nology Center. Roanoke. V A 24109. J . A . Irvine and G . E. Gorder are \vith thc ITT Defense Conimunica-

lions Division. Nutle) . N J 071 I O . IEEE Log Nuniber 8825247.

are thus becoming increasingly attractive for demanding high-speed applications such as digital signal processors.

High-speed parallel multipliers are key components in GaAs digital signal processor architectures that will be necessary to handle the signal-processing requirements of the next generation of military systems. Higher process- ing speeds will enable more complex algorithms to be ex- ecuted in real time and provide enhanced system capabil- i t y . This paper reports the measured performance of a high-speed 4-bit arithmetic and logic unit (ALU), 4 X 4-bit multiplier, and 8 x &bit multiplieriaccurnulator, all implemented in low-power GaAs EID direct-coupled FET logic (DCFL). The 8 x 8-bit multiplierIaccumulator is a two’s complement design that includes input and output latches, a 19-bit output with 3 bits of extension to handle accumulated products, control functions to clear the input and output, and a built-in self-test mode. The 4 x 4-bit multiplier is a parallel array multiplier designed with full- adders that provide essentially the same delays but at only 46 percent of the power and in less than 65 percent of the area required by the adders in the 8-bit design. In addi- tion, the measured performance of a GaAs digital arith- metic subsystem (DAS) that performs arithmetic and logic functions required in signal processing is reported. The DAS combines seven of ITT’s GaAs IC’s, including the 8 X 8-bit multiplieriaccumulator. two 4-bit ALU’s. three logical multiplexers. and a demultiplexer, using a com- mercially available prototype board. Arithmetic and logic operations are performed by the DAS on a two 8-bit words.

11. CIRCUIT DESIGN The ALU was designed with a bit-slice architecture and

is functionally compatible with the ALU portion of an in- dustry-standard 4-bit microprocessor slice. A block dia- grain of the ALU is shown in Fig. l . The ALU is an asyn- chronous design constructed of all NOR DCFL combinational logic. A 3-bit operation code selects one of five logic functions or three arithmetic (two’s comple- ment) functions. A carry look-ahead generator provides carry propagate and generate bits enabling the ALU to be used in a bit-slice design.

Both the 4 X 4 and 8 X %bit multiplexers were imple- mented in parallel designs to provide multiply times faster than could be realiLed with serial niultipliers. The 4 x

0018-9383/89/0200-0240$01 .OO Q I989 IEEE

4-bit unsigned binary multiplier uses an array adder that has a worst case delay of 15 gate delays. The array adder adds the partial products of the two input words. The par- tial products Rij = Y i X j are generated by inverting and then performing a N O R operation on the input bits. The multiplier consists of eight full adders and four half ad- ders. The adder delays to generate the sum and carry are t , = T,/ and t , = 27,/, where T,/ is the average delay through a gate. The worst case multiplication time, including the time to generate partial products, is 17 gate delays. A built-in self-test, activated by a self-test control bit, feeds back the most significant bit (MSB) of the product to tog- gle the input bits such that each of the output bits toggle between 0 and 1 . forming an oscillator. The delay of the self-test is 17 gate delays, so the self-test frequency of oscillation is an accurate measurement of the multiply time. The 4 x 4-bit multiplexer was implemented with a minimum switching FET gate width equal to 10 pm. The multiplier consists of 156 gates.

The 8 x 8-bit multiplieriaccumulator is a two's com- plement design that includes 8-bit latches on the inputs and a 19-bit latch on the output. On each negative clock transition, the input words are latched into, and the prod- uct of the previous input words is latched out of the mul- tiplier. The tree adder array has been designed to perform partial product summation and previous product accu- mulation. The adder array has been extended by 3 bits to allow larger sums due to accumulated products. Carry look-ahead adders (CLA's) have been used to reduce the delay in the adder array. A block diagram of the 8 X %bit multiplieriaccumulator is shown in Fig. 2 . The mode of the multiplier (multiplication or multiplication with ac- cumulation) is set by a control bit that determines whether the accumulator-select multiplexer feeds the previous product back to the adder array. A sign-bias technique was used in the 8 X 8-bit multiplieriaccumulator that re- sults in the partial product summation shown in Fig. 3. As shown, the partial products R 7 i and Ril are inverted

a, x , I Latch

Partial Product

Self Test

ACC Cntl

I I I I

Adder T I MSBJ

Fig. 2 . Bloch diagram of the two's complement 8 x 8-hit multiplier/uc- cumulator.

gates, while the second design uses 100 gates. The type of CLA used for each 4-bit slice depends on whether the carry o r sum is the critical signal in the worst case delay path. The multiplier delay, including the delay of the latches, the partial product generator. the adder array, and the setup time in the output latch, is 35 gate delays. The total gate count for the 8 X 8-bit niultiplieriaccumulator is 1317.

The 8 x 8-bit multiplieriaccumulator includes an in- novative built-in self-test that was used to verify the speed performance of the multiplier chips with on-wafer probe testing. The self-test was designed to toggle each of the output bits and to exercise as many of the gates as possible without adding any delay to the critical path. By increas- ing the clock frequency until the multiplier n o longer works, the self-test mode provides a technique t o verify the speed and functionality of each multiplieriaccuniula- tor chip. Also, to verify both modes of operation of the chip, the accumulator is toggled on and off during the self- test by feeding back an output bit to the accumulator con- trol. As shown in Fig. 2 . the MSB of the multiplier sum is fed back to the MSB of the Y input and the MSB of the multiplier product is fed back to the accumulator control. A multiplexer in both paths selects the feed back signals if the self-test is activated. The self-test is activated by setting the ST control to 1 and letting X = - 1 and Y = 43. Initially, the output P = X x Y = ( - 1 ) x 43 = -43 since the accumulator is off (controlled by clearing the output latch). This result sets the MSB of Y high ( Y =

-85) and sets the accumulator mode active. The next

242

SELl ; I I ;X r S E L 2

CLK 8 x &Bit

Acc 1,- Mult/Acc

IEEE TRANSACTIONS ON ELEC I RON DEVICFS. VOL 36 NO 2. FEBRUARY 19XY

rl 4[Ai ‘/ 1, 4f ~: 4-Bit 4-Bit

Yl Y6 Y5 Y4 Y3 Y 2 Y1 YO

X7 X6 X5 X4 X3 X2 X1 XO

RO6 R05 R04 R03 R02 R01 ROO

a R16 R15 R14 R13 R12 R11 R10

R26 R25 R24 R23 R22 R21 R20 - R37 R36 R35 R34 R33 R32 R31 R30

R46 R45 R44 R43 R42 R41 R40 - R57 R56 R55 R54 R53 R52 R51 R50

R67 R66 R65 R64 R63 R62 R61 R60

R77 R76 fi

1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

A18 A17 A16 A15 A14 A13 A12 All A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

P18 P17 P16 P15 P14 P13 P12 P11 P10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0

Fig. 3. Partial product summation from a sign-bias technique used in the 8 X 8-bit multiplieriaccumulator

Cntl 4 4

8

DMux 1

8, /

I F i S E L 4

I

CN

8,

’ * SEL3

t + OVR P CN + 4

Fig. 4. Block diagram of the digital arithmetic subsystem (DAS) .

block diagram of the DAS is given in Fig. 4. The DAS combines seven GaAs IC’s and performs arithmetic and logic operations on two 8-bit words ( R , S ). A 4-bit select code (SELI-SEL4) in combination with the 3-bit ALU operation code ( I ) and an accumulation control bit (ACC cntl) allows the DAS to provide multiplication (with or without accumulation), arithmetic and logic functions, or a combination of the two, i .e. , ( R + S ) X ( R + S ). Four different types of GaAs integrated circuits are incorpo- rated into the DAS: an 8 X 8-bit multiplier/accumulator, a 4-bit arithmetic and logic unit (ALU), an 8-bit 2 : 1 log- ical multiplexer (MUX), and an 8-bit 1 : 2 logical demul- tiplexer (DEMUX). Two 4-bit ALU’s are operated in par- allel, with the carry output of one ALU connected to the carry input bit of the following ALU, to allow 8-bit arith- metic and logic processing. The arithmetic and logic functions provided by the subsystem are listed in Table I .

To obtain high-speed operation at low power dissipa- tion, enhancement/depletion direct-coupled FET logic (E/ D DCFL) is used. For the switching EFET in the 4 X

4-bit multiplier, a minimum gate width of 10 pm is used, while a 20-pm-wide EFET is used in the ALU, multi- plexer, demultiplexer, and 8 x 8-bit multiplier/accumu- lator. Basic building blocks, such as gates, D-type flip- flops, adders, and drivers were optimized for maximum speed and minimum power dissipation, while keeping the switching point at the mid-point of the logic swing. Cir- cuits to provide a direct comparison of the speed and power dissipation of IO- and 20-pm switching FET design rules were included on the die. The complete 4-bit ALU, multiplexer, demultiplexer, 4 x 4-bit multiplier, and 8 X 8-bit multipliers were extensively simulated with an im- proved SPICE model, including all measured intercon- nect parasitics.

SINGH er al. : INTEGRATED CIRCUITS FOR A DIGITAL SIGNAL PROCESSOR

TABLE I DAS ARITHMETIC AND LOGIC FUNCTIONS

Function With or Without

R + S R - S S - R R OR S R AND S R AND S R EOR S R ENOR S R x S R x ( R + S )

-

R x ( R - $5) R X ( S - R )

S x ( R - S) S x ( S - R ) ( R + S ) x ( R + S ) ( R - S ) x ( R - S ) (S - R ) X ( S - R)

S x ( R + S)

Cin Cin Cin

ACCUM, ACCUM, ACCUM, ACCUM, ACCUM, ACCUM, ACCUM, ACCUM, ACCUM, ACCUM,

Cin Cin Cin Cin Cin Cin Cin Cin Cin Cin

111. FABRICATION PROCESS The circuits are fabricated with a titanium tungsten ni-

tride (TiWN) self-aligned gate process, as illustrated in Fig. 5. This fully planar process employs selective ion implantation into 2-in undoped LEC ybstrates. The sub- strates are first passivated with 850 A of plasma-depos- ited silicon oxynitride ( S O N ) , through which selective Si implants are performed for the EFET and DFET active channels. Th? SiON passivation layer is then removed, and a 2000-A layer of TiWN is deposited by reactive sputtering, as described elsewhere [ 101.

The TiWN layer is patterned into “T-gate” structures by liftoff of a Ni etch mask and subsequent reactive-ion etching. A self-aligned n+ implant is then performed, and after removal of the Ni mask, the wafer is capped with SiON and annealed at 810°C for 20 min. To maximize implant activation, we have optimized the composition and stress in the SiON anneal cap, which has a refractive indexn = 1.55.

After annealing, ohmic contacts are formed by liftoff and alloying of AuGe/Ni. The circuits are then com- pleted by defining twon levels of interconnect metalliza- tion, each using 6000 A of T i /Pd /Au patterned by lift- off. The interconnection levels are separated by 1 pm of polyimide, for low-capacitance crossovers. The sheet re- sistance of the interconnect metal is 0.06 Q/sq, and the via resistance for a 3 pm X 3 pm contact between first- and second-level metal is 0.09 Q .

IV. DEVICE AND CIRCUIT PERFORMANCE The EFET devices have a typical threshold voltage of

+O. 1 V, with a standard deviation of 30 mV over a 2-in wafer. Their average transconductance over a wafer is typically 230 mS/mm (measured at Vgs = +0.6 V, V,, = 1 .O V ) , with a standard deviation over the wafer typ- ically 3 percent of the mean. The DFET load devices have a typical threshold voltage of -0.5 V, with a standard deviation of 40 mV . Their wafer-averaged transconduc- tancc is typically 180 mS/mm.

All logic gates, D-type flip-flops, adders, and drivers

243

T-GATE FORMATION

j l

I \ Lp---- - ~- -2

SELF-ALIGNED n+ IMPLANT

1 I i 1 1 1 I 1

OHMIC CONTACTS AuGe i NI TIWN

FIRST-LEVEL INTERCONNECT TiPdAu 7

CONTACT VIAS

PHOTORESIST

SECOND-LEVEL INTERCONNECT TiPdAu, --

Fig. 5 . Self-aligned gate fabrication process.

TABLE I1 AVERAGE PERFORMANCE OF CIRCUITS USING 10- A N D 20-pm SWITCHIUC

FET’s

Circuit Using Using 10 pm EFETS 20-pm EFETS

Ring OSC. (FI = FO = 1): Supply Voltage (V) 1.2 1.2 Gate Delay ( p s ) 44 39 Power Diss. ( m w ) 0.23 0.44 Yield 97% 97%

supply Voltage ( v ) 1.2 1.2 Max. Input Freq. (GHz) 2.25 2.39 Power Diss. ( m w ) 1.9 3.7 Yield 97% 97%

Divide-by-Two Circuits:

were tested individually on wafers using probe cards. Wafer-averaged gate delay of 44 ps with a power dissi- pation of 0.23 mW/gate at a power supply voltage of 1.2 V is obtained for inverters with IO-pm-wide switching EFET’s (Table 11). Divide-by-two circuits using a D-type

flip-flop have an average maximum input frequency of 2.25 GHz and an average power dissipation of 1.9 mW, with a yield of 97 percent out of 35 die tested. Table I1 compares the performance and yield of circuits imple- mented with 10 pm versus 20 pm switching FET's. As shown in the table, the IO-pm-wide EFET provides a 40-percent lower power-delay product.

A . 4-bit Arithmetic and Logic Unit A microphotograph of the ALU is shown in Fig. 6 . The

ALU has 527 FET's in a chip size of 2.1 X 1.2 mm. High-frequency testing of the ALU's was done on-wafer using a high-frequency probe card and two test conditions that toggled all of the outputs. Functional circuit yield on the best wafer was 86 percent. Full functional testing of the ALU was performed at 50 MHz using an automated data generatorianalyzer test system. Operated under com- puter control, this system allows a bit-by-bit error analy- sis of output data compared to expected data. Full func- tionality of the 4-bit ALU was verified by exercising the 4096 possible input test vectors.

Fig. 7 shows the least and most significant ALU output bits (FO and F 3 ) responding to a change in the least sig- nificant bit (SO) of one of the input bits. Total DCFL ALU delays were 490 ps for F O and 780 ps for the F 3 output. Since the F 3 critical path involves 1 1 gate delays, this implies an average delay of 7 1 ps per gate. At a power supply voltage of 1.2 V , the average power consumption for the chip was 131 mW excluding output drivers, and 185 niW including output drivers. The ALU IC main- tained its GaAs output levels for input data rates up to 1.2 GHz. This is state-of-the-art speed and power perfor- mance for a 4-bit ALU [ 1 11.

The effect of power supply voltage variation on the maximum frequency of operation and power dissipation of the 4-bit ALU has been investigated. The DCFL cir- cuits operate over a wide variation in power supply volt- age. As illustrated in Fig. 8 , there is a minimal change in maximum frequency of chip operation due to power sup- ply voltage variation.

Fig. 6 . Mi( :rephotograph of the tabricated &bit A L U . Chip 1.2 mm.

Power Supply Voltage = I .2 V SO Frequency = 100 MHz FO Critical Path Delay = 490 p\ F3 Critical Path Delay = 780 p b

Power Dissipation = 13 I mW

is 2 .1 X

Fig. 7 . Waveforms o i ii typical ?-bit ALU

2.5 1

I" (1120

0 5 1 , I 1.0 1 5 2.0 2.5

400 3 E -

300 6 t- 4

200 0 E n

100

T O X

POWER SUPPLY VOLTAGE / V i

Fig. 8. Maximum frequency o f operation and power dissipation versus power supply ~ o l t a ~ e lo r the ?-bit ALU.

B. 4 x 4-hit Multiplier A microphotograph of the 4 X 4-bit multiplier circuit

IS shown in Fig. 9. It comprises eight full-adders, four half-adden. logic gates, and driver\, and use\ 503 FET's with a minimum switching FET width of 10 pm. High- speed te\ting was done on-wafer in the self-test mode. In this test mode, the multipliers showed a wafer-averaged critical delay of 1.1 ns, with an average power dissipation of 51 inW and a yield of 94 percent on the best wafer. Subnanosecond multiplication time (990 ps) was ob- tained at a power supply voltage of 1.2 V as shown in Fig. 10. The effect of power supply voltage variation on the multiplication time and power dissipation is shown in Fig. 1 1 . The multiplication time, equal to the critical path

shown In the figure, lS 940 Ps at a power Flg 9 Mlcrophotoglaph ot the tnbriidted 1 x ?-bit multiplier Chip \ I /L

I \ 0 97 x 0 97 111111 voltage of 2 .0 V . This is the fastest multiplication time

SlNGH er ( I / liu I bGRATl-D CIRCUITS FOR A DIG1 rAL SIGNAL PROCESSOR 245

c

Fig. I O . High-frequency waveforins of the 4 x 4-bit multiplier. The worst case delay shown is 990 ps with 63-mW power dissipation at V = 1.2 V .

reported for a multiplier using any semiconductor tech- nology [ 121.

C. 8 x 8-bit Multi~~liers/Accumulutor The microphotograph of the two's complement 8 X

8-bit multiplieriaccumulator chip is shown in Fig. 12. The 8 x 8-bit multipliers were tested on-wafer at high fre- quency using the self-test mode described previously. Fig. 13 displays the clock input and the product output bits PO, P 3 , and P 17. The maximum clock frequency of op- eration in this mode was 315 MHz, resulting in a multi- plication time of 3.17 ns, with an implied gate delay of 91 ps per gate. This is the fastest multiplication time yet reported for this type of a 8 X 8-bit multiplier [ 131. Table 111 summariLes the 8 x 8-bit multiplier/accumulator per- formance across the best wafer. The self-test functional yield was 61 percent and the spread of multiplication time across the wafer is minimal. Full functional testing using all 65 536 possible test vectors was performed on wafer for chips passing the self-test mode. The yield of fully functional 8 x 8-bit multiplier chips on a wafer was as high as 46 percent. The effect of power supply voltage variation on the minimum critical path delay and power dissipation of the 8 X 8-bit multiplieriaccumulator has been investigated. The DCFL circuits operate over a wide variation in power supply voltage, as illustrated by Fig. 14.

D. Digital Arithmetic System A photograph of the DAS 15 shown in Fig. 15. The

subsystem consists of seven packaged integrated circuits

Fig. 12. Microphotograph of the fabricated 8 X 8-bit multiplier/accumu- lator. Chip size is 4.20 X 4 . 1 5 min.

Fig. 13. High-frequency waveforms of the 8 X %bit nlultiplier/accumu- lator. The worst case delay is 3 .17 ns with 870-mW power consumption (excluding drivers) at V,,[) = 1.4 V.

3 . 3 , , 2.0 - U)

5 3 .2

5 >

E 3.1

3.0 1.4 1.6 1.8 2.0

z 0

1.5 2 a LI)

1.0 g a

3 0.5 2

W

POWER SUPPLY VOLTAGE (V)

Fig. 14. Critical path delay and power dissipation of the 8 X 8-bit m u l t ~ - plieriaccumulator versus power supply voltage.

TABLE I11 8 X 8-bit M L L I IPLIER/ACCLML L I I O R PFRFOKMZ\CF

Pa rame te r Average Slowest Fastest

Power Supply Voltage ( V ) 1.5 1.5 1.5

Power Dissipation ( m w ) W/O Output Drivers 983 935 993 With Output Drivers 1169 1118 1188

Max. Clock Frequency (MHz) 301 287 315

Multiplication Time ( n s ) 3.32 3.48 3.17

mounted in high-speed sockets on a commercially avail- able prototype board. High-speed signal routing between devices is accomplished with 50-0 0.034-diameter semi-

246 IEEE TRANSACTIONS ON ELECTRON DEVICES. Vol. 36 NO 2. FEBRUARY I Y X Y

Fig. 15. Photograph of the 8-bit digital arithmetic subsystem

I - ,

2 ns dlv I *Delay = 9 6 ns +

Fig 16 DAS high-frequency performance at a clock rdte of 325 MHz Meawred delay I S 9 6 ns

rigid coax cable or twisted pair wire. Approximately 120 high-speed transmission line interconnections were re- quired. The lengths of the interconnect lines were de- signed to satisfy the timing requirements of the individual chips and are connected using a daisy chain configuration. Termination resistors and decoupling capacitors were sol- dered on the bottom of the board.

The DAS was tested for functionality, delay, and speed of operation. All modes of operation of the DAS (multi- plication, arithmetic, logic, and combinations) were ver- ified by error-free operation when tested with over 200 vectors at 50 MHz. Fig. 16 shows the measured delay of the digital arithmetic subsystem in the ( R + S ) x ( R + S ) mode of operation. The input R word is set at 7, while the input S word toggles between 16 and 0 by toggling the S 4 input bit. With the ALU operation code set at ( R + S ) , the output of the ALU toggles between ( 7 + 16) = 2 3 , and ( 7 + 0 ) = 7. The output of the ALU is applied

to both inputs ( X , Y ) of the multiplier. Multiplier input words are latched in by the clock, and the corresponding ( R + S ) x ( R + S ) output is latched out one clock cycle later. The multiplier outputs toggle between ( 7 + 16) X

( 7 + 16) = 529 and ( 7 + 0 ) x (7 + 0 ) = 49. The delay between the S 4 input bit and the DAS output bit P 9 , after switching through the output logical MUX, is 9 .6 ns at a clock rate of 325 MHz. Power dissipation of the DAS without drivers is 1.4 W with a power supply voltage of 1.4 V.

V. TEMPERATURE EFFECTS The performance of FET's, logic gates, ring oscillators

and dividers has been verified over the military tempera- ture range of -55 to 125°C. Packaged circuits were func- tionally tested while being cycled in a temperature bath. Nearly identical results were obtained for several chips tested, and measurements made with rising and falling temperature sequences gave very similar results. The FET threshold voltage decreases with temperature at a rate of 1 mV/"C , and the temperature coefficient for the trans- conductance is - 1 X 10-3/"C. The mean temperature coefficients for the saturated drain current and source re- sistance are 1 X lO-'/"C and 1.5 x lO-'//"C, respec- tively.

The effect of temperature variation on the noise margin of a two-input NOR gate is shown in Fig. 17. The worst case noise margin of two- to ten-input DCFL NOR gates showed a temperature sensitivity of 1 mV/"C . From Fig. 17, it is concluded that the change in switching point with temperature ( - 0 . 6 m V / " C ) for a two-input NOR gate is adequate for the successful operation of an MSI circuit at

SlhCiH er ni.: lNTFGKATF,I) CIKCLIITS FOR A DIGITAL SIGNAL PROCESSOR 247

> -

* One Ramped A Both Ramped

HIGH

TABLE IV MEASURED A N D SIMULATED DELAY^ FOR ADDER, 4-bit ALU. A N D 4 X

.?-bit A N D 8 X &bit MULTIPLIERS

0.0 ' I I I I I -100 -50 0 50 100 150

TEMPERATURE ("C) Fig. 17. Temperature etfect on noise margin of a two-input hOR gate , for

two conditions: one input ramped. and both inputs ramped siniulta- neoualy .

up to 125°C. However, for reliable operation of LSI cir- cuits over the military temperature range, logic gates with decreased temperature sensitivity will be required, along with the use of temperature compensation circuitry. For example, an E/D logic gate now in development should provide a reduction of 50 percent in the magnitude of the temperature coeficients presented here. Further optimi- zation of the logic gates is in progress for LSI tempera- ture-tolerant circuits.

The temperature variation of propagation delay and power dissipation for two-input NOR gates has also been investigated. From - 5 5 to + 125"C, delay decreases by I O percent and power dissipation increases by 17 percent, so that power-delay product increases by only 4 pecent. The change in delay and power is nearly linear over the range from - 5 5 to + 125°C. D-type flip-flop frequency divider performance has also been investigated from -55 to 125°C. Measurements were taken on packaged devices with both rising and falling temperature sequences. An increase in maximum frequency of operation of about 20 percent is typically observed for these frequency dividers in going from -55 to + 125°C.

The circuits were also subjected to a high-temperature bias test. Packaged circuits were placed in an oven cham- ber, with electrical connections made to an external bias supply. A power supply voltage of 1.7 V was applied to the circuits while they were maintained at an ambient temperature of 150°C. The power supply current drawn by the circuit was recorded by a computer at hourly in- tervals. The circuits were periodically removed from the oven and tested for high-frequency performance. After a cumulative storage for 3000 h at 150"C, less than a 1- percent change in both high-frequency performance and power supply current has been observed for these circuits.

VI. DISCUSSION Ring oscillators and frequency dividers based on 10-

and 20-pm switching FET's have been designed, fabri- cated, and tested. As illustrated in Table 11, circuits with 10-pm minimum EFET width provide 40-percent lower power-delay product than those with 20-pm-wide FET's. These circuits were designed and laid out with a 3-pm line/3-pm space (6-pm pitch) design rule. Based on a 10-pm EFET minimum width and a 2-pm/2-pm (4-pm

Circuit

Adde c

4-bi t ALU

4x4-bit Multiplier

8x8-bit Multiplier w/o Accumulator

Measured Delay for Circuit Designed with Minimum EFET Width of

I 10 pm I 20 p m

I I

I

I

I I

247 ps I 222 ps

_ _ 1 780 ps

1.13 ns 1 --

_ _ I 2.63 ns

Simulated Delay for Circuit Designed with Minimum EFET Width of

I 10 p m I 20 pm

I

235 ps I 225 ps I

8 3 0 ps 1 810 ps I

1.15 na I -- i

2.66 ns I 2.58 ns

pitch) design rule, it is projected that the circuits would have about half the power dissipation and the same max- imum frequency of operation without any reduction in yield.

The performance of adders, 4-bit ALU's, and 4 X 4-bit and 8 x 8-bit multipliers were simulated. The SPICE pa- rameters were evaluated from the FET measurements made on wafers from which circuits were characterized. The simulated results along with the wafer-averaged mea- sured data are summarized in Table IV. The agreement between measured and simulated results is within 5 per- cent. The table also confirms that the circuits based on an EFET with a 10-pm minimum width would have half the power dissipation and the same maximum frequency of operation.

The 4-bit ALU, as shown in Fig. 7, dissipates 131 mW (61 mW if 10-pm EFET's were used), with a typical worst case delay of 780 ps. The critical path for the 4-bit ALU consists of 11 gates, which translates into an aver- age delay of 71 ps for each loaded gate in the path. The performance of the ALU compares well with the earlier reported results: 1.4 ns with 350-mW power for a 4-bit ALU [ 111 and 800 ps with 2.6-W power for an 8-bit ALU

The critical path delay for the 4 X 4-bit multiplier is 990 ps, with a power dissipation of 63 mW. Dividing by the number of gate delays in the critical path, 17, the av- erage gate propagation delay is 58 ps, which is one of the fastest gate delays obtained from a 4 X 4-bit multiplier. In the design of this multiplier, a 2-pm X 2-pm wiring design rule was used, and the minimum width of the switching EFET was 10 pm. The critical multiplication time of 990 ps with 63-mW power dissipation (62-pJ power-delay product ) compares favorably with the pub- lished results of 1 .6 ns, 48 mW, (77 pJ) [12] and 2.5 ns, 40 mW, ( 100 pJ) [ 151. We also observed a minimum crit- ical delay of 940 ps for a 4 x 4-bit multiplier at = 2.0 V, which is the fastest multiplication time reported in the literature 1161.

The performance of the 8 x 8-bit multiplier/accumu- lator is compared to that of previously reported 8 X 8-bit multipliers in Table V. The best performance observed for the 8 x 8-bit multiplier/accumulator is a total delay of 3.17 ns with power dissipation of 870 mW (435 mW

1141.

Ib.EE TRANSAC IIONS O N E L t C T R O K DF-VICES. VOI,. 7 6 . S O . 7 . FEBRU-\RY I ' jXY

TABLE V 8 X &bit M L L T I P L I F R ~

Au tho r s Device Speed Power

Gonoi et.al JFET GaAs multi- without acc. 876 mW 1986 I171 plier/accumulator 6 ns

1816 ga5es 182 ps/gate 15.5 mm chip

Cirillo et.al MODFET GaAs 3.2 ns 1.9 w 1987 I 1 8 1 mu1 t ipl je r 70 ps/gate 1.4 mW/gate

10.5 mm chip

Delhaye et.al MESFET GaAs 3.0 ns 330 mW 1987 [131 multi lier 115 ps/gate 0.41 mW/gate

12 mm' chip

washio et.al SICOS silicon 2.7 ns 900 mW 1987 [ll multiplier

2017 transistors

Present MESFET GaAs with acc. with acc. multiplier/ 3.17 ns 870 mw accumulator 1317 gaies 17.4 mm chip 91 ps/gate 0.66 mw/gate

MESFET GaAs without acc. without acc. multiplier 2.6 ns 600 mW (extracted)

with 10-pm EFET's) at a power supply voltage of I .4 V . This delay includes the critical path delay in both the mul- tiplier and the accumulator. In order to compare the per- formance of the 8 x &bit multiplieriaccumulator to other devices. some of which do not include inputioutput latches or an accumulator, the performance of our device without latches and accumulator has been extrapolated in Table IV to be 2.6 ns. The extracted power-delay product per logic gate ( 9 1 ps x 0.66 mW = 60 f J ) is the lowest re- ported for DCFL gates on an LSI chip.

VII . CONCLUSION A 4-bit arithmetic and logic uni t , 4 x 4-bit multiplier,

and 8 x &bit multiplieriaccumulator have been designed, fabricated with GaAs EID self-aligned gate technology, and tested for use in advanced GaAs digital signal pro- cessors. The circuits were evaluated on-wafer using high- frequency probe cards with a yield on the best wafer of 83 percent for the 4-bit ALU, 94 percent for 4 x 4-bit multiplier, and 43 percent for 8 X 8-bit multiplieriaccu- mulator. The 4-bit ALU can handle data rates up to 1.2 GHz and dissipates only 131-mW power. The multipli- cation time for 4 x 4-bit array multiplier is 940 ps at a power supply voltage of 2.0 V , which is the fastest mul- tiplication time reported for a multiplier using any semi- conductor technology. The 8 X %bit two's complement multiplieriaccumulator consists of 4278 FET's or 13 17 logic gates and provides a multiplication time of 3.17 ns, implying a propagation delay of 91 ps per gate. This is

the fastest multiplication time yet reported for a multiplier of this type. Furthermore, circuits fabricated with a I 0-pm-wide switching EFET exhibited a 40-percent lower power-delay product than those fabricated with a 20-pm- wide EFET. Based on measured results, it can be pro- jected that the 8 x 8-bit multiplier, if fabricated with a I0-pm-wide EFET, would dissipate only 500 mW of power at a power supply voltage of 1.5 V , and show little degradation in speed. These measured results demonstrate state-of-the-art high-frequency performance at extremely low power dissipation. The circuits were also shown to operate over a wide variation in power supply voltage and temperature.

To demonstrate the integration of GaAs IC's for high- speed digital signal processing, an 8-bit digital arithmetic subsystem (DAS) has been assembled and tested. The DAS comprises seven GaAs DCFL IC's and performs arithmetic and logic operations on two &bit words. The DAS was tested for functionality, speed. and delay. It op- erated to clock frequencies as high as 325 MHz. the max- imum clock frequency of the multiplier, with a corre- sponding delay of 9 . 6 ns.

REFERENCES [ I ] K . Wa\hio. K . NaLarato. and T . NaLamura. "2.7 n\ 8 X %hit par-

allel array multiplier using sidewall base contact structure." / F E E J . Solit/-Stnre Crr-c.itit.5. v o l . SC-22. pp. 613-614. 1987.

12) J . Y. Lee. H . L . GarLin. and C. W . Sla)man. "A high-speed high- density silicon 8 x X - h i t parallel multiplier." / E E E J . Soiitl-Srcirc' C i r t x i t ~ . vol SC-22. pp. 35-40, 1987.

S I N G H e r ( I / . INTEGRA I E D CIRCUITS FOR A DIGITAL SlG&.,il, PROCESSOK

P. C. Hunt and M . P. Cooke. "Process HE: A highly ad\,anced trench isolated hipolar technology for analogue and digital application\." in Pro<.. IEEE Cii.\/ott/ I t t / r g ~ - t i t c ~ t / Circuit.\ Cotif:. 1988. pp. 2 2 . 2 . 1- 22.2.4. T . Yamaguchi. Y . C S . Yu. E. Lane. J . Lee. E . Patton. R . Herman. D. Adrendt, V . Drohny. and V . Garuts. "70 ps ECL gate Si bipolar technology using horo\enic-polq process with coupling-base i n - plant." in Proc.. /€Et-- Cii.\totti / t i r c g i - i r / t ~ c / Cirwirt Cotrf:. 1988. pp. 22.3.1-22.3.4. H. P. Singh. R . A . Sadler. A . E. Geisaberger. W . J . Tanis. and E. R . Schtneller. "High-speed. low-power GaA\ programmable counters lor \ynthesizer applications," IEEE GtiA.\ IC Swrp. T ~ I . Dig.. 1987.

Y . Nnha)ama. K . Suynma. H . Shimiru. N. Yokoyama. H . Ohnishi. A. Shihatonii. and H . Ishikawa. "A GaAs 16 X 16-bit parallel niul- tiplier." IEEE J . Solit/-Sttrte Circ.~rits. vol . SC-18. pp. S99-603. 1983. Y . Ishii. M . Ino. M. Idda. M. Hirayania, and M . Ohmori. "Process- ing technologies for GaAs mei i ior ) LSl's." i n / L E E GtrA\ IC S ~ i p .

D . Harrington. J . Bolen. J . Fay. W . Gee. C . Lowc. K . Nguyen. T . Nicaleh. J . Reeder. Y . R o h . G. Trocger. and C . Vogcl\ang. "A GaAs 3?-bit RISC IiiicroprocessOr." in f E t E GuA.5 IC .Yw/p T d ! . Di,q.. 1988. N. Kobayashi. S h'otomi. M. Su7itki. T. Tsuchiya. K . Nishiuchi . K . Odani. A. Shihatonii, T . Mimura, and M. Ahe. "A fully operational I Kbit H E M T static RAM." in IEEE GoA.7 IC S ~ i p . Tc,c./~. Dig.. 1985. pp. 207-210. A . E. Geisshergcr. R . A . Sadler. M. L. Balzan. and J . W. Crites. "TiW nitride thermall) stable Schottky contacts to GaAs: Character- ization and application to SAG FET fabrication." J . Vrrc.. S C , ~ . T d - rial. B. \ol . 5 . pp. 1701 - 1706. No\ .!lkc R. E. Oettel. M . D. Upton. R . Eden. F Lee. and P. Lau. " A &bit gallium arsenide ALU designed with a compiler." in Proc,. I k E E C~J. \ /OJJJ Irrtc~,yrtrrcr/ Ci~ -~ . i ( / t \ CfitfJ. 1987. pp. 170- I73 A . R . Schlier. S. S. Pei. N. J . Shah. C . W . Tu . and G. E. Mohoney. " A high-speed 4 X 4-bit parallel multiplier using selectively doped hetci-ostiucture transistor\." IEEE Gir'4.s IC S ~ t t ~ p . T c c ~ . Dis . . 1985.

E. Delhaye. C . Rocher. M . Fichelson. and 1 Lecuru. "A 3 . 0 ns. 330 niW 8 X 8 GaAs Booth ' \ multiplier." in IEEE GtrA.! IC Svmp. Tcdi. Dig . . 1987. pp . 249-252. M . Ino. T . Takada. M . Ida. and N. Kato. "High-speed GaAs &bit ALU." Triiti.5. Iti.\t . t / r i . t r o ! i . Coti/ttii(ti. E J J ~ . J ~ I ~ O I J , Siw. E. \oI.

E. Delhaye. C . Rocher. J . Baelde. J . Gihereau. and M. Rocchi. "A 2 .5 -ns . 40 mW. 4 x &hit GaA\ multiplier in two's complement mode." IEEE J . Solicl-Stntc~ Ciri.itir.\. v o l . SC-22. pp. 409-414. 1987. K. Ka7i i . Y Watanabe. M . Suruhi. 1. Hanyu. M . Kosugi. K . Odani. T . Mimura. and M. Ahe. "A 40-ps high electron mobility transistor 4.1 K fa te array." IEEE J . Solicl-Sttrrr Circuits. \wl. 23. pp. 485- 48Y. 1988. K. Gonoi. I Honbori. M. Wada. K . Tog;i\hi. and Y. Kato. "A GaAs 8 X 8-hit miiltiplier~;iccumulator using JFET DCFL." / P E E J . So/ic/- S t c i t c ~ C~rc.irit.\. \ o l . SC-21. pp. 523-519. 1986. N. C . Cirillo. J r . . D . K . Arch. P J . Vold. B. K . Bet i . 1. R . Mactag- gart. and B . L . Grung. "8 X 8-bit pipelined parallel multiplier u t i - lizing sell-aligned gate n L-( AI. Ga )As/ 'GaAs MODFET IC technol- ogy." in I E E t G t A IC .Sv!ty). 7ec.h. Di,g.. 1987. pp. 257-260.

pp. 269-272.

T(.C/J. Din.. 1984. pp. 121-124.

1987.

pp. 91-93.

E69. pp. 302-304. 1'986.

where he taught graduate courses in \olid-\tate physic\ and w a s engaged i n reseat-eh ot the electrical properties o l metal-insulator and ineta-seiiii- conductor de \ ices . From 1978 to 1982. he & a \ associated h i t h Wright- Patterson Air Force Ba\e. D a y t o n . O H . a\ a Senior Visiting Scientist. &hcrc he was invol\,ed in the re<enrch and development of high-speed digital cir- cuits utili7ing GaA\ insulated-gate FET's . He joined the ITT Gallium Ar- senide Technology Center. Roanohe. VA. in 1982 a s Senior Principal Sci- ent i \ t . I n his current position iis Technical Stall Fellow. he is responsible for the debign and testing o t high-$peed GaAs digital circuits. He is author or co-author of more t h a n 80 research papers and technical reports.

Dr . Singh was awarded a Certificate o f Recognition by the Electron Mi- croscopy Society of America in 1972 for Be\t Phlsical Science Applica- tion. "An Electron Microscope Study o f Vapor-Liquid-Solid Grouth i n I n and Sn Thin Films."

Robert A . Sadler ( S 76-M 84) w d s born 'it Fort C,iinphell KY. o n Fchruan I 1954 He ~ e t s i \ e d the B S d n d M S degiec\ in c l t ' i t i i c d l engineer ing trom North Carolina Stdte Uni \e i \ i t \ R,i

le iyh. i n I978 .ind 1980 rc\pecti\ely m d the Ph D degiee i n e l e c t i i c a l engineering troiii Col nel l Uni \e r \ i t \ Ith,ica NY. in I984 Hi\ doctor'il research was o n \ubiiiicroiiieter~gate self-aligned GaAs MESFET's tor digital IC's,

While dt Cornell. he \\:is a Houard Hughe\ Doctoral Fello\b at the Hushes Research Laboro-

tories. Malibu. C A . where he ho rkcd o n electron-beam lithography and the early development o f retractor) \elt-dligncd gate fabrication technol- ogy. In 1983. he joined the ITT Gallium Arsenide Technolog) Center. Roanoke. V A . w i t h respon\ibilit) tor GaA\ materialh and self-aligned gate pi-oces\ development. I n his current position a \ Principal MTS. hc i\ rc- \pon\ible t o r digital IC fabrication. parametric te \ t dc\elopiiicnt. and ;id- \anted d i ~ i t a l device dcvclopinei i t . He has authored or coauthored more than 30 technical puhlications o n GaAs device\ and material\.

Dr . Sadler 15 a nicniher ot the American Vacuum Societ)

*

.lanies A . Ir\ine (S '67-M'81) n r i \ horn in Glen Ridge NJ. i n 1947 He reiei\ed the S b E de grec (with Honois) trom the Uni\er \ i ty 0 1 Dela- b a r e in 1969 ,ind the S E E degree trtrnl l l c u Yorh Uni\cr\ i t) in 1971

He Ioincd ITT 9 Delsn\c Coiiiiiiunic'ition Di- \ i \ ion i n 1969 \\here he ~ d s rc\pon\ihle tor the design of microL\a\flc active circui ts a n d \tihsys- tern\. He later m a \ in \o l \cd in the de\ ign 01' mil-

c components tor :id\ ;inced teiiis. Since 1980. he h a \ hccn

involved in the developnient of CaA\ riionolithic integrated circuits. T h e w have included circuits lor niicrowa\e and Iiii!liiiicter-\liivc \j \tern\. high- data circuits for i i i i c ro \ \a \c a n d n i i l l i i i i e t c r -uavc \!stein\. hish-data rate optical \)stenis. and nio\t rccentlh high-speed signal procc\\ ing.

Ilausila P. Singh ( M 81-SM 88) was horn in

Vaian,i\i Indict. in 1942 He received the B S de gree m i th honor\ the M S degree in phy\ ic \ and the Ph D degree in \olid-\tate ph)sic\ t rom the B,in,irds Hindu Unt\er\ i ty. Indi'i. in 1961. 196.5 m d 1968 iespecti \el)

M i t h the Birla In\titute of Technolog) and Sc ience Pilani India trom 1968 to 1969 u h e r e he taught i o u r w 5 in p h j \ i c < He wed\ a Postdoctoral Re\e,irch Fellow 'it the M,i\\,ichu- \c t t \ In \ t i tu te ol Technolog) Cainhridgc. and 'it

He

the Uni\er\ i t) ol Southern CaliIoini,i Lo\ Angcle\ troni 1969 to 1972 He \pent \ i x )edr\ 'i\ a Readet i n Ph)stc\ 'it Punlahi Uni\ci \ i t ) India

Greta E. Gorder %as h o r n in Oah Ridge. TN. o n hln! 27. 1959. She received the B.S. degrcc trotii Broun Uni \c r \ i t y . Providence. RI . and the

tree Irom Fairleigh Dlckin\on Uni \c i -s i t ) . Ruthertord. NJ. in ineering in 1981 and 1985. rcspccti \clq.

She h a \ hecn associated \< i th the ITT Defense Ci>iiitiiuiiication Di\ !\ i t in

since 1981 and currentl) hold\ the po\irion ot Senior Member Technical Stan in the Ad\anccd De\ign Group. She h a \ been re\pon\ihle l o r the de- \ign and devclopiiicnr o f microw ;I\ e component\ tor coi~~iiiiiniciitioii~ equipment. Thi\ h a \ inc luded both ~inali ip ond digital GiiA\ monolithic in- tegrated circuits. ;I\ \\ell a s con\ent ion; i l i i i icro\\a\e component \ . Most reccntlq. \he h a \ been respoii\ible f o r the de\ign o f ;i GaAs multiplier iiccuiiiiiliitor and ;I static R A M iniplementetl in the direct-coup!cd FE-T lopic fnii i i ly. She I \ the co-author o f S I Y paper\ co \e r ing iiiicro\\;i\c coiiiiiiuni- cations and G;rAs IC dc\ ign mt l cle\clopmcnt