Gate oxide and threshold voltage reliability ... · 3/7/2018 · the semiconductor substrate...

Gate oxide and threshold voltage reliability considerations for SiC MOSFETs

Dr. Thomas Aichinger, Infineon Austria AG

Dr. Peter Friedrichs, Infineon Technologies AG

12018-03-07 no marking Copyright © Infineon Technologies AG 2018. All rights reserved. Infineon Proprietary

Agenda

General introduction gate oxide challenges

Gate oxide reliability

MOS channel performance

Threshold voltage stability

Conclusions

1

2

3

4

5

Si MOSFET vs. SiC MOSFET


Agenda





Conclusions

1

2

3

4

5



Introduction: What is the GOX for and what are the (main) challenges?

What are the reliability challenges?

– Time-Dependent-Dielectric-Breakdown (TDDB) fatal device failure

– Bias Temperature Instability (BTI) gradual drift of VTH

• Gate oxide (GOX) isolates the gate from source/drain

• Allows an inversion channel to form when applying a gate bias > VTH

• Is made of amorphous SiO2

p-

n++ n++

S D

G

Body

GOX

Rch

What are the performance challenges?

– Limit the channel resistance of the device fulfill RONxA SPECs

M: The GOX bulk and the GOX-SiC interface must be engineered in a way to fulfill certain reliability and performance requirements

Poly


Agenda





Conclusions

1

2

3

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Why does the GOX require special attention in SiC MOSFETs?

1. SiC has a larger bandgap (1.1eV Si vs. 3.2 eV SiC)

enhanced tunneling

higher fields in blocking state

Baliga, SiC power devices 2005

higher risk for early GOX breakdown

Senzaki et al, APL 2006

2. SiC operates at higher internal fields (0.3 MV/cm Si vs. 3.0 MV/cm SiC)

3. SiC has higher defect density in the substrate and in the GOX


1. Larger bandgap of SiC

electron injection

10 MV/cm

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

0 1 2 3 4 5 6 7 8 9 10 11

I [A

]

EOX [MV/cm]

65nm SiO2 on SiC

BUT: The intrinsic breakdown field of SiO2 is still >10MV/cm

The larger bandgap enhances tunneling currents through the gate oxide

hole injection

At the same oxide field, the gate leakage current is higher in SiC/SiO2 systems

Q: Why is that?

A: Because the FN-tunneling

barriers for electron and hole

injection are decreased

M: TDDB in thick oxide devices is rather field driven and not so much determined by the tunneling current

4.6 eV

5.5 MV/cm

IgVg characteristics of SiC MOSCAPs with 65nm GOX


2. Higher blocking capability of SiC

The gate oxide of SiC MOSFETs needs to be protected from the drain potential

𝐸𝑆𝑖𝑂2 =𝜀𝑆𝑖𝐶𝜀𝑆𝑖𝑂2

𝐸𝑆𝑖𝐶

A1: Using 𝜀𝑆𝑖𝐶 ≈ 10; 𝜀𝑆𝑖𝑂2 ≈ 3.9, the field in the SiO2

may reach up to 7.5MV/cm

Measures limiting the field in the GOX in blocking mode (high VDS)?

• Implant deep p-regions below the GOX (JFET)

• Overdesign EPI layers

• Limit negative gate voltage in blocking mode

M: All measures which reduce the GOX stress in blocking mode increase the RON (key trade-off for SiC MOSFETs)

Q1: Assume that the field in the SiC near the

GOX is close to breakdown (3MV/cm). How

high would be the field in the adjacent GOX?

The field is even higher at curved structures


3. Higher defect density of SiC

Substrate defects, particles, process variations, ect. may cause GOX distortions

(“extrinsics”) which decrease the lifetime of affected devices early breakdown

Oxide thinning model:

Any distortion in the GOX can be described as a local oxide thinning

A1a: The GOX always fails at its weakest link

Q1: Why are extrinsic defects in the GOX so critical?

A1b: One doesn’t know if a device is affected or not

The thinner the GOX, the higher is the electric field at a certain gate bias and the lower is the time to breakdown


1 chip life


intrinsic branch

Bulk propertyextrinsic branch

DD related

𝑙𝑛 − 𝑙𝑛 1 − 𝐹

𝑙𝑛 𝑡

Example: 10.000 devices were stressed to end of life:

M: The GOX failure probability is typicallydetermined the extrinsic branch

M: The Weibull distribution is a “weakest link distribution” named after the Swedish mathematician Waloddi Weibull.


The failure probability of Time-Dependent-Dielectric-

Breakdown (TDDB) is described by the Weibull distribution.


How does the Weibull plot look like for SiC and Si-MOSFETs (same area and GOX thickness)?

same intrinsic oxide reliability

M: It is (by today) unclear how to decrease the extrinsic GOX defect density in modern SiC MOSFET devices (2-20mm2) well below 1% at the end of process BUT <0.001% (10ppm) or even < 0.0001% (1ppm) is needed

M: At end of processing (EOP) SiC MOSFETs have a much larger extrinsic defect density failure probability can be up to 4 orders of magnitude higher

1 chip life


Agenda





Conclusions

1

2

3

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5



Measures to improve the GOX reliability of SiC MOSFETs

› Minimize the number of devices with critical extrinsics at the EOP

Continuously improve substrate defect density

Continuously improve processing related defect density

› Limit the gate oxide field in blocking mode

Use proper shielding e.g. buried p-implants (at the cost of RON)

› Limit the gate oxide field in on-state

Choose on-state gate voltages as low as possible (at the cost of RON)

› Avoid voltage spikes in the application

M: It is not required to produce hardware with excellent reliability as long as one can screen defective parts and deliver hardware with excellent reliability

This is all nice but by far not enough!

Q: What else can be done to improve GOX reliability?

A: Electrically screen devices with critical extrinsics


Agenda





Conclusions

1

2

3

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5



Why is the MOS channel in the focus of improvement for SiC power MOSFETs?

textbook MOSFET physics

1. Increase chip area (W) layout (large chip) cost, yield

2. Decrease channel length (L) change channel implant DIBL, punch through

3. Decrease gate oxide thickness (tOX) reduce oxidation time GOX reliability

4. Increase device use voltage (VGS,use) change data-sheet GOX reliability

5. Decrease device threshold voltage (VTH) reduce channel dose re-turn on, switching losses

6. Increase channel mobility (µn) limit surface roughness

use the best crystal plane know how, VTH stability?

optimize interface passivation

µn

› How can the channel resistance be improved?

Parameter Process change Drawback

M: The best way to reduce the channel resistance is to improve the inversion carrier mobility (only 10% of bulk) improve SiC/SiO2 interface quality

RCH can make up to 50% of the total RON RON = $$$


Why is it so hard to make a good MOS interface?

Surfaces and interfaces are more complex because they break the symmetry of the periodic crystal

Wolfgang Pauli

Q1: What makes the SiC/SiO2 interface

particular challenging?

• more room for electrically active defects

• carbon has to be removed during oxidation

• additional point defect types exist

• interface passivation is less efficient

M: Even after passivation, the interface and near oxide trap densities at the SiC-SiO2 interface are ≈100 times larger than at the Si-SiO2 interface

› Why do point defects at the interface affect the inversion carrier mobility?

– Inversion carrier are trapped can no longer conduct current

– Trapped charges act as Coulomb scattering centers reduced

drift mobility

God made the bulk;

surfaces were

invented by the devil

… SiC/SiO2 was

invented by the

devils’ mother-in-law


How does SiC/SiO2 interface passivation work?

GOX before POA

SiCSiC

› The state-of-the-art passivation gas is Nitric Oxide (NO)

› During POA, NO diffuses into the GOX and gets cracked

› N passivates interface defects while O oxidizes the SiC

› During oxidation excess carbon has to be removed (SiC SiO2)

NO POA

› Nitrogen is known to passivate defects at the SiC/SiO2 interface

M: The key to get a nicely passivated interface is to keep oxidation and passivation in balance


Agenda





Conclusions

1

2

3

4

5



Threshold voltage stability considerations

1. What is Bias Temperature Instability (BTI)

2. What are the consequences for the device?

3. Difference extrinsic vs. intrinsic BTI (SiC vs Si MOSFETs)

4. The 2 components of intrinsic BTI in SiC MOSFETs:

– fully reversible VTH hysteresis

– more permanent VTH drift


› Extrinsic BTI: due ionic contaminations (Na, K)

– during device fabrication

– from outside during normal device operation

› Intrinsic BTI: depends on the physical properties of

the SiC/SiO2 interface

– the density of interface states and border traps

– their ability to exchange charge carriers with the semiconductor substrate

Extrinsic vs. intrinsic BTI

M: Extrinsic BTI is the same for Si and SiC MOSFET devices

M: Intrinsic BTI

‼ larger for SiC MOSFET devices higher defect density at the SiC/SiO2

interface and near-interface oxide region

‼ critical for SiC MOSFETs degradation of the RON (+∆VTH)

can be accelerated by voltage and temperature

follows a power law like time evolution and is therefore very well predictable

Na+, K+


Intrinsic BTI in SiC MOSFETs

› In SiC-MOSFETs 2 intrinsic BTI components exist

– fully reversible threshold voltage hysteresis (∆𝑉𝑇𝐻𝐻𝑌𝑆𝑇)

– more permanent threshold voltage drift (∆𝑉𝑇𝐻𝐵𝑇𝐼)

-5V

15V

-5V

15V

0h 10h 1000h

time

-5V

15V

VTH response

gate voltage

. . . . . . . . . . . .


Fully reversible VTH hysteresis

› Possible origin of the VTH hysteresis

– Charging and discharging of traps at SiC/SiO2 interface

› Size of the effect

– SiC MOSFETs: up to 5V

– Si MOSFETs: several mV (due to the much lower Dit)

› Application relevance

– Actively supports switching

– No negative aspects seen

hysteresis is proportional to average Dit


More permanent VTH drift

› Possible origin of the more permanent VTH drift

– Border traps within the SiO2 exchange carriers with the SiC via a thermodynamic energy barrier (∆𝐸)

› Size of the effect

– SiC MOSFETs: <400mV within 1000h DC stress @ VGS,max & TJmax

– Si MOSFETs: <40mV within 1000h DC stress @ VGS,max & TJmax

› Application relevance

– Permanent VTH and RON drift risk for parameter drift out of SPEC

Border trap candidate: stretched Si-O bonds near the semiconductor interface

A1: The conduction band minimum of Si is

0.5eV lower larger tunneling barrier

Q1: Why is it much harder to charge the same

oxide traps in Si MOSFETs?El-Sayed et al.,“Nature of intrinsic and extrinsic electron trapping in SiO2”, PRB, 2014


› Countermeasure

– Reduce density of border traps effectively

Agenda





Conclusions

1

2

3

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5



Conclusions

› Gate oxide reliability considerations

• Intrinsic reliability: similar for SiC and Si MOSFETs

• The GOX of SiC MOSFETs needs to be shielded from the drain potential in blocking mode

• SiC MOSFETs have much larger extrinsic defect density (EOP)

Si-like GOX reliability achievable by extrinsics screening

Screening only efficient using thicker bulk gate oxide (Ebr >> Euse)

› MOS channel considerations

• The channel resistance of SiC MOSFET significantly contributes to the total RON

• Point defects at the SiC/SiO2 interface degrade the channel mobility of SiC MOSFETs

• NO POA reduces point defect density thereby improving the channel mobility

› Threshold voltage stability considerations

• Extrinsic VTH instabilities: the same for SiC and Si MOSFETs

• Intrinsic VTH instabilities: higher for SiC MOSFETs & consist of 2 different components

a fully reversible VTH hysteresis (stable over time)

a more permanent BTI drift reduce border trap density


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Gate oxide and threshold voltage reliability ... · 3/7/2018 · the semiconductor substrate...

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