RT8800/B

1DS8800/B-08 April 2011 www.richtek.com

General DescriptionThe RT8800/B are general purpose multi-phasesynchronous buck controllers dedicating for high densitypower supply regulation. The parts implement 2, and 3buck switching stages operating in interleaved phase setautomatically. The output voltage is regulated andcontrolled following the input voltage of FB pin. With sucha single analog control, the RT8800/B provide a simple,flexible, wide-range and extreme cost-effective high-density voltage regulation solutions for various high-densitypower supply application. The RT8800/B multi-phasearchitecture provide high output current while maintaininglow power dissipation on power devices and low stresson input and output capacitors. The high equivalentoperating frequency also reduces the componentdimension and the output voltage ripple in load transient.

RT8800/B implement both voltage and current loops toachieve good regulation, response and power stagethermal balance. The RT8800/B apply the time sharingDCR current sensing technology newly as well; with sucha topology, the RT8800/B extract the DCR of outputinductor as sense component to deliver a more preciseload line regulation and better thermal balance capability.Moreover, the parts monitor the output voltage for over-current and over-voltage protection; Soft-start andprogrammable under-voltage lockout are also provided toassure the safety of power system.

Features5V Power Supply Voltage2/3-Phase Power Conversion with Automatic PhaseSelection (RT8800 : 2/3-Phase, RT8800B : 2-Phase)Output Voltage Controlled by External ReferenceVoltagePrecise Core Voltage RegulationPower Stage Thermal Balance by DCR CurrentSensingExtreme Low-Cost, Lossless Time Sharing CurrentSensingInternal Soft-startHiccup Mode Over-Current ProtectionOver-Voltage ProtectionAdjustable Operating Frequency and Typical at300kHz Per PhasePower Good indicationSmall 16-Lead VQFN Package (For RT8800 only)RoHS Compliant and 100% Lead (Pb)-Free

ApplicationsDesktop CPU core powerLow Output Voltage, High power density DC-DCConvertersVoltage Regulator Modules

General Purpose 2/3-Phase PWM Controller for High-DensityPower Supply

Marking InformationFor marking information, contact our sales representativedirectly or through a Richtek distributor located in yourarea.

Ordering Information

Note :

Richtek products are :

RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.

Package TypeQV : VQFN-16L 3x3 (V-Type)S : SOP-16Lead Plating SystemP : Pb FreeG : Green (Halogen Free and Pb Free)

RT8800/B

2-Phase2/3-Phase

RT8800/B

2DS8800/B-08 April 2011www.richtek.com

Pin Configurations(TOP VIEW)

VQFN-16L 3x3

RT8800

SOP-16

RT8800B

Functional Pin Description

DACFBNegative input of internal buffer amplifier for referencevoltage regulation. The pin voltage is locked at internalVREF = 0.8V by properly close the buffer amplifier feedbackloop.

DACQThe pin is defined as the output of internal buffer amplifierfor reference voltage regulation.

FBThe pin is defined as the inverting input of internal erroramplifier.

DVDThe pin is defined as a programmable power UVLOdetection input. Trip threshold = 0.8V at VDVD rising.

COMPThe pin is defined as the output of the error amplifier andthe input of all PWM comparators.

PIThe pin is defined as the positive input of the error amplifier.

RTSwitching frequency setting. Connect this pin to GND witha resistor to set the frequency.

ICOMMONCommon negative input of current sense amplifiers for allthree channels.

PGOODOutput power-good indication. The signal is implementedas an output signal with open-drain type.

ISP1 , ISP2 , ISP3Current sense positive inputs for individual converterchannel current sense.

PWM1 , PWM2 , PWM3PWM outputs for each phase switching drive.

VDDChip power supply. Connect this pin to a 5V supply.

GNDChip power ground.

Exposed Pad (17) (RT8800)The exposed pad must be soldered to a large PCB andconnected to GND for maximum power dissipation.

DACFB ISP1

PGOODISP3ISP2

DVDFB

DACQ

ICO

MM

ON

CO

MP PI

RT

PW

M1

VD

D

PW

M3

PW

M2

12

11

10

9

13141516

1

2

3

4

8765

GND17

VDDDACFBDACQ

FBDVD

COMPPI

RT ICOMMONGNDPGOODISP2ISP1N/CPWM1PWM2

2

9876543

10

161514131211

RT8800/B

3DS8800/B-08 April 2011 www.richtek.com

Typical Application Circuit(Note : The inductor’ s DCR value must be large than 0.3mΩ

: X7R/R-type capacitor is required for all time constant setting capacitor of DCR sensing.)

BOO

T1

UG

ATE1

PHAS

E1

LGA

TE1

VD

D

PV

CC

PWM

1

PWM

2RT9

602

1114 5 1 2

41312

UG

ATE2

PHAS

E2

LGA

TE2

BOO

T2

GN

D

PGN

DSS

12/S

M

101u

F

12V

1uF PH

B83

N03

LT

PH

B95

N03

LT

1uF

2200

uF

12V

789

PH

B83

N03

LT

PH

B95

N03

LT

1uF

2200

uF

SS

12/S

M1u

F

VC

OR

E

3 6

10

3.3n

F

2.2

0

0

0 0

2.2 3.3n

F

0.5u

H

0.5u

H

1uH

PH

AS

E2

PH

AS

E1

10uF

x 4

1000

uF x

12

PH

AS

E2

PH

AS

E1

PI

DA

CQ

DA

CFB

PGO

OD

PW

M2

ISP

2

FB

COMP

VDD

PWM1

RT

DVD

ICOMMON

ISP1

VID

0

VID

2

VID

3

VID

4

VID

1

VID

5

3.3V 12

V

VC

OR

E

5V

11

4

65

8

3

9

13

1216

15

1

27

15k

10nF

33pF

3k0 0

Opt

iona

l

Opt

iona

l

1uF

1uF

430

3k16

k27

k

10k

1.8k

110k

56k

27k

13k

6.8k

3.3k

RR

RT8

800B

5.1k

GN

D10

Opt

iona

l for

R &

C

1uF

1000

uF

Opt

iona

l

RD

RO

OP

RIC

OM

MO

N1

RIC

OM

MO

N2

R1

R2 R3

R4

R5

R6

R7

R8

R9

R10

R11 R

12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22 R

23

R24

R25 R

26

C1

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

to C

29

C30

to C

33

D1

D2

Q1

Q2

Q3

Q4

Q5

Q6

L1

L2 L3

C2

Figure A. 2-phase with resistive DAC

RT8800/B

4DS8800/B-08 April 2011www.richtek.com

PH

ASE3

PHA

SE2

PHAS

E1

PI DAC

Q

DAC

FB

PGO

OD

PWM

3

PWM

2

ISP3

ISP2

FB

COMP

VDD

PWM1

RT

DVD

ICOMMON

ISP1

VID

0

VID

2

VID

3

VID

4

VID

1

VID

5

3.3V 12

V

V CO

RE

5V

9

3

54

7

2

8

12

11101415

13

16

16

GN

D

15k

10nF

33pF

3k

4.7u

F

Opt

iona

l

Opt

iona

l

Opt

iona

l

1uF

1uF

1uF

430

3k16

k

27k

10k

1.8k

110k

56k

27k

13k

6.8k

3.3k

RRR

RT8

800

5.1k

BOO

T2

PWM

3

PWM

2

PWM

1

BOO

T1

LGAT

E3

PVC

C3

PHAS

E3

UG

ATE3

BOO

T3

UGATE2

PVCC2

PHASE2

LGATE2

NC

UGATE1

PVCC1

PHASE1

LGATE1

VDD

12V

5VS

BP

HAS

E1

VIN

PH

ASE

2

V CO

RE

PHAS

E3

124

2223

910111514

3 8

2021

1917

16 7 5 4 2

GN

D

12V

12V

12V

V IN 12V

1uF

1000

uF

1uH

01u

F1u

F0

10 1uF

3.3n

F2.

2

1uF

01u

F0

3.3u

F2.

2

0.5u

H

0.5u

H

0.5u

H

1uF

03.

3nF

2.2

0

1uF

10uF

x 4

1000

uF x

12

RT9

605

1500

uF x

4

12V

VIN

Opt

iona

l

Opt

iona

l

RD

RO

OP

RIC

OM

MO

N1

RIC

OM

MO

N2

R1

R2 R3

R4

R5

R6

R7

R8

R9

R10

R11 R12

R13

R14

R15

R16 R17

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

C1

C2

C3

C4

C8

C9

C10

to C

13

C5

C6

C7

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

to C

35

C36

to C

39

D1 D

2

D3

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

L1

L2

L3

Figure B. 3-phase with resistive DAC

RT8800/B

5DS8800/B-08 April 2011 www.richtek.com

PHAS

E3

PH

AS

E2

PHAS

E1

PI DAC

Q

DAC

FB

PGO

OD

PWM

3

PWM

2

ISP3

ISP2

FB

COMP

VDD

PWM1

RT

DVD

ICOMMON

ISP1

3.3V 12

V

VC

OR

E

5V

9

3

54

7

2

8

12

11101415

13

16

16

GN

D

15k

10nF

33pF

3k

4.7u

F

Opt

iona

l

Opt

iona

l

Opt

iona

l

1uF

1uF

1uF

430

3k16

k

27k

10k

5.1k

RRR

RT8

800

BOO

T2

PWM

3

PWM

2

PWM

1

BOO

T1

LGAT

E3

PVC

C3

PHAS

E3

UG

ATE3

BOO

T3

UGATE2

PVCC2

PHASE2

LGATE2

NC

UGATE1

PVCC1

PHASE1

LGATE1

VDD

12V

5VS

BP

HA

SE

1VIN

PH

AS

E2

V CO

RE

PHAS

E3

124

2223

910111514

3 8

2021

1917

16 7 5 4 2

GN

D

12V

12V

12V

V IN

12V

1uF

1000

uF

1uH

01u

F1u

F0

10 1uF

3.3n

F

2.21u

F0

1uF

0

3.3u

F2.

2

0.5u

H

0.5u

H

0.5u

H

1uF

03.

3nF

2.2

0

1uF

10uF

x 4

1000

uF x

12

RT9

605

1500

uF x

4

12V

VIN

Opt

iona

l

Opt

iona

l

RD

RO

OP

RIC

OM

MO

N1

RIC

OM

MO

N2

5.1k

10nF RT9

401A

/B

VID

1

VDD

VID

0

VID

3

VDA

GN

D

VID

2

VID

4

5V

1 2 3 45678

R1

R2 R

3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

to C

14C

15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

to C

36

C37

to C

40

D1 D

2

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8 Q9

L1

L2

L3

Figure C. 3-phase with RT9401A/B DAC generator

RT8800/B

6DS8800/B-08 April 2011www.richtek.com

Function Block Diagram

Osc

illat

or&

Ram

p G

ener

ator

++ ++++

Sam

ple

& H

old

PW

M1

PW

M2

PW

M3

OC

P

SU

M/N

& O

CP

Det

ectio

n

PG

OO

DD

VD

GN

D

Sof

t Sta

rt

+

+-

ICO

MM

ON

ISP

1IS

P2

ISP

3

PW

M L

ogic

& D

river

PW

MC

P

+ -

PW

M L

ogic

& D

river

PW

MC

P

+ -

PW

M L

ogic

& D

river

PW

MC

P

+ -+++

Mux

Mux

Sam

ple

& H

old

Sam

ple

& H

old

VD

D

FBE

A

GM

CO

MP

-

+ -

0.8V

VR

EF

PI

Buf

fer

Am

plifi

er

INH

INH

INH

Pow

er O

nR

eset

RT

MA

J

500m

V

OV

P

DA

CFB

DA

CQ

RT8800/B

7DS8800/B-08 April 2011 www.richtek.com

VID5 VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage (V)

1 1 1 1 1 1 1.0800

1 1 1 1 1 0 1.1000 0 1 1 1 1 0 1.1125 1 1 1 1 0 1 1.1250 0 1 1 1 0 1 1.1375 1 1 1 1 0 0 1.1500 0 1 1 1 0 0 1.1625 1 1 1 0 1 1 1.1750 0 1 1 0 1 1 1.1875 1 1 1 0 1 0 1.2000 0 1 1 0 1 0 1.2125 1 1 1 0 0 1 1.2250 0 1 1 0 0 1 1.2375 1 1 1 0 0 0 1.2500

0 1 1 0 0 0 1.2625 1 1 0 1 1 1 1.2750 0 1 0 1 1 1 1.2875 1 1 0 1 1 0 1.3000 0 1 0 1 1 0 1.3125 1 1 0 1 0 1 1.3250 0 1 0 1 0 1 1.3375 1 1 0 1 0 0 1.3500 0 1 0 1 0 0 1.3625 1 1 0 0 1 1 1.3750 0 1 0 0 1 1 1.3875 1 1 0 0 1 0 1.4000 0 1 0 0 1 0 1.4125 1 1 0 0 0 1 1.4250 0 1 0 0 0 1 1.4375 1 1 0 0 0 0 1.4500 0 1 0 0 0 0 1.4625 1 0 1 1 1 1 1.4750 0 0 1 1 1 1 1.4875 1 0 1 1 1 0 1.5000 0 0 1 1 1 0 1.5125 1 0 1 1 0 1 1.5250 0 0 1 1 0 1 1.5375 1 0 1 1 0 0 1.5500

Table. Output Voltage Program

To be continued

RT8800/B

8DS8800/B-08 April 2011www.richtek.com

VID5 VID4 VID3 VID2 VID1 VID0 Nominal Output Voltage (V)

0 0 1 1 0 0 1.5625 1 0 1 0 1 1 1.5750 0 0 1 0 1 1 1.5875 1 0 1 0 1 0 1.6000 1 0 1 0 0 1 1.6250 1 0 1 0 0 0 1.6500 1 0 0 1 1 1 1.6750 1 0 0 1 1 0 1.7000 1 0 0 1 0 1 1.7250 1 0 0 1 0 0 1.7500 1 0 0 0 1 1 1.7750 1 0 0 0 1 0 1.8000 1 0 0 0 0 1 1.8250 1 0 0 0 0 0 1.8500

Table. Output Voltage Program

Note: 1 : Open0 : VSS or GND

RT8800/B

9DS8800/B-08 April 2011 www.richtek.com

Absolute Maximum Ratings (Note 1)

Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7VInput, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VDD + 0.3VPower Dissipation, PD @ TA = 25°CVQFN-16L 3X3 -------------------------------------------------------------------------------------------------- 1.47WSOP-16 ----------------------------------------------------------------------------------------------------------- 1WPackage Thermal Resistance (Note 2)VQFN-16L 3X3, θJA --------------------------------------------------------------------------------------------- 68°C/WSOP-16, θJA ----------------------------------------------------------------------------------------------------- 100°C/WJunction Temperature ------------------------------------------------------------------------------------------ 150°CLead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------- 260°CStorage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°CESD Susceptibility (Note 3)HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kVMM (Machine Mode) ------------------------------------------------------------------------------------------- 200V

Electrical Characteristics(VDD = 5V, TA = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

VDD Supply Current Nominal Supply Current IDD PWM 1,2,3 Open -- 5 -- mA

Power On Reset

Rising 4.0 4.2 4.5 VDD Threshold

Hysteresis 0.2 0.5 -- V

DVD Rising Threshold 0.75 0.8 0.85 V

DVD Hysteresis -- 65 -- mV

Oscillator

Free Running Frequency fOSC RRT = 16kΩ 170 200 230 kHz

Frequency Adjustable Range fOSC_ADJ 50 -- 400 kHz

Ramp Amplitude ΔVOSC RRT = 16kΩ -- 1.7 -- V

Ramp Valley VRV -- 1.0 -- V

Maximum On-Time of Each Channel 62 66 75 %

Minimum On-Time of Each Channel -- 120 -- ns

RT Pin Voltage VRT RRT = 16kΩ 0.77 0.82 0.87 V

Recommended Operating Conditions (Note 4)

Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V ± 10%Ambient Temperature Range--------------------------------------------------------------------------------- 0°C to 70°CJunction Temperature Range--------------------------------------------------------------------------------- 0°C to 125°C

To be continued

RT8800/B

10DS8800/B-08 April 2011www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

Reference Voltage

Reference Voltage VDACFB 0.79 0.8 0.81 V

DACFB Sourcing Capability -- -- 10 mA

Error Amplifier

DC Gain -- 65 -- dB

Gain-Bandwidth Product GBW CL = 10pF -- 10 -- MHz

Slew Rate SR CL = 10pF -- 8 -- V/μs

Current Sense GM Amplifier

Recommended Full Scale Source Current -- 100 -- μA

OCP trip level IOCP 160 190 220 μA

Protection

Over-Voltage Trip (VFB - VDACQ) -- 500 -- mV

Power Good

PGOOD Output Low Voltage VPGOOD IPGOOD = 4mA -- -- 0.2 V

PGOOD Delay TPGOOD_Delay 90% * VOUT to PGOOD_H 4 -- 8 ms

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC

51-3 thermal measurement standard.

Note 3. Devices are ESD sensitive. Handling precaution recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

RT8800/B

11DS8800/B-08 April 2011 www.richtek.com

Typical Operating Characteristics

VREF vs. Temperature

0.78

0.785

0.79

0.795

0.8

0.805

0.81

0.815

-25 -10 5 20 35 50 65 80 95 110 125

Temperature

VR

EF(V

)

(°C)

GM3GM2GM1

RICOMMON1 = 430Ω

Frequency vs. RRT

0

100

200

300

400

500

600

700

800

900

1000

0 5 10 15 20 25 30 35 40 45 50 55 60

RRT (k )

Freq

uenc

y (k

Hz)

(kΩ)

Load Line

1.24

1.26

1.28

1.3

1.32

1.34

1.36

1.38

1.4

0 10 20 30 40 50 60 70 80 90 100

Output Current (A)

Out

put V

olta

ge (V

)

RLL = 1.5mΩ, RICOMMON2 = 10kΩ, RDROOP = 100ΩVIN = 12V

Efficiency vs. Output Current

0

10

20

30

40

50

60

70

80

90

100

0 10 20 30 40 50 60 70 80 90 100

Output Current (A)

Effi

cien

cy (%

)

Driver RT9605

VIN = 12V, VOUT = 1.4V

GM

0

10

20

30

40

50

60

70

80

90

0 10 20 30 40 50 60 70 80 90 100 110

VC (mV)

I AD

J (u

A) GM3

GM2GM1

RICOMMON1 = 430Ω

(°C)

OCP Trip Point vs. Temperature

0

30

60

90

120

150

180

210

240

-25 -10 5 20 35 50 65 80 95

Temperature

Ix (u

A)

RT8800/B

12DS8800/B-08 April 2011www.richtek.com

Frequency vs. Temperature

0

50

100

150

200

250

300

350

-25 -10 5 20 35 50 65 80 95 110 125

Temperature

Freq

uenc

y (k

Hz)

(°C)

RRT = 16kΩ

Time (2.5μs/Div)

Load Transient Response

UGATE1(20V/Div)

VCORE(200mV/Div)

UGATE2(20V/Div)

UGATE3(20V/Div)

phase 1, IOUT = 5A to 85A @SR = 93A/us)

Time (2.5μs/Div)

Load Transient Response

UGATE1(20V/Div)

VCORE(200mV/Div)

UGATE2(20V/Div)

UGATE3(20V/Div)

phase 3, IOUT = 5A to 85A @SR = 93A/us)

Time (10ms/Div)

Over Current Protection

IL1+IL2(50A/Div)

VCORE(1V/Div)

PWM1(10V/Div)

VCOMP(2V/Div)

Short While Turn_On

Time (10ms/Div)

Over Current Protection

IL1+IL2(50A/Div)

VCOMP(2V/Div)

PWM1(10V/Div)

VCORE(1V/Div)

Short After Turn_On

Time (2.5μs/Div)

Load Transient Response

UGATE1(20V/Div)

VCORE(200mV/Div)

UGATE2(20V/Div)

UGATE3(20V/Div)

phase2, IOUT = 5A to 85A @SR = 93A/us)

RT8800/B

13DS8800/B-08 April 2011 www.richtek.com

Time (10μs/Div)

VID On the Fly RisingIOUT = 5A

VFB(200mV/Div)

VID0(2V/Div)

PWM(5V/Div)

VCORE(200mV/Div)

Time (10μs/Div)

VID On the Fly RisingIOUT = 90A

VFB(200mV/Div)

VID0(2V/Div)

PWM(5V/Div)

VCORE(200mV/Div)

Time (25μs/Div)

VID On the Fly Falling

VFB(200mV/Div)

VID0(2V/Div)

PWM(5V/Div)

VCORE(50mV/Div)

IOUT = 90A

Time (25μs/Div)

VID On the Fly Falling

VFB(200mV/Div)

VID0(2V/Div)

PWM(5V/Div)

VCORE(100mV/Div)

IOUT = 5A

RT8800/B

14DS8800/B-08 April 2011www.richtek.com

Application InformationRT8800/B are multiphase DC/DC controllers for extremelow cost applications that precisely regulate CPU corevoltage and balance the current of different power channelsusing time sharing current sensing method. The converterconsisting of RT8800/B and its companion MOSFET driverRT96xx series provide high quality CPU power and allprotection functions to meet the requirement of modernVRM.

Phase Setting and Converter Start UpRT8800/B interface with companion MOSFET drivers (likeRT9602, RT9603, and RT9605) for correct converterinitialization. RT8800/B will sense the voltage on PWMpins at the instant of POR rising. If the voltage is smallerthan (VDD − 1.2V) the related channel is activated. Tie thePWM to VDD and the corresponding current sense pins toGND or left float if the channel is unused. For example, for2-Channel application, tie PWM3 to VDD and ISP3 to GND(or let ISP3 open).

PGOOD Function and Soft StartTo indicate the condition of multiphase converter,RT8800/B provide PGOOD signal through an open drainconnection. The output becomes high impedance afterinternal SS ramp > 3.5V.

1) Mode 1 (SS< Vramp_valley)

Initially the COMP stays in the positive saturation. WhenSS< VRAMP_Valley, there is no non-inverting input availableto produce duty width. So there is no PWM signal andVOUT is zero.

2) Mode 2 (VRAMP_Valley< SS< Cross-over)

When SS>VRAMP_Valley, SS takes over the non-invertinginput and produce the PWM signal and the increasing

duty width according to its magnitude above the rampsignal. The output follows the ramp signal, SS. Howeverwhile VOUT increases, the difference between VOUT andSSE(SS − VGS) is reduced and COMP leaves thesaturation and declines. The takeover of SS lasts until itmeets the COMP. During this interval, since the feedbackpath is broken, the converter is operated in the open loop.

3) Mode3 ( Cross-over< SS < VGS + VREF)

When the Comp takes over the non-inverting input for PWMAmplifier and when SSE (SS − VGS) < VREF, the output ofthe converter follows the ramp input, SSE (SS − VGS).Before the crossover, the output follows SS signal. Andwhen Comp takes over SS, the output is expected to followSSE (SS − VGS). Therefore the deviation of VGS isrepresented as the falling of VOUT for a short while. TheCOMP is observed to keep its decline when it passes thecross-over, which shortens the duty width and hence thefalling of VOUT happens.

Since there is a feedback loop for the error amplifier, theoutput’ s response to the ramp input, SSE (SS − VGS) islower than that in Mode 2.

4) Mode 4 (SS > VGS + VREF)

When SS > VGS + VREF, the output of the converter followsthe desired VREF signal and the soft start is completednow.

Voltage ControlThe voltage control loop consists of error amplifier,multiphase pulse width modulator, driver and powercomponents. As conventional voltage mode PWMcontroller, the output voltage is locked at the positive inputof error amplifier and the error signal is used as the controlsignal of pulse width modulator. The PWM signals ofdifferent channels are generated by comparison of EAoutput and split-phase sawtooth wave. Power stagetransforms VIN to output by PWM signal on-time ratio.

Output Voltage ProgramThe output voltage of a RT8800/B converter is programmedto discrete levels between 1.08V and 1.85V. The voltageidentification (VID) pins program an external voltagereference (DACQ) with a 6-bit digital-to-analog converter(DAC). The level of DACQ also sets the OVP threshold.The output voltage should not be adjusted while theconverter is delivering power. Remove input power before

COMP

VCORE

SSE_Internal

SS_Internal

Cross-over

VRAMP_Valley

RT8800/B

15DS8800/B-08 April 2011 www.richtek.com

DAC Design GuidelineIn high temperature environment, VCORE becomesunstable for the leakage current in VID pins is increasing.The leakage will increase current consumption of CPU,and then raise RT8800's VDACQ reference output, so doesVCORE voltage. Below are four comparison charts fordifferent CPUs.

Note: In Below Figure 2 to Figure 5, The Original R means

the resister values shown in typical application circuit.

R=1/3 and R=1/9 mean that The Original R is divided

by 3 or 9.

Figure 5

Figure 4

VCORE vs. Temperature

1.335

1.34

1.345

1.35

1.355

1.36

1.365

1.37

1.375

1.38

30 35 40 45 50 55 60 65 70

Temperature

VC

OR

E (V

)

(°C)

CPU : P4-2.8GVCORE = 1.35V

R = 1/9

R = 1/3

The Original R

Figure 3

Figure 2

changing the output voltage. Adjusting the output voltageduring operation may trigger the over-voltage protection.The DAC function is a precision non-inverting summationamplifier shown in Figure 1. The resistor values shownare only approximations of the actual precision valuesused. Grounding any combination of the VID pins increasesthe DACQ voltage. The “open” circuit voltage on the VID

pins is the band gap reference voltage (VREF = 0.8V).

+

-

VREF(0.8V)

VDACFB

OP VDACQ

RF

RG

VID0

VID1

VID2

VID3

VID4

VID5

R

RR

R

R

R

Figure 1. The Structure of Discrete DAC Generator

VCORE vs. Temperature

1.54

1.55

1.56

1.57

1.58

1.59

1.6

1.61

1.62

1.63

1.64

30 35 40 45 50 55 60 65 70

Temperature

VC

OR

E (V

)

(°C)

CPU : P4-3.2GVCORE = 1.55V

R = 1/9

R = 1/3

The Original R

VCORE vs. Temperature

1.54

1.56

1.58

1.6

1.62

1.64

1.66

1.68

30 35 40 45 50 55 60 65 70

Temperature

VC

OR

E (V

)

(°C)

CPU : P4-3.06GVCORE = 1.55V

R = 1/9

R = 1/3

The Original R

VCORE vs. Temperature

1.52

1.54

1.56

1.58

1.6

1.62

1.64

1.66

30 35 40 45 50 55 60 65 70

Temperature

VC

OR

E (V

)

(°C)

CPU : Celeron 2.0GVCORE = 1.55V

R = 1/9

R = 1/3

The Original R

RT8800/B

16DS8800/B-08 April 2011www.richtek.com

Figure 9 is the test circuit for GM. We apply test signal atGM inputs and observe its signal process output by PIpin sinking current. Figure 10 shows the variation of signalprocessing of all channels. We observe zero offsets andgood linearity between phases.ICOMMON1

CXLC R

VI IDCR VCRDCR

L=×=×=

Current Sensing SettingRT8800/B senses the current flowing through inductorvia its DCR for channel current balance and droop tuning.The differential sensing GM amplifier converts thevoltage on the sense component (can be a senseresistor or the DCR of the inductor) to current signalinto internal circuit (see Figure 7).

Figure 7. Current Sense Circuit

L DCR

R

RICOMMONGMx

Ix

C

+

-

IL

VC+ -

Figure 9. The Test Circuit of GM

PWM Signal & High Side MOSFET Gate Signal

Low Side MOSFET Gate Signal

Inductor Current

Falling Slope = Vo/LIL

IL(AVG)

IL(S/H)

Figure 8. Inductor current and PWM signal

SIN

OINOFF

OFFOL(AVG)L(S/H)

ICOMMON1

L(S/H)X(S/H)

T x )V

V- V( T

2

T x L

V - I I ; R

DCR x I I

=

==

In order to maintain the VDACQ within 1% tolerance in theworst case, the total driver current of the DAC regulatorshould support up to 40mA. As the design of RT8800/B,the maximum driving current of the internal OP is 10mA.As shown in Figure 6, we suggest to add an externaltransistor 2N3904 for higher current for VDAC regulation.

+

-

VREF(0.8V)

VDACFBOP

PI43

121

VID0

VID1

VID2

VID3

VID4

VID5

1.34k

645

310

162

81

2.63k

VCC

Q12N3904

VDACQ

Figure 6. Immune circuit against CPU Leakage Current

ICOMMON1

SIN

OINO

L(AVG)X(S/H)

S

RDCR x

2L

T x )V

V- V( - V - I I

T period switching, for

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

=

=

The sensing circuit gets by localfeedback.

IX is sampled and held just before low side MOSFET turnsoff (Figure 8).

ICOMMON1

LX

RDCR x II =

L DCR

ESR

RICOMMON11kGMx

Ix

VC+

-

VISPXVICOMMON

C

+ -

RT8800/B

17DS8800/B-08 April 2011 www.richtek.com

Figure 10. The Linearity of GMx

GM

0

10

20

30

40

50

60

70

0 20 40 60 80 100

VC (mV)

I AD

J (uA

)

GM1

GM2

GM3

Figure 11 shows the time sharing technique of GMamplifier. We apply test signal at phase 3 and observe thewaveforms at both pins of GM amplifier. The waveformsshow time sharing mechanism and the perfomance of GMto hold both input pins equal when the shared time is on.

Figure 11

Time Sharing of GM

Time (1μs/Div)

PWM3

VISP3and

VICOMMON

CH1:(2V/Div)CH2:(50mV/Div)CH3:(50mV/Div)

VISP3

VICOMMON

Current Ratio Setting

For some case with preferable current ratio instead ofcurrent balance, the corresponding technique is provided.Due to different physical environment of each channel, itis necessary to slightly adjust current loading betweenchannels. Figure 12. shows the application circuit of GMfor current ratio requirement. Applying KVL along L+DCRbranch and R1+C//R2 branch:

Look for its corresponding conditions:

Figure 12. Application circuit for current ratio setting

LC

CC

CCC

LL

I x DCR R2 R1

R2 VFor

VR2

R2R1 dt

dVC x R1

V dt

dVC R2V R1 I x DCR

dtdIL

+=

++=

+⎟⎠

⎞⎜⎝

⎛ +=+

C x (R1//R2) DCR

L Let

I x DCR dtdI xDCR x C x (R1//R2) I x DCR

dtdIL L

LL

L

=

+=+

Figure 13. GM3 Setting for current ratio function

Figure 14. GM1,2 Setting for current ratio function

LC I x DCR x R2 R1

R2 VThen

C x (R1//R2) DCR

L if Thus

+=

=

With internal current balance function, this phase wouldshare (R1+R2)/R2 times current than other phases.Figure 13 &14 show different settings for the power stages.

IL

1.5uH 1m

3k 1uF

3k

1.5uH 1m

1.5k 1uF

IL

R2

L DCR

R1

C

IL

+ -VC

RT8800/B

18DS8800/B-08 April 2011www.richtek.com

RICOMMON2 ≤ 85.8kΩ

Choose RICOMMON2 = 82kΩ

Assume the negative inductor valley current is −5A at noload, then for

RICOMMON1 = 330Ω, RADJ = 160Ω, VOUT = 1.300

ICOMMON1

L

ICOMMON2

L

ICOMMON2

OUT

ICOMMON1

L

ICOMMON2

LOUT

ICOMMON1

L

ICOMMON2

ICOMMONX

RDCRI

RDCRI

RV

RDCRI

RDCRIV

RDCRI

RVI

×+

×+=

×+

×+=

×+=

ICOMMON1

L

ICOMMON2

ICOMMONR

DCRIRV ×

≥

ΩΩ×

≥330

1m5AR

1.3VICOMMON2

-

if GM holds input voltages equal, then

VISPX = VICOMMON

For the lack of sinking capability of GM, RICOMMON2 shouldbe small enough to compensate the negative inductorvalley current especially at light loads.

For load line design, with application circuit in Figure 15,it can eliminate the dead zone of load line at light loads.

VISPX = VOUT +IL x DCR

Figure 15. Application circuit of GM

Current BalanceRT8800/B senses the inductor current via inductor’ s DCRfor channel current balance and droop tuning. Thedifferential sensing GM amplifier converts the voltage onthe sense component (can be a sense resistor or theDCR of the inductor) to current signal into internal balancecircuit.

The current balance circuit sums and averages the currentsignals and then produces the balancing signals injectedto pulse width modulator. If the current of some powerchannel is larger than average, the balancing signalreduces that channels pulse width to keep current balance.

The use of single GM amplifier via time sharing techniqueto sense all inductor currents can reduce the offset errorsand linearity variation between GMs. Thus it can greatlyimprove signal processing especially when dealing withsuch small signal as voltage drop across DCR.

Voltage Reference for Converter Output & Load DroopThe positive input of error amplifier is PI pin that sinkscurrent proportional to the sum of converter output current.VDRP = 2ISINK x RDRP. The load droop proportional to loadcurrent can be set by the resistor between PI pin & externalVDACQ produced by either buffer amplifier or other voltagesource. The PI pin voltage should be larger than 0.8V forgood droop circuit performance.

Figure 16

Load Line without dead zone at light loads

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.3

1.31

0 5 10 15 20 25

IOUT (A)

VC

OR

E (V

)

RICOMMOM2 open

RICOMMON2 = 82k

L DCR

ESR

RICOMMON1GMx

Ix

+

-

RICOMMON2

VISPXVICOMMON

VC

C

+ -

RT8800/B

19DS8800/B-08 April 2011 www.richtek.com

DAC Offset Voltage TuningThe Intel specification requires that at no load the nominaloutput voltage of the regulator be offset to a value lowerthan the nominal voltage corresponding to the VID code.The offset is tuning from RG in the DAC generator asFigure 18.

If VID0~6 is set at VSS (Ground), and to suppose thatshunt resistance is Rs.

From below equation, we can tune the value of RG toincrease or decrease the base voltage of VDACQ.

REFS

FREF

G

FDACQ x V

RR x V)

RR (1 V ++=

+

-

VREF(0.8V)

VDACFBOP VDACQ

RF

RG

VID0

VID1

VID2

VID3

VID4

VID5

R

RR

R

R

R

Figure 18. The Structure of Discrete DAC Generator

Over Current ProtectionOCP comparator co\mpares each inductor current sensed& sample/hold by current sense circuit with this referencecurrent(150uA). RT8800/B uses hiccup mode to eliminatefault detection of OCP or reduce output current whenoutput is shorted to ground.

Figure 19. The Over Current Protection in the interval

CH1:(5V/Div)CH2:(5V/Div)

Over Current Protection

Time (25ms/Div)

PWM

IL

Figure 20. Over Current Protection at steady state

CH1:(5V/Div)CH2:(5V/Div)

Over Current Protection

Time (25ms/Div)

PWM

VSS

Fault DetectionThe “hiccup mode” operation of over current protectionis adopted to reduce the short circuit current. The in-rushcurrent at the start up is suppressed by the soft startcircuit through clamping the pulse width and output voltageby an internal slow rising ramp.

Figure 17. Load Droop Circuit

EAFB

PI+ -

+-

VDACQVDRP

2xIX12xIX22xIX3

ISINK

RT8800/B

20DS8800/B-08 April 2011www.richtek.com

Design Procedure Suggestiona.Output filter pole and zero (Inductor, output capacitor

value & ESR).

b.Error amplifier compensation & sawtooth wave amp-litude (compensation network).

Current Loop Settinga.GM amplifier S/H current (current sense component

DCR, ICOMMON pin external resistor value).

b.Over-current protection trip point (RICOMMON1 resistor).

VRM Load Line Settinga.Droop amplitude (PI pin resistor).

b.No load offset (RICOMMON2)

Power Sequence & SSDVD pin external resistor and SS pin capacitor.

PCB Layouta.Sense for current sense GM amplifier input.

b.Refer to layout guide for other items.

Voltage Loop Setting

Design Example

Given:Apply for four phase converter

VIN = 12V

VCORE = 1.5V

ILOAD(MAX) = 100A

VDROOP = 100mV at full load (1mΩ Load Line)

OCP trip point set at 35A for each channel (S/H)

DCR = 1mΩ of inductor at 25°C

L = 1.5μH

COUT = 8000μF with 5mΩ equivalent ESR.

Figure 21. Type 2 compensation network of EA

2. Over-Current Protection SettingConsider the temperature coefficient of copper3900ppm/°C,

EA

RB2

RB1

+

-15k

C1

12nF

C2 68pF

4.7k

1. Compensation Settinga. Modulator Gain, Pole and Zero:

From the following formula:

Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)

where VRAMP : ramp amplitude of saw-tooth wave

35.6AI

A1503301.39mI

A150R

DCRI

L

L

ICOMMON1

L

=

=Ω

Ω×

=×

μ

μ

LC Filter Pole = 1.45kHz and

ESR Zero =3.98kHz

b. EA Compensation Network:

Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pFand use the Type 2 compensation scheme shown inFigure 21. By calculation, the FZ = 0.88kHz,FP = 322kHz and Middle Band Gain is 3.19 (i.e10.07dB).

RT8800/B

21DS8800/B-08 April 2011 www.richtek.com

Layout ConsiderationsPlace the high-power switching components first, andseparate them from sensitive nodes.

1. Most critical path:

The current sense circuit is the most sensitive part ofthe converter. The current sense resistors tied toISP1,2,3 and ICOMMON should be located not morethan 0.5 inch from the IC and away from the noiseswitching nodes. The PCB trace of sense nodes shouldbe parallel and as short as possible. R&C filter of chokeshould place close to PWM and the R & C connectdirectly to the pin of each output choke, use 10 mildifferencial pair, and 20 mil gap to other phase pair.Less via as possible.

Figure 22. Power Stage Ripple Current Path

SW2L2

SW1L1

COUT RL

VOUTVIN

RIN

CINV

2. Switching ripple current path:

a. Input capacitor to high side MOSFET.

b. Low side MOSFET to output capacitor.

c. The return path of input and output capacitor.

d. Separate the power and signal GND.

e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisypoints. Keep them away from sensitive small-signalnode.

f . Reduce parasitic R, L by minimum length, enoughcopper thickness and avoiding of via.

3. MOSFET driver should be closed to MOSFET.

RT8800/B

22DS8800/B-08 April 2011www.richtek.com

Figure 23. Layout Consideration

Figure 24

PWM

RT

PI

VCC

COMP

FB

RT8800/B

CSPx

+5VIN

CBP

CCRICOM

COUTRC

RFB

Next to IC

Locate nextto FB Pin

LO1 VCORE

CIN

Locate near MOSFETs

CBOOT

+12V or +5V0.1uF

+12V

VCC

IN

GND

BST

DRVH

SW

DRVLRT9603

Next to IC

GND

GND

ICOMMON

RDRD

RT8800/B

23DS8800/B-08 April 2011 www.richtek.com

Figure 25

Figure 26

RT8800/B

24DS8800/B-08 April 2011www.richtek.com

Figure 27

RT8800/B

25DS8800/B-08 April 2011 www.richtek.com

Outline Dimension

A

A1A3

D

E

1

D2

E2

L

be

SEE DETAIL A

Dimensions In Millimeters Dimensions In Inches Symbol

Min Max Min Max

A 0.800 1.000 0.031 0.039

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 2.950 3.050 0.116 0.120

D2 1.300 1.750 0.051 0.069

E 2.950 3.050 0.116 0.120

E2 1.300 1.750 0.051 0.069

e 0.500 0.020

L 0.350 0.450 0.014 0.018

V-Type 16L QFN 3x3 Package

Note : The configuration of the Pin #1 identifier is optional,but must be located within the zone indicated.

DETAIL APin #1 ID and Tie Bar Mark Options

11

2 2

RT8800/B

26DS8800/B-08 April 2011www.richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611

Richtek Technology CorporationTaipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien CityTaipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email: marketing@richtek.com

F

B

CI

H

D

A

J

M

Dimensions In Millimeters Dimensions In Inches Symbol

Min Max Min Max

A 9.804 10.008 0.386 0.394

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.254 0.007 0.010

I 0.102 0.254 0.004 0.010

J 5.791 6.198 0.228 0.244

M 0.406 1.270 0.016 0.050

16–Lead SOP Plastic Package