30
GENERAL VLSI SYSTEM COMPONENTS Dr. Mohammed M. Farag
GENERAL VLSI SYSTEM
COMPONENTS
Dr. Mohammed M. Farag
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Gate-level NAND 2:1 multiplexor.
Multiplexers
Multiplexor using switch logic.
Gate-level 4:1 MUX A 4:1 MUX using instanced 2:1 devices.
EE 432 VLSI Modeling and Design 2
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
4:1 MUX using nFET pass transistors.
Multiplexers (2)
Simple 4:1 pass-FET MUX layout.
EE 432 VLSI Modeling and Design 3
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Split-array 4:1 MUX for full-rail output.
Multiplexers (3)
EE 432 VLSI Modeling and Design 4
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
A vector 2:1 MUX.
Multiplexers (4)
Single-bit cell tiling for an 8-bit 2:1 MUX.
EE 432 VLSI Modeling and Design 5
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
An active-high 2/4 decoder.
Decoders
EE 432 VLSI Modeling and Design 6
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Active low 2/4 decoder.
Decoders (2)
EE 432 VLSI Modeling and Design 7
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
a 4-bit equality detector.
Comparators
8-bit equality detector.
EE 432 VLSI Modeling and Design 8
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
4-bit magnitude comparator logic.
Comparators (2)
Comparator output summary.
EE 432 VLSI Modeling and Design 9
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Additional logic for A_EQ_B
and Enable features.
Comparators (3)
Comp 8 logic diagram.
EE 432 VLSI Modeling and Design 10
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
8-bit comparator system.
Comparators (4)
EE 432 VLSI Modeling and Design 11
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Function table for an 8-bit priority
encoder.
Encoders
Symbol for priority encoder
EE 432 VLSI Modeling and Design 12
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Logic diagram for the priority encoder.
Encoders (2)
EE 432 VLSI Modeling and Design 13
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Q0 and Q1 circuits for the 8-bit priority
encoder.
Encoders (3)
EE 432 VLSI Modeling and Design 14
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
General rotator.
Rotators and Shifters
A 4-bit rotate-right network.
EE 432 VLSI Modeling and Design 15
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Left-rotate switching array.
Rotators and Shifters (2)
EE 432 VLSI Modeling and Design 16
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
An 8 X 4 barrel shifter.
Rotators and Shifters (3)
FET-array barrel shifter.
EE 432 VLSI Modeling and Design 17
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
D-latch.
Latches and Flip-Flops
CMOS circuit for a D-latch.
Gated D-latch with Enable control.
AOI CMOS gate for D-latch with Enable.EE 432 VLSI Modeling and Design 18
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Closed-loop inverter configurations.
Latches and Flip-Flops (2)
Operation of a bistable circuit.
EE 432 VLSI Modeling and Design 19
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Adding an input node to the bistable circuit.
Latches and Flip-Flops (3)
D-latch using oppositely phased switches.
EE 432 VLSI Modeling and Design 20
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Operation of the D-latch.
Latches and Flip-Flops (4)
EE 432 VLSI Modeling and Design 21
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
C2MOS-based D-latch circuits.
Latches and Flip-Flops (5)
EE 432 VLSI Modeling and Design 22
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Master-slave D-type flip-flop.
Latches and Flip-Flops (6)
Edge-triggered DFF symbols.
EE 432 VLSI Modeling and Design 23
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Alternate circuitry for the master-slave DFF.
Latches and Flip-Flops (7)
EE 432 VLSI Modeling and Design 24
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
DFF circuits with assert-low Clear and
Clear/Set controls.
Latches and Flip-Flops (8)
EE 432 VLSI Modeling and Design 25
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
DFF modified to a TFF circuit using feedback.
Latches and Flip-Flops (9)
EE 432 VLSI Modeling and Design 26
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
D-type flip-flop with Load control.
Latches and Flip-Flops (10)
EE 432 VLSI Modeling and Design 27
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Operation of the CMOS DFF with load control.
Latches and Flip-Flops (11)
CMOS master-slave FF
with Load control.
EE 432 VLSI Modeling and Design 28
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
Construction of an n-bit register.
Registers
EE 432 VLSI Modeling and Design 29
Faculty of Engineering - Alexandria University 2013Faculty of Engineering - Alexandria University 2013
One-bit static multiport register circuit.
Registers (2)
An n-bit static multiport register.
EE 432 VLSI Modeling and Design 30
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