Generalized Isomorphism

between Synchronous Circuits

and State Machines

Shunji Nishimura

Ju ly 1, 2015 ITC-CSCC

2

MotivationCategory theory

Great successes in software scienceex. programming semantics (modeling)

might be in hardware

morphism

composition

morphism

b a∘

object

a

morphismb

object object

3

Known isomorphism

f

D-FlipFlop synchronous circuit and state machine

Low LowHigh

D-FF

f

next

equaldiscretesampling

circuit

SM

4

(part of) Our isomorphismD-Latch synchronous circuit and state machine

a0 a1 a2 a3

a0 a1 a2 a3

f

D-Latch

f

next

equal

circuit

SM

time structuretransformation

Agenda

(0) Modeling on category theory

(1) Evaluation operator

(2) Comprehensive Latches

(3) Transformation of time structure

(1)

(2)(3)

6

Category:

signal as:

Modeling on category [1/3]

morphism

composition

morphism

b a∘

object

a

morphismb

object object

transit

ion

composition

of transition

signalvalue

transitionsignalvalue

signalvalue

time as:

transit

ion

composition

of transition

timepoint

transition

timepoint

timepoint

7

A B

SS := functor A × S → B × SA circuit:

An evaluation pattern := functor time T → signal A

Modeling on category [2/3]

category A

functor

category B

Functor: mapping between categories

Natural transformation: mapping between functors

8

Modeling on category [3/3]

categoryNaturaltransformation

category

functor F

functor G

will be used for our transformation of time structure.

(Agenda)

(0) Modeling on category theory

(1) Evaluation operator

(2) Comprehensive Latches

(3) Transformation of time structure

(1)

(2)(3)

10

Evaluation operator [1/3]

AA×S

T BB×S

af

a ▷ f

fA B

SS

time

evaluationresult

Define operator ▷ which determines evaluation results.

evaluationpattern

circuit

= a ▷ fviz.a

Time (= category) for evaluation

Encountering problem

Intend to : (transit t0 → t1 → t2),

but in fact : (exists t0 → t2).

11

: non-deterministic branching

t0 t1 t2

t0 t1 t2

compositon

Evaluation operator [2/3]

: joining together

Consider time structure τ of time T as:

τ ⊂ { morphisms of T }a ▷ f

τ

12

τ τ

t0 t1

f s0fs0

= f

next

= f

state machine

combinational

circuit

Evaluation operator [3/3]

Similar to the state machine evaluation

To imitate logic simulation, iterative calculation is described by identity morphism.

(Agenda)

(0) Modeling on category theory

(1) Evaluation operator

(2) Comprehensive Latches

(3) Transformation of time structure

(1)

(2)(3)

14

？

Comprehensive Latches [1/2]

order reversal of previous/current signal

rejected

accepted

aim to build the most general latches/FFs

rejected accepted

τ redundant(premised on )

corresponding to enable state of D-Latchs

corresponding to disable state of D-Latchs

15

C

A

A A

A

A

1 2 n

Comprehensive Latch : (C×A)×An → A×An

= C×An+1 → An+1

input state output state

Comprehensive Latches [2/2]

Definiton: serial connection of (function to) the previous units

(Agenda)

(0) Modeling on category theory

(1) Evaluation operator

(2) Comprehensive Latches

(3) Transformation of time structure

(1)

(2)(3)

17

Transformation of time structure [1/2]

C×T n+1

T T

(clock) ckρ

id (identity)

C×T

T n+1

ck×id ▷ ρτ

comprehensivelatch

τ: time structure

ρ :

T T

(Natural transformation)

id

Renewed time structure is defined as:

18

t0

ck

τ

(Low enable)

=

ρ =

=

=

ex.

τ=

t1 t2 t3 t4 t5 t6

t0 t0 t0 t3 t4 t4 t4

t0 t1 t2 t3 t4 t5 t6

D-Latch

throughkeep

=( id )

∴

Transformation of time structure [2/2]

ck×id ▷ρnatural transformation

19

Theorem: isomorphism [1/2]

ρ synchronous circuit and state machine (ρ: comprehensive latch)

f

f

next

equaltime structuretransformation

ρ

a0 a1 a2

τ

=

=

ckpattern =

a0 a1 a2

==pattern

alongwith

alongwith

The two functors in the centerare the same.

20

C×A×Sn+1

T BB×Sn+1

clock ckfρ

a

AA×S

B×S=

evaluationpattern

circuit f

f

ρ

C

A

S

Sn

B

S

Sn

ck×a ▷ fρ

τ

a ▷ fa

comprehensive latch

τ: time structure

ρ :

Theorem: isomorphism [2/2]

C×A

21

Conclusion

Generalized theory was acquired using category theory.

A common modeling of circuits and state machines is presented.

A generalized concept of latches/FFs is also presented.

A state machine corresponding to a D-Latch synchronous circuit is available.