ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Experiment 7

VHDL Modeling of Embedded Microprocessors and

Microcontrollers

ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Simple Microprocessor

ECE 448 – FPGA and ASIC Design with VHDL 3

Basic Architecture• Control unit and

datapath• Note similarity to

single-purpose processor

• Key differences• Datapath is general• Control unit doesn’t

store the algorithm – the algorithm is “programmed” into the memory

Processor

Control unit Datapath

ALU

Registers

IRPC

Controller

Memory

I/O

Control/Status

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 4

Instruction Cycles

Processor

Control unit Datapath

ALU

Registers

IRPC

Controller

Memory

I/O

Control/Status

10...

...

load R0, M[500] 500

501

100

inc R1, R0101

store M[501], R1102

R0 R1

PC=100

10

Fetch ops

Exec. Store results

clk

Fetch

load R0, M[500]

Decode

100

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 5

Architectural Considerations

• Clock frequency• Inverse of clock

period• Must be longer

than longest register to register delay in entire processor

• Memory access is often the longest

Processor

Control unit Datapath

ALU

Registers

IRPC

Controller

Memory

I/O

Control/Status

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 6

A Simple (Trivial) Instruction Set

opcode operands

MOV Rn, direct

MOV @Rn, Rm

ADD Rn, Rm

0000 Rn direct

0010 Rn

0100 RmRn

Rn = M(direct)

Rn = Rn + Rm

SUB Rn, Rm 0101 Rm Rn = Rn - Rm

MOV Rn, #immed. 0011 Rn immediate Rn = immediate

Assembly instruct. First byte Second byte Operation

JZ Rn, relative 0110 Rn relative PC = PC+ relative (only if Rn is 0)

Rn

MOV direct, Rn 0001 Rn direct M(direct) = Rn

Rm M(Rn) = Rm

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 7

Addressing Modes

Data

Immediate

Register-direct

Registerindirect

Direct

Indirect

Data

Operand field

Register address

Register address

Memory address

Memory address

Memory address Data

Data

Memory address

Data

Addressingmode

Register-filecontents

Memorycontents

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 8

Sample Program

int total = 0;for (int i=10; i!=0; i--) total += i;// next instructions...

C program

MOV R0, #0; // total = 0

MOV R1, #10; // i = 10

JZ R1, Next; // Done if i=0

ADD R0, R1; // total += i

MOV R2, #1; // constant 1

JZ R3, Loop; // Jump always

Loop:

Next: // next instructions...

SUB R1, R2; // i--

Equivalent assembly program

MOV R3, #0; // constant 0

0

1

2

3

5

6

7

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 9

Architecture of a Simple Microprocessor

• Storage devices for each declared variable• register file holds each

of the variables• Functional units to carry

out the FSMD operations• One ALU carries out

every required operation

• Connections added among the components’ ports corresponding to the operations required by the FSM

• Unique identifiers created for every control signal

Datapath

IRPC

Controller(Next-state and

controllogic; state register)

Memory

RF (16)

RFwa

RFwe

RFr1a

RFr1e

RFr2a

RFr2eRFr1 RFr2

RFw

ALUALUs

2x1 mux

ALUz

RFs

PCld

PCinc

PCclr

3x1 muxMsMweMre

To all input control signals

From all output control signals

Control unit

16Irld

2

1

0

A D

1

0

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL 10

A Simple Microprocessor

FSM operations that replace the FSMD operations after a datapath is created

RFwa=rn; RFwe=1; RFs=01;Ms=01; Mre=1;

RFr1a=rn; RFr1e=1; Ms=01; Mwe=1;

RFr1a=rn; RFr1e=1; Ms=00; Mwe=1;

RFwa=rn; RFwe=1; RFs=10;

RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=00RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=01PCld= ALUz;RFrla=rn;RFrle=1;

MS=10;Irld=1;Mre=1;PCinc=1;

PCclr=1;Reset

Fetch

Decode

IR=M[PC];PC=PC+1

Mov1 RF[rn] = M[dir]

Mov2

Mov3

Mov4

Add

Sub

Jz0110

0101

0100

0011

0010

0001

op = 0000

M[dir] = RF[rn]

M[rn] = RF[rm]

RF[rn]= imm

RF[rn] =RF[rn]+RF[rm]

RF[rn] = RF[rn]-RF[rm]

PC=(RF[rn]=0) ?rel :PC

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

PC=0;

from states below

FSMD

Datapath

IRPC

Controller(Next-state and

controllogic; state

register)

Memory

RF (16)

RFwa

RFwe

RFr1a

RFr1e

RFr2a

RFr2eRFr1 RFr2

RFw

ALUALUs

2x1 mux

ALUz

RFs

PCld

PCinc

PCclr

3x1 muxMsMweMre

To all input control signals

From all output control signals

Control unit

16Irld

2

1

0

A D

1

0

You just built a simple microprocessor!

Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"

ECE 448 – FPGA and ASIC Design with VHDL George Mason University

PIC Microcontroller

ECE 448 – FPGA and ASIC Design with VHDL 12

PIC Microcontroller implemented inside of an FPGA device

PICµController

FPGA

PORTB PORTA

7-Seg Decoder

PORTADisplay

PORTC= PORTC(0)STROBE

CLK

RESET

ECE 448 – FPGA and ASIC Design with VHDL 13

PICROM256 x 12

Data

Addr

PROGRAM

PC

Instruction Decoder

W ALU

COMPUTATIONS

8

12

4CONSTANTS OPCODES

Address Bus

Data Bus

8

8

CONTROL UNIT

MCLR CLK

EXTENDEDALU PORTA PORTB PORTC

4 8 8

DATA

FSRDin Dout

REGFILE

R8

R31

Fsel

4 8 8

8

PIC Microcontroller Core

ECE 448 – FPGA and ASIC Design with VHDL 14

Set Port Directions

RESET

Sum <= ‘0’Counter <= ‘0’

Wait for a rising edge at Port C(0)

Port B <= Port ASum <= Sum + Port A

Counter <= Counter + 1

Counter = 8?

N

Y

Wait for a rising edge at Port C(0)

Port B <= Sum(3 downto 0)

Wait for a rising edge at Port C(0)

Port B <= Sum(7 downto 4)

Flowchart of our PIC program

ECE 448 – FPGA and ASIC Design with VHDL 15

Selected Registers of PIC

W

PC

PORTA

ADDRWorking Register (Accumulator)

Program Counter

PORTBPORTC

050607

0809

R8R9

R30

R311F

Bidirectional Input/Output Ports

Register File (General Purpose

Registers)

TRISA

Direction Registers for Ports A, B & C

TRISB

TRISC

1E

.

.

0A R10

ECE 448 – FPGA and ASIC Design with VHDL 16

Selected PIC Instructions (1)

MOVF f, d

f

W

MOVF f, 0

MOVF f, 1

MOVWF f

W

f

MOVWF f

MOVLW k

k

W

MOVLW k

k <0,255>

f <8,31>

ECE 448 – FPGA and ASIC Design with VHDL 17

Selected PIC Instructions (2)

CLRF f

f

CLRF f

0

CLRW

W

CLRW

0

f <8,31>

ECE 448 – FPGA and ASIC Design with VHDL 18

Selected PIC Instructions (3)

INCF f, d

f

INCF f,1

+1

W

INCF f,0

ECE 448 – FPGA and ASIC Design with VHDL 19

Selected PIC Instructions (4)

ADDWF f, d

W

ADDWF f, 1

+

f

ADDWF f, 0

ECE 448 – FPGA and ASIC Design with VHDL 20

Selected PIC Instructions (5)

ANDWF f, d

W

ANDWF f, 1

and

f

ANDWF f, 0

ECE 448 – FPGA and ASIC Design with VHDL 21

Selected PIC Instructions (6)

SWAPF f, d

SWAPF f, 0

fH fL

W

SWAPF f, 1

ECE 448 – FPGA and ASIC Design with VHDL 22

Selected PIC Instructions (7)

CALL label

CALL label

label

RETLW

RETLWCALL label

label

GOTO label

GOTO label

label

ECE 448 – FPGA and ASIC Design with VHDL 23

Selected PIC Instructions (8)

BTFSC f, b

b7 0

f

f(b) = 0? BTFSC f, b

Yes

No

After-next Instruction

Next instruction

ECE 448 – FPGA and ASIC Design with VHDL 24

Selected PIC Instructions (8)

BTFSS f, b

b7 0

f

f(b) = 1? BTFSS f, b

Yes

No

After-next Instruction

Next instruction

ECE 448 – FPGA and ASIC Design with VHDL 25

Selected PIC Instructions (9)

TRIS f

TRISB

8

TRISA

4

TRISC

8

W

TRIS PORTA

TRIS PORTB

TRIS PORTC

1 – Input port bit direction

0 – Output port bit direction

ECE 448 – FPGA and ASIC Design with VHDL 26

MPASM

*.ASM

*.LST*.HEX

MPSIM

Source File in the PIC Assembly Language

Listing FileHEX File

PIC Programming Environment

ECE 448 – FPGA and ASIC Design with VHDL 27

Questions?