ECE 448 FPGA and ASIC Design with VHDL George Mason University

FPGA Design Flow

ECE 448Lecture 7

ECE 448 – FPGA and ASIC Design with VHDL 2

Resources & Required Reading

Integrated Interfaces: Active-HDL with Synplify®

Integrated Synthesis and Implementation

Movie Demos

Active-HDL Help

ECE 448 – FPGA and ASIC Design with VHDL 3

Design flow (1)

Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;

Specification (Lab Experiments)

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulationSynthesis

ECE 448 – FPGA and ASIC Design with VHDL 4

Design flow (2)

Implementation

Configuration

Timing simulation

On chip testing

ECE 448 – FPGA and ASIC Design with VHDL 5

Design Process control from Active-HDL

ECE 448 – FPGA and ASIC Design with VHDL 6

Simulation Tools

Many others…

ECE 448 – FPGA and ASIC Design with VHDL 7

ECE 448 – FPGA and ASIC Design with VHDL 8

ECE 448 FPGA and ASIC Design with VHDL George Mason University

Synthesis

ECE 448 – FPGA and ASIC Design with VHDL 10

Synthesis Tools

… and others

Synplify Pro Xilinx XST

ECE 448 – FPGA and ASIC Design with VHDL 11

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

beginA1<=A when (NEG_A='0') else

not A;B1<=B when (NEG_B='0') else

not B;Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;

with (L1 & L0) selectY1<=MUX_0 when "00",

MUX_1 when "01",MUX_2 when "10",MUX_3 when others;

end MLU_DATAFLOW;

VHDL description Circuit netlist

Logic Synthesis

ECE 448 – FPGA and ASIC Design with VHDL 12

Features of synthesis tools

• Interpret RTL code

• Produce synthesized circuit netlist in a standard EDIF format

• Give preliminary performance estimates

• Display circuit schematic corresponding to EDIF netlist

ECE 448 – FPGA and ASIC Design with VHDL 13

Timing report after synthesis

Performance Summary *******************

Worst slack in design: -0.924

Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack

Type Group ------------------------------------------------------------------------------------------------------

-exam1|clk 85.0 MHz 78.8 MHz 11.765 12.688 -0.924

inferred Inferred_clkgroup_0System 85.0 MHz 86.4 MHz 11.765 11.572 0.193

system default_clkgroup ==========================================================

=

ECE 448 FPGA and ASIC Design with VHDL George Mason University

Defining Constraints

ECE 448 – FPGA and ASIC Design with VHDL 15

Pin Assignment

LAB2

CLOCKCONTROL(0)

CONTROL(2)CONTROL(1)

RESET

SEGMENTS(0)SEGMENTS(1)SEGMENTS(2)SEGMENTS(3)SEGMENTS(4)SEGMENTS(5)SEGMENTS(6)

P10

K2N6

K3R7K4

T7

M6

M11

R10

P8

E11FPGA

ECE 448 – FPGA and ASIC Design with VHDL 16

XSA Board – XSA-3S1000

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FPGA device present on the board

XC3S1000-4FT256

Spartan 3family

1000 k= 1 M

equivalent logic gates

speed grade

-4= standard

performance

256 pins

package type

ECE 448 – FPGA and ASIC Design with VHDL 18

Arrangement of Components

ECE 448 – FPGA and ASIC Design with VHDL 19

XSA Board Connectivity

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DIP Switches and Pushbuttons

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100 MHz Programmable Oscillator

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ECE 448 – FPGA and ASIC Design with VHDL 23

ECE 448 – FPGA and ASIC Design with VHDL 24

ECE 448 – FPGA and ASIC Design with VHDL 25

Sample UCF File

NET "clock" LOC = "P8";NET "control<0>" LOC = "K4";NET "control<1>" LOC = "K3";NET "control<2>" LOC = "K2";NET "reset" LOC = "E11";NET "segments<0>" LOC = "R10";NET "segments<1>" LOC = "P10";NET "segments<2>" LOC = "M11";NET "segments<3>" LOC = "M6";NET "segments<4>" LOC = "N6";NET "segments<5>" LOC = "T7";NET "segments<6>" LOC = "R7";

ECE 448 – FPGA and ASIC Design with VHDL 26

Pin Assignment

LAB2

CLOCKCONTROL(0)

CONTROL(2)CONTROL(1)

RESET

SEGMENTS(0)SEGMENTS(1)SEGMENTS(2)SEGMENTS(3)SEGMENTS(4)SEGMENTS(5)SEGMENTS(6)

P10

K2N6

K3R7K4

T7

M6

M11

R10

P8

E11FPGA

ECE 448 FPGA and ASIC Design with VHDL George Mason University

Implementation

ECE 448 – FPGA and ASIC Design with VHDL 28

Implementation

• After synthesis the entire implementation process is performed by FPGA vendor tools

ECE 448 – FPGA and ASIC Design with VHDL 29

ECE 448 – FPGA and ASIC Design with VHDL 30

Translation

Translation

UCF

NGD

EDIF NCF

Native Generic Database file

Constraint Editor

User Constraint File

Native Constraint

File

Electronic Design Interchange Format

Circuit netlist Timing Constraints

Synthesis

ECE 448 – FPGA and ASIC Design with VHDL 31

Circuit netlist

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Mapping

LUT2

LUT3

LUT4

LUT5

LUT1FF1

FF2

LUT0

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PlacingCLB SLICES

FPGA

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Routing

Programmable Connections

FPGA

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Configuration

• Once a design is implemented, you must create a file that the FPGA can understand• This file is called a bit stream: a BIT file (.bit extension)

• The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

ECE 448 – FPGA and ASIC Design with VHDL 36

Report files

ECE 448 – FPGA and ASIC Design with VHDL 37

Map report header

Release 7.1.03i Map H.41Xilinx Mapping Report File for Design 'exam1'

Design Information------------------Command Line : c:\Xilinx\bin\nt\map.exe -p 2S200FG256-6 -o map.ncd -pr b -k

4-cm area -c 100 -tx off exam1.ngd exam1.pcf Target Device : xc2s200Target Package : fg256Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.26.6.4 $Mapped Date : Wed Nov 02 11:15:15 2005

ECE 448 – FPGA and ASIC Design with VHDL 38

Map reportDesign Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 144 out of 4,704 3% Number of 4 input LUTs: 173 out of 4,704 3%Logic Distribution: Number of occupied Slices: 145 out of 2,352 6% Number of Slices containing only related logic: 145 out of 145 100% Number of Slices containing unrelated logic: 0 out of 145 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 210 out of 4,704 4% Number used as logic: 173 Number used as a route-thru: 5 Number used as 16x1 RAMs: 32 Number of bonded IOBs: 74 out of 176 42% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25

ECE 448 – FPGA and ASIC Design with VHDL 39

Place & route report

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.

-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels-------------------------------------------------------------------------------- TS_clk = PERIOD TIMEGRP "clk" 11.765 ns | 11.765ns | 11.622ns | 13 HIGH 50% | | | -------------------------------------------------------------------------------- OFFSET = OUT 11.765 ns AFTER COMP "clk" | 11.765ns | 11.491ns | 1 -------------------------------------------------------------------------------- OFFSET = IN 11.765 ns BEFORE COMP "clk" | 11.765ns | 11.442ns | 2 --------------------------------------------------------------------------------

ECE 448 – FPGA and ASIC Design with VHDL 40

Post layout timing report

Timing summary:---------------

Timing errors: 0 Score: 0

Constraints cover 42912 paths, 0 nets, and 1038 connections

Design statistics: Minimum period: 11.622ns (Maximum frequency:

86.044MHz) Minimum input required time before clock: 11.442ns Minimum output required time after clock: 11.491ns

ECE 448 – FPGA and ASIC Design with VHDL 41

Static Timing Analysis

ECE 448 – FPGA and ASIC Design with VHDL 42

Static Timing Analyzer

• Performs static analysis of the circuit performance

• Reports critical paths with all sources of delays

• Determines maximum clock frequency

ECE 448 – FPGA and ASIC Design with VHDL 43

Static Timing Analysis

• Min. Clock Period = Length of The Critical Path

• Max. Clock Frequency = 1 / Min. Clock Period

ECE 448 – FPGA and ASIC Design with VHDL 44

Static Timing Analysis

• Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers

D Qin

clk

D Qout

tP logic

tCritical = tP FF + tP logic + tS FF

ECE 448 – FPGA and ASIC Design with VHDL 45

Timing Characteristics of Combinational Circuits

• Combinational Circuits Are Characterized by Propagation Delays• through logic components (gates, LUTs)• through interconnects (routing delays)

tp LUT tp routing

LUT LUT LUT

Total propagation delay through combinational logic

ECE 448 – FPGA and ASIC Design with VHDL 46

Timing Characteristics of Combinational Circuits (2)

• Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components• Number of logic levels is the number of

logic components (gates, LUTs) the signal propagates through

• Routing Delays Depend on:• Length of interconnects• Fanout

ECE 448 – FPGA and ASIC Design with VHDL 47

Timing Characteristics of Combinational Circuits (3)

• Fanout – Number of Inputs Connected to One Output• Each inputs has its capacitance• Fast switching of outputs with high fanout

requires higher currents and strong drivers

LUT LUT

LUT

LUT

ECE 448 – FPGA and ASIC Design with VHDL 48

Timing Characteristics of Combinational Circuits (4)

• In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays

ECE 448 – FPGA and ASIC Design with VHDL 49

Timing Characteristics of Sequential Circuits (1)

• Timing Features of Flip-flops• Setup time tS – minimum time the input has

to be stable before the rising edge of the clock

• Hold time tH – minimum time the input has to be stable after the rising edge of the clock

• Propagation delay tP – time to propagate input to output after the rising edge of the clock

ECE 448 – FPGA and ASIC Design with VHDL 50

Timing Characteristics of Sequential Circuits (2)

D Q

clk

clk

D

Q

tS tH

tP

Input D must remain

stable during

this interval

Input D can freely

change during

this interval

ECE 448 – FPGA and ASIC Design with VHDL 51

Timing simulation after implementation

ECE 448 – FPGA and ASIC Design with VHDL 52

Timing vs. functional simulation

• Simulation before synthesis is used to verify circuit functionality and may differ from the

one after synthesis and implementation

• Implementation tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays.

• Generated netlist contains many component

instantiation statements with library references

ECE 448 – FPGA and ASIC Design with VHDL 53

SDF file

( DELAYFILE ( CELL( CELLTYPE “XOR”) ( INSTANCE U34.Z_VTX) ( DELAY( INCREMENT ( DEVICE 01 (0.385090:0.385090:0.3850900.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177) ) ) ) )

A part of the SDF file is shown below.It indicates XOR gate delays (low to high, high to low) of minimum, typical and worst case timing

ECE 448 – FPGA and ASIC Design with VHDL 54

Netlist from the synthesis tool

library IEEE;library TC200G;use IEEE.std_logic_1164.all;use TC200G.components.all;entity CONSYN is port( RSTn, CLK, D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; FF_OUT, COMB_OUT, FF_COMB_OUT : out std_logic);end CONSYN;architecture structural of CONSYN issignal XOR8, FF, n70, n71, n72, n73, n74, n75, n76, n67, n68, n69 : std_logic;begin FF_OUT <= FF; COMB_OUT <= XOR8;FF_reg : FD2 port map( Q => FF, QN => n75, D => XOR8, CP => CLK, CD => RSTn) ;

U30 : MUX21L port map( Z => n71, A => n67, B => n68, S => n69);

U31 : EN port map( Z => n67, A => D1, B => D0); U32 : IV port map( Z => n68, A => n67); U33 : EOP port map( Z => n69, A => D6, B => D7); U34 : EO3 port map( Z => n70, A => D3, B => D2,

C => D4); U35 : EO port map( Z => n72, A => D5, B => n70); U36 : EOP port map( Z => XOR8, A => n72,

B => n71); U37 : FA1A port map( S => n73, CO => n76, CI => D3,

A => D2, B => FF); U38 : EO3 port map( Z => n74, A => n68, B => n73,

C => D4); U39 : EOP port map( Z => FF_COMB_OUT, A => D5,

B => n74);end structural;