George Mason University ECE 448 – FPGA and ASIC Design with VHDL

Survey of ReconfigurableLogic Technologies

ECE 448Lecture 17

2 ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 3.6 Programmable Logic Devices

3 ECE 448 – FPGA and ASIC Design with VHDL

Main source

• Clive „Max” Maxfield, The Design Warrior’s Guide

to FPGAs

Chapter 2 Fundamental Concepts

Chapter 3 The Origin of FPGAs

Chapter 4 Alternative FPGA Architectures

4 ECE 448 – FPGA and ASIC Design with VHDL

1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000

FPGAs

ASICs

CPLDs

SPLDs

Microprocessors

SRAMs & DRAMs

ICs (General)

Transistors

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Technology Timeline

5 ECE 448 – FPGA and ASIC Design with VHDL

Programmable Logic Devices

6 ECE 448 – FPGA and ASIC Design with VHDL

PLDs

SPLDs CPLDs

PLAsPROMs PALs GALs etc.

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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

First Programmable Logic Devices

7 ECE 448 – FPGA and ASIC Design with VHDL

Programmable logic device as a black box

Logic gates and

programmableswitches

Inputs

(logic variables) Outputs

(logic functions)

8 ECE 448 – FPGA and ASIC Design with VHDL

General structure of a PLA(Programmable Logic Array)

f 1

AND plane OR plane

Input buffers

& inverters

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

9 ECE 448 – FPGA and ASIC Design with VHDL

Gate-level diagram of a PLA

f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4

10 ECE 448 – FPGA and ASIC Design with VHDL

Customary schematic for a PLA

f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

11 ECE 448 – FPGA and ASIC Design with VHDL

Programmable Array Logic

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

12 ECE 448 – FPGA and ASIC Design with VHDL

Macrocell at the output of PAL

f 1

To AND plane

D Q

Clock

SelectEnable

Flip-flop

13 ECE 448 – FPGA and ASIC Design with VHDL

ProgrammableInterconnect

matrix

Input/output pinsSPLD-like

blocks

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

A generic structure of CPLD(Complex Programmable Logic Device)

14 ECE 448 – FPGA and ASIC Design with VHDL

Structure of a CPLD

PAL-likeblock

I/O

blo

ck PAL-like

block

I/O b

lock

PAL-likeblock

I/O

blo

ck

PAL-likeblock

I/O b

lock

Interconnection wires

15 ECE 448 – FPGA and ASIC Design with VHDL

A section of a CPLD

D Q

D Q

D Q

PAL-like block

16 ECE 448 – FPGA and ASIC Design with VHDL

100 wires

30 wires

Programmablemultiplexer

Connections between the programmable interconnect matrix and simple PAL-like blocks

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

17 ECE 448 – FPGA and ASIC Design with VHDL

Field Programmable

Gate Arrays

18 ECE 448 – FPGA and ASIC Design with VHDL

ASICs

StructuredASICs

GateArrays

StandardCell

FullCustom

Increasing complexity

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

The world of ASICs

19 ECE 448 – FPGA and ASIC Design with VHDL

PLDs ASICs

Standard Cell

Full Custom

Gate Arrays

Structured ASICs*

SPLDs

CPLDs

*Not available circa early 1980s

TheGAP

Gap between PLDs and ASICs

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

20 ECE 448 – FPGA and ASIC Design with VHDL

Programmableinterconnect

Programmablelogic blocks

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

General structure of an FPGA

21 ECE 448 – FPGA and ASIC Design with VHDL

&|

a

b

cy

AND

OR

y = (a & b) | c

0

1

0

1

0

1

MUX

MUX

MUX

0

b

a

1

x

0

y

0

1

MUX0

1

c

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Mux-Based Logic Block

22 ECE 448 – FPGA and ASIC Design with VHDL

Required function Truth table

a b c y

00001111

00110011

01010101

01010111

y = (a & b) | c

&

|

a

b

cy

AND

OR

LUT-Based Logic Block

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

23 ECE 448 – FPGA and ASIC Design with VHDL

16-bit SR

16 x 1 RAM

4-input LUT

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Xilinx Multipurpose LUT

24 ECE 448 – FPGA and ASIC Design with VHDL

16-bit SR

flip-flop

clock

muxy

qe

abcd

16x1 RAM

4-inputLUT

clock enable

set/reset

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Simplified view of a Xilinx Logic Cell

25 ECE 448 – FPGA and ASIC Design with VHDL

16-bit SR

16x1 RAM

4-inputLUT

LUT MUX REG

Logic Cell (LC)

16-bit SR

16x1 RAM

4-inputLUT

LUT MUX REG

Logic Cell (LC)

Slice

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Xilinx CLB Slice

26 ECE 448 – FPGA and ASIC Design with VHDL

CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Xilinx CLB

27 ECE 448 – FPGA and ASIC Design with VHDL

RAM blocks

Multipliers

Logic blocks

RAM Blocks and Multipliers in Xilinx FPGAs

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

28 ECE 448 – FPGA and ASIC Design with VHDL

uP

RAM

I/O

etc.

Main FPGA fabric

Microprocessorcore, special RAM,

peripherals andI/O, etc.

The “Stripe”

Additional cores outside of the main fabric

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

29 ECE 448 – FPGA and ASIC Design with VHDL

uP

(a) One embedded core (b) Four embedded cores

uP uP

uP uP

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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Embedded Microprocessor Cores

30 ECE 448 – FPGA and ASIC Design with VHDL

Clock signal fromoutside world

Clocktree

Flip-flops

Special clockpin and pad

A simple clock tree

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

31 ECE 448 – FPGA and ASIC Design with VHDL

Clock signal fromoutside world

Special clockpin and pad

Daughter clocksused to drive

internal clock treesor output pins

ClockManager

etc.

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Clock Manager

32 ECE 448 – FPGA and ASIC Design with VHDL

Ideal clock signal

1 2 3 4

Real clock signal with jitter

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Superimposed cycles

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Jitter

33 ECE 448 – FPGA and ASIC Design with VHDL

Clock signal fromoutside world

with jitter

Special clockpin and pad

“Clean” daughterclocks used to driveinternal clock trees

or output pins

ClockManager

etc.

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Removing Jitter

34 ECE 448 – FPGA and ASIC Design with VHDL

1.0 x original clock frequency

2.0 x original clock frequency

.5 x original clock frequency

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Frequency Synthesis

35 ECE 448 – FPGA and ASIC Design with VHDL

Figure 4-20

0o Phase shifted

90o Phase shifted

180o Phase shifted

270o Phase shifted

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Phase shifting

36 ECE 448 – FPGA and ASIC Design with VHDL

Main (mother) clock

Untreated daughter clock

De-skewed daughter clock

1 2 3 4

1 2 3 4

1 2 3

Clock signal fromoutside world

Special clockpin and pad

De-skewed daughterclocks used to driveinternal clock trees

or output pins

Daughter clock (monitoreddownstream of the clock manager)

fed back to special input

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Removing Clock Skew

37 ECE 448 – FPGA and ASIC Design with VHDL

01

54

6

7

3

2

General-purpose I/Obanks 0 through 7

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

General-Purpose IO Blocks

38 ECE 448 – FPGA and ASIC Design with VHDL

FPGA

Differential pairs

Transceiver block

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Using High-Speed Tranceivers to Communicate Between Devices

39 ECE 448 – FPGA and ASIC Design with VHDL

Programming Reconfigurable

Logic Devices

40 ECE 448 – FPGA and ASIC Design with VHDL

a

Fat

Logic 1

y = 0 (N/A)&

Faf

b

Fbt

Fbf

Pull-up resistors

NOT

NOT

AND

Fuses

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

A Fusible Link Technologies: Unprogrammed Device

41 ECE 448 – FPGA and ASIC Design with VHDL

a

Fat

Logic 1

y = a & !b&

b

Fbf

Pull-up resistors

NOT

NOT

AND

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

A Fusible Link Technologies: Programmed Device

42 ECE 448 – FPGA and ASIC Design with VHDL

a

Logic 1

y = 1 (N/A)&

b

Pull-up resistors

Unprogrammedantifuses

NOT

NOT

AND

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

An Antifuse Technology: Unprogrammed Device

43 ECE 448 – FPGA and ASIC Design with VHDL

a

Logic 1

y = !a & b&

b

Pull-up resistors

Programmedantifuses

NOT

NOT

AND

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

An Antifuse Technology: Programmed Device

44 ECE 448 – FPGA and ASIC Design with VHDL

(a) Before programming

Substrate

Metal

Oxide

Metal

Amorphous silicon column

(b) After programming

Polysilicon via

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Growing an Antifuse

45 ECE 448 – FPGA and ASIC Design with VHDL

control gate

source drain

control gate

floating gate

source drain

(a) Standard MOS transistor (b) EPROM transistor

Siliconsubstrate

Silicondioxide

Sourceterminal

Control gateterminal

Drainterminal

Sourceterminal

Control gateterminal

Drainterminal

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

EPROM Technology

46 ECE 448 – FPGA and ASIC Design with VHDL

Logic 1

Pull-up resistor

Row(word) line

Column(data) line

EPROMTransistor

Logic 0The Design Warrior’s Guide to FPGAs

Devices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

An EPROM Transistor-Based Memory Cell

47 ECE 448 – FPGA and ASIC Design with VHDL

E2PROM Cell

NormalMOS transistor

E2PROMtransistor

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

EEPROM Technology

48 ECE 448 – FPGA and ASIC Design with VHDL

SRAM

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Static RAM-based Technology

49 ECE 448 – FPGA and ASIC Design with VHDL

Technology SymbolPredominantly

associated with ...

Fusible-link SPLDs

Antifuse FPGAs

EPROM SPLDs and CPLDs

E2PROM/FLASH

SPLDs and CPLDs(some FPGAs)

SRAM FPGAs (some CPLDs)SRAM

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Summary of Programming Technologies

50 ECE 448 – FPGA and ASIC Design with VHDL

State-of-the-art

Feature

Technology node

SRAM AntifuseE2PROM /

FLASH

One or moregenerations behind

One or moregenerations behind

FastReprogramming

speed (inc.erasing)

----3x slower

than SRAM

YesVolatile (must

be programmedon power-up)

NoNo

(but can be if required)

MediumPower

consumptionLow Medium

Acceptable(especially when usingbitstream encryption)

IP Security Very Good Very Good

Large(six transistors)

Size ofconfiguration cell

Very smallMedium-small

(two transistors)

NoRad Hard Yes Not really

NoInstant-on Yes Yes

YesRequires externalconfiguration file

No No

Yes(very good)

Good forprototyping

NoYes

(reasonable)

Yes(in system)

Reprogrammable NoYes (in-system

or offline)

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

51 ECE 448 – FPGA and ASIC Design with VHDL

(a) Host computer (b) Device programmer

Unprogrammeddevice

Programmeddevice

Programming a PLD

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

52 ECE 448 – FPGA and ASIC Design with VHDL

A PLD Programming Unit

(courtesy of Data IO Corp).

53 ECE 448 – FPGA and ASIC Design with VHDL

Configuration data in

Configuration data out

= I/O pin/pad

= SRAM cell

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Configuration of SRAM based FPGAs

54 ECE 448 – FPGA and ASIC Design with VHDL

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

FPGA Configuration Modes

Serial load with FPGA as master

Mode Pins Mode

Serial load with FPGA as slave

Parallel load with FPGA as master

Parallel load with FPGA as slave

Use only the JTAG port

0 0

0 1

1 0

1 1

0

0

0

0

x x1

55 ECE 448 – FPGA and ASIC Design with VHDL

Configuration data in

Mem

ory

Dev

ice

Control

Configurationdata out

FPGA

Cdata In

Cdata Out

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Serial Load with FPGA as a Master

56 ECE 448 – FPGA and ASIC Design with VHDL

Mem

ory

Dev

ice

Control

FPGA

Cdata In

Cdata Out

FPGA

Cdata In

Cdata Out

etc.

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Daisy-Chaining FPGAs

57 ECE 448 – FPGA and ASIC Design with VHDL

Configuration data [7:0]Mem

ory

Dev

ice

Control FPGA

Cdata In[7:0]

Address

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Parallel Load with FPGA as a Master(off-the-shelf memory)

58 ECE 448 – FPGA and ASIC Design with VHDL

Configuration data [7:0]

Mem

ory

Dev

ice

Control FPGA

Cdata In[7:0]

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Parallel Load with FPGA as a Master(special-purpose memory)

59 ECE 448 – FPGA and ASIC Design with VHDL

Mem

ory

Dev

ice

Control

Mic

rop

roce

sso

r

Address

DataP

erip

her

al,

Po

rt, e

tc.

FPGA

Cdata In[7:0]

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Parallel Load with FPGA as a Slave

60 ECE 448 – FPGA and ASIC Design with VHDL

JTAG data in

Input pin fromoutside world

Output pin tooutside world

To internallogic

From internallogic

From previousJTAG filp-flop

To nextJTAG filp-flop

Input pad

Output pad

JTAG flip-flops

JTAG data out

The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Using the JTEG PortJTEG = Joint Test Action Group, IEEE 1149.1

61 ECE 448 – FPGA and ASIC Design with VHDL

JTAG data inJTAG data out

FPGA

Core

Primary scan chain

Internal (core) scan chain

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Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

Internal Processor Boundary Scan Chain

62 ECE 448 – FPGA and ASIC Design with VHDL

Reconfiguration Interfaces in Xilinx FPGAs

SelectMap (8 bits Parallel)

JTAG

Internal PortICAP(Virtex-II)

63 ECE 448 – FPGA and ASIC Design with VHDL

Configuration times

of selected FPGA

devices