Symbol a B 6. & Eo Eox Esi 't Iln AE At hi BYCBO BYCEQ BYEBQ BY DSS C Ca C JC Crn CJS Cfb CGD C J COY Cox Cp Cs D E Ep fT om Gm hfe I IB Ie ID Glossary: Symbol Definitions Description Impact ionization coefficient BIT current gain = lc/lb Small variation, i.e. 6. Yg. Md etc 6. in MOSFET subthreshold Id for a 6. Yd * * * Permittivity of free space F/cm Dielectric constant of silicon dioxide * Dielectric constant of silicon * Time constant Mobility Electron mobility Hole mobility BJT collector area BJT emitter area Temperature acceleration factor Electric field acceleration factor sec cm 2 Ns cm 2 Ns cm 2 Ns cm 2 cm 2 * * Collector-base breakdown voltagelemitter open Collector-emitter breakdown voltagelbase open Emitter-base breakdown voltagelcollector open MOSFET source-drain breakdown with Y gS=O Capacitance Y Y Y Y F Capacitance per unit area NPN collector capacitance NPN emitter capacitance NPN Substrate capacitance MOS flatband capacitance MOSFET gate-drain capacitance Junction capacitance MOSFET overlap capacitance MOS oxide capacitance Capacitance per unit periphery NPN Collector-substrate capacitance Impurity diffusivity Electric Field Peak Electric Field BJT frequency at which 6=1 MOSFET source/drain conductance Transconductance BJT large signal transistor gain Current BJT base current BIT collector current MOSFET drain current F/cm 2 F F F F F F F/cm F F/cm F cm 2 /sec Y/cm Y/cm Hz 1/0 1/0 * A A A A
Transcript
Symbol a B 6. & Eo
Eox
Esi 't
~
Iln
~ AE At hi
BYCBO BYCEQ BYEBQ BYDSS
C Ca CJC
Crn CJS Cfb CGD CJ
COY
Cox Cp Cs D E Ep fT
om Gm hfe I
IB Ie ID
Glossary: Symbol Definitions
Description Impact ionization coefficient BIT current gain = lc/lb Small variation, i.e. 6. Y g. Md etc 6. in MOSFET subthreshold Id for a 6. Y d
* * *
Permittivity of free space F/cm Dielectric constant of silicon dioxide * Dielectric constant of silicon * Time constant Mobility Electron mobility Hole mobility BJT collector area BJT emitter area Temperature acceleration factor Electric field acceleration factor
sec cm2Ns cm2Ns cm2Ns
cm2 cm2
* *
Collector-base breakdown voltagelemitter open Collector-emitter breakdown voltagelbase open Emitter-base breakdown voltagelcollector open MOSFET source-drain breakdown with Y gS=O Capacitance
Y Y Y Y F
Capacitance per unit area NPN collector capacitance NPN emitter capacitance NPN Substrate capacitance MOS flatband capacitance MOSFET gate-drain capacitance Junction capacitance MOSFET overlap capacitance MOS oxide capacitance Capacitance per unit periphery NPN Collector-substrate capacitance Impurity diffusivity Electric Field Peak Electric Field BJT frequency at which 6=1 MOSFET source/drain conductance Transconductance BJT large signal transistor gain Current BJT base current BIT collector current MOSFET drain current
F/cm2 F F F F F F
F/cm F
F/cm F
cm2/sec Y/cm Y/cm
Hz 1/0 1/0
* A A A A
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SImilal DescrjPtiaQ lloil:! IE BJT emitter current A
losat MOSFET saturation current (V d= V g=5V) A
Io MOS gate current A
IoIDL Gate-Induced drain leakage A Is BJT saturation current A
!sub MOSFET Substrate current A Ipp Latchup current A IT Latchup trigger current A IH Latchup holding current A Ik NPN Collector Knee Current A
jrx hole current density Ncm2 High Level Injection critical I density Ncm2 c
k Boltzmann's constant eVfK L MOSFET channel length Jl.m
Leff MOSFET effective channel length Jl.m U Effective funneling length J..I.m M Multiplication factor. * n BIT ideality factor *
Na Substrate (or acceptor) doping concentration cm-3
Nc NPN collector doping concentration cm-3
Nt Donor doping concentration cm-3
q Elementary charge C Q Charge per unit area C/cm2
~ NPN base Gummel Number l/cm2
~ Charge-to-breakdown (in MOS capacitors) C/cm2 Qc NPN Collector Gummel Number l/cm2
Qf Fixed oxide charge density C/cm2
Qit Interface trap charge density C/cm2 Qrn Mobile ion charge density C/cm2
~t Oxide trap charge density C/cm2 Qr Reverse bias stress charge (in NPNs) C R Resistance Ohm=n
RB NPN base resistance n RBext NPN extrinsic base resistance n
Rc Contact resistance n Rc BJT collector resistance n Rch MOSFET channel resistance n RE BJT emitter resistance n
Rlin MOSFET linear region resistance n Rs MOSFET source/drain resistance n So Surface recomination velocity cm/sec S Subthreshold swing in MOSFETs mV/Dec t Time sec T Temperature "C
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~il:mbQI DescriptiQU Uuits tb Base transit time sec td Delay time sec
tox Oxide thickness em VA BJT Early Voltage V
VBE BJT base-emitter voltage V VCB BJT collector-base voltage V vs. Scattering limited velocity cm/sec VD MOSFET drain voltage V
VDsat MOSFET saturation voltage V Vee Supply voltage V Vo MOSFET gate voltage V Vpt Punch through voltage V Vs MOSFET source voltage V VT MOSFET threshold voltage V W MOSFET channel width em
Wb BJT basewidth cm We BJT effective epi thickness cm
Weff MOSFET effective channel width cm X· J Junction depth cm
About the Authors
Chapter 1. Introduction Antonio R. Alvarez was born in Havana, Cuba in 1956. He received a BEE
and an MSEE from the Georgia Institute of Technology in 1978 and 1979 respectively. He joined Motorola as a staff engineer in 1979 working initially in linear technology development --- high voltage Bipolar-DMOS LC.s and Power BiMOS. In 1982 he joined Motorola's Bipolar Technology Center specializing in digital bipolar and BiCMOS technologies, where he became responsible for all aspects of BiCMOS Gate Array and Memory technology. In 1987 he joined Cypress Semiconductor (and later Aspen, a Cypress subsidiary) as program manager for BiCMOS technology. In 1990 he became Vice-President of Research & Development responsible for CMOS and BiCMOS technology development. Mr. Alvarez has developed and taught courses in applied statistics, basic process and device technology, and BiCMOS. He has published over 25 papers and has 2 patents. Mr. Alvarez is a member of the IEEE and has served as subcommittee member and panelist on numerous international conferences.
Chapter 2. Device Design Jim Teplik received the BSEE and MSEE from the University of Cincinnati
in 1979 and 1981 respectively. In 1981 he joined Motorola as a Device Engineer for fast static RAMs. In 1985 he joined the Advanced Technology Center to work on the development of BiCMOS technology. He has been involved with the application of statistical methods coupled with process and device simulation tools to develop and optimize BiCMOS. His latest efforts have involved the optimization and integration of submicron BiCMOS. He has coauthored several papers in the area of BiCMOS technology and the application of response surface design. He is a member of the IEEE and Tau Beta Pi.
Chapter 3. BiCMOS Process Technology Roger H. Eklund received the BS degree in chemistry from Davidson
College in 1974 and the PhD degree in chemistry from the University of Texas at Austin in 1979. After graduating, he joined Texas Instruments where he is currently a Senior Member of the Technical Staff working in the area of process development for submicron Bipolar/BiCMOS technologies.
Roger A. Haken was born in Purley, Surrey, England in 1950. He received the Higher National Diploma in electrical and electronic engineering from Southampton College of Technology in 1971 and MS and PhD degrees in electronics from the University of Southampton in .1972 and 1975 respectively. From 1975 to 1978 he was with GEC Hirst Research Centre working on design of buriedchannel MOSFETs and CCDs, and multilevel polysilicon technology. In 1978 he joined Texas Instrument's Central Research Lab, where he was involved in the design and fabrication of NMOS and CCD circuits for analog signal processing. In 1980 he became responsible for the development of CMOS technology and
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circuit design for a SONOS non-volatile RAM. In 1982, he became manager of the VHSIC 1.2JlIl1 NMOS SRAM technology in the Semiconductor Process and Design Center. From 1984 to 1990 he was research manager of TI's sub-micron CMOS and BiCMOS technology development for VLSI logic. In 1986 DR. Haken was elected a TI Fellow. Dr. Haken was a Sr. Member of the IEEE, and past Publications Chairman and subcommittee member of the International Electron Device Meeting. He held 15 patents and was author or co-author of over 30 technical publications. Dr. Haken passed away in 1990. He is missed.
Robert H. Haveman received a BA (1967) and MS (1970) in electrical engineering from Rice University, and a PhD in electrical engineering (1974) from the University of Colorado. He performed postdoctoral research on thin film optical waveguides at the University of Queensland. In 1976 he became a National Research Council Postdoctoral Fellow at the National Bureau of Standards, where he focused on high speed optical detectors and superconducting LC.s using Josephson junctions. Since joining Texas Instruments in 1978 he has concentrated on process integration for submicron MOS and bipolar devices. A Senior Member of the Technical Staff, his current responsibilities include BiCMOS process development. Since 1985 he has also served as an Adjunct Professor of Electrical Engineering at the Southern Methodist University. He holds nine U.S. patents and has authored or co-authored 18 publications.
Louis N. Hutter was born in Covington, Kentucky in 1954. He received the BS degrees in mathematics and physics from Northern Kentucky University in 1976 and the MS degree in electrical engineering from the M.LT. in 1978. In 1978 he joined Texas Instruments as a process development engineer in the Linear Products department where he was involved in the development of CMOS and high voltage merged technologies. He is presently an engineering manager responsible for advanced CMOS and BiCMOS process development directed towards low and medium voltage analog applications. Elected a Senior Member of the Technical Staff in 1983, Mr. Hutter has authored several articles and has a number of patents pending. He is a member of the IEEE and Sigma Xi.
Chapter 4. Process Reliability Rajeeva Lahri received his PhD (1982) in Electrical Engineering from the
State University of New York at Buffalo. Since 1986, he has been with National Semiconductor. Currently he is Director of CMOS Technology development, responsible for sub-half micron CMOS, BiCMOS, and embedded Non-Volatile technologies. He is a member of the IEEE, has co-authored over 30 technical articles, and holds 2 U.S. patents.
Richard Merrill holds a B.A. in mathematics from the University of Vermont and a B.E. in electrical engineering from Dartmouth College. In 1976, he joined the IBM Watson Research Lab as part of the Silicon Semiconductor Technology group, concentrating on CCD devices. Since 1980, he has been with
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National Semiconductor, involved primarily CMOS device development. He is currently manager of a group responsible for the interface between process and product development
James Shibley received the B.A. in physics (1978) from the University of Chicago and the M.S.E.E. (1982) from the University of Washington. He joined National Semiconductor in 1982, specializing in CMOS process development, including wafer level reliability, yield enhancement, and device physics.
Hai Wang received the M.S. (1987) and PhD (1989) in electrical engineering from Ohio State University. He is currently with National Semiconductor involved in CMOS device reliability and process integration.
Bami Bastani received both MSEE and PhD degrees in solid state electronics from Ohio State University. He joined Intel's Technology Development group in 1980 and worked on the 64K DRAM project as a Senior Device Physicist. Later he became Project Manager for 1 Megabit DRAM and Advanced Microprocessor technologies. Dr. Bastani has been with National (Fairchild) Semiconductor since 1985, where he was responsible for BiCMOS and ECL technology development. In 1989 Dr. Bastani assumed the role of Vice-President Research & Development, adding CMOS technology and package R&D to his responsibilities. Currently he is Vice-President for Non-Volatile Memories. He is a member of the IEEE and on the Technical committees for the Technology Symposium on VLSI and the Device Research Conference.
Chapter S. BiCMOS Digital Design Prasad A. Raje received the B. Tech. degree form the Indian Institute of
Technology, Bombay (1986) and the M.S. (1988)and Ph.D. (1991) degrees from Stanford University, all in Electrical Engineering. In 1987 he worked at Texas Instruments, where he implemented a simulator to predict voltage distributions in I.C. substrates in the presence of substrate current injection. During summer appointments with Hewlett-Packard in 1988 and 1989 he worked on performance analysis of BiCMOS digital logic. His thesis research was in BiCMOS device and circuit design, emphasizing gate delay modeling, scaling and comparison of BiCMOS and CMOS. He is currently a member of the Technical Staff at Hewlett-Packard Labs where he is developing BiCMOS circuit design techniques for high speed CPU applications. He has written over 10 papers in the field of BiCMOS. Mr. Raje is a member of the IEEE.
Chapter 6. Standard Memories Hiep van Tran was born in Viet Nam in January 1949. From 1978 to 1985
he was with Mostek working as an I.C. circuit designer. He joined Texas Instruments in 1985 and is currently a Member of the Technical Staff in the VLSI Design Laboratory. Mr. Tran has been awarded ten U.S. patents.
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Pak Kuen Fung received the BS with honors and the MS degrees in electrical engineering form the University of Arkansas in 1984 and 1986 respectively. While at the University of Arkansas Mr. Fung was supported by a TI Fellowship. He joined Texas Instruments in 1983 part time and full time in 1986 at the VLSI Design Laboratory. He is currently involved in SRAM circuit design using BiCMOS technology. Since joining TI, he has helped design two 16K BiCMOS SRAMs and a 256K BiCMOS SRAM. Mr. Fung is a member of Thu Beta Pi and Eta Kappa Nu.
David B. Scott received the BSc degree in physics in 1974 and the MASc and PhD degrees in electrical engineering in 1976 and 1980 respectively all from the University of Waterloo. In 1979 he joined Texas Instruments as a Member of the Technical Staff. Currently he is a Senior Member of the Technical Staff in the VLSI Design Laboratory working on BiCMOS modeling and design. He has published papers on short-channel effects in MOSFETs, charge-coupled and bucket-brigade devices, bipolar & CMOS technology, silicide contact resistance, hot carrier effects and electrostatic discharge protection. His current research interest is in BiCMOS design techniques.
Ashwin Shah was born in Bombay, India in 1950. He received the B. Technology degree in electrical engineering from the Indian Institute of Technology in 1972 and the MS degree in electrical engineering from the Illinois Institute of Technology in 1975. From 1974 to 1975 he was involved in DRAM design at Mostek. He joined Texas Instruments in 1975 and since then has been involved in the design and development of CCD and other high density MOS memories. He has been involved in various high density DRAM designs and managed the design activities of an experimental4Mbit DRAM. His current research interests are in the area of BiCMOS applications for memories and ASICs, presently managing the BiCMOS design branch of the VLSI Design Lab in the Semiconductor Process and Design Center at TI. Mr. Shah was elected a TI Fellow in 1988. He is a senior member of the IEEE, has been a member of the ISSCC program committee since 1986, and is a member of the Symposium on VLSI Circuits.
Chapter 7. Testability Marc. E. Levitt is a Staff Engineer at Sun Microsystems Computer
Corporation. Currently he is involved in the design and test of ASICs, SPARC processors, and SPARC-based computer systems. He holds a B.S. in computer engineering from Lehigh University and an M.S. and Ph.D. in electrical engineering from the University of Illinois. Dr. Levitt has also held positions at DEC and HP. His interests besides test, include VLSI design, CAD, and electronics manufacturing. He is a member of Tau Beta Pi, Eta Kappa Nu, IEEE and ACM.
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Kaushik Roy received his B. Tech in Electronics and Electrical Communications Engineering from the Indian Institute of Technology in 1983, M.S. in 1985, and Ph.D. in Electrical Engineering in 1990 from the University of lllinois. Currently he is a member of the Technical Staff at the Semiconductor Process and Design Center of Texas Instruments. Dr. Roy's research interests include Testing, VLSI Design, Field Programmable Gate Arrays, and Faulttolerant computing. He is a member of Phi Kappa phi, IEEE, and ACM.
Chapter 8. Analog Design Hae-Seung Lee was born in Seoul, South Korea in 1955. He received the
BS and MS degrees in electrical engineering from the Seoul National University in 1978 and 1980 respectively. He received the PhD degree in electrical engineering from the University of California at Berkeley in 1984, where he worked on self-calibration techniques for AID converter. In 1980, he was a Member of the Technical Staff in the Department of Mechanical Engineering at the Korean Institute of Science and Technology where he was involved in the development of alternative energy sources. Since 1984 he has been with the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, where he is now an Associate Professor. Since 1985, he has served as a consultant to Analog Devices and MIT Lincoln Laboratories. His research interests are in the areas of integrated circuits, devices, fabrication technologies, and solid-state sensors. Prof. Lee is the recipient of a 1988 Presidential Young Investigator's Award.
Chapter 9. CAD Methods for BiCMOS Design Krishnan Sampathkumar received an BSC in Math (1981) in India and
BSEE from Rutgers University in 1984. In 1985 he joined Fairchild Semiconductor as a CAD Engineer in the gate array division. In 1987 he joined Cypress Semiconductor and worked on all aspects of CAD for design verification and user interface in CMOS design. In 1987 he transferred to Aspen Semiconductor as CAD manager to develop the CAD environment for BiCMOS technology. Currently Mr. Sampathkumar is CAD manager for BiCMOS and CMOS technology products at Maxim Integrated Products.
Chapter 10. A Perspective on BiCMOS Trends For a biography of A. R. Alvarez refer to Chapter 1.
