1
GRAPHIC ERA UNIVERSITY DEHRADUN
SEMESTER-I
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Electronic Devices and Circuits or Equivalent
9. Objective: To provide a thorough knowledge of semiconductor devices, their C-V/I-V characteristics, MOSFET Modeling, simulation and parameter extraction for MOSFET or new devices
10. Details of the Course:
Sl. No.
Contents Contact Hours
1 Basic Device Physics Semiconductor Properties, Band Structure of Semiconductors, Three Terminal MOS Structure, MOS System under External Bias, Four Terminal MOS Transistor: Structure and Operation, Threshold Voltage, MOSFET Current Voltage (I-V) Characteristics, Channel Length Modulation, Body Effect, Measurement of Parameters.
10
2 MOSFET Models and Device Scaling MOSFET Models: DC, Small Signal, High Frequency and Noise Models of MOSFETS. MOS Capacitors. Device Scaling, Short and Narrow Channel Effects, MOSFET Channel Mobility Model, DIBL, Charge Sharing and Other Non-Linear Effects.
8
3 SOI Devices Structure of SOI Devices, Advantage of SOI Devices, Partially Depleted and Fully Depleted SOI Devices, Fin-FET, Recent Development in Microelectronics.
8
4 Simulation and SPICE Modeling Principle of Circuit Simulation and its Objectives, SPICE Modeling: SPICE MOSFET Models-Level 1, 2, 3 and 4 Models and their Comparison, Circuit Description, AC, DC, Transient, Noise, Temperature Extra Analysis, Semiconductor Diode, BJT Parameters.
8
5 Modeling and Parameters Extraction JFET, MOSFETS and MESFETS: Modeling of JFET, MOSFET, MESFETS and Parameters Extraction. HBTS: Principles of Hetero-Junction Devices, HBTS, HEMT
8
Semiconductor Devices and Modeling
0 1 3
VDM 101
0
0 100 30 020
3
4
Autumn
Core
2
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices, 3rd Ed., Wiley-Interscience.
2006
2. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, 3rd Ed., Tata McGraw-Hill.
2003
Reference Books
1. M. H. Rashid, Introduction to PSPICE using OrCAD for circuits and electronics, PHI, Ed.
2008
2. N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice, 4th Ed., Springer-Verlag.
1993
3
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Electronics
9. Objective: To provide basic knowledge of digital circuits, SM chart and to write their
VHDL code. After going through this course the students will be able to
design network and VHDL code for various arithmetic operations. Further
they will be able to design with programmable gate arrays and logic
devices.
10. Details of the Course for VHDL:-
Sl.
No.
Contents Contact Hours
1 Introduction to VHDL
VHDL description, combinational networks, modeling Flip-flop
using VHDL, VHDL model for multiplexer, compliance and
simulation of VHDL codes, modeling a sequential machine,
variables, signals and constants, arrays VHDL operators, VHDL
functions, VHDL procedures, packages and libraries, VHDL model
for a counter. Advanced VHDL: Attributes, transport and inertial
delays, operator overloading, multi valued logic and signal
resolution, IEEE-1164, standard logic, generic, generate
statements, synthesis of VHDL codes, synthesis examples.
10
2 Design of networks for arithmetic operations
Design of serial adder with accumulator, state graph for control
networks design of binary Multiplier, multiplication of signed binary
numbers, design of binary divider. Digital design with SM chart:
State machine charts, derivation of SM charts, realizations of SM
charts, implementation of dice game.
8
3 Floating point arithmetic and programmable gate arrays
Representation of floating point numbers, floating point
multiplication, and other floating point operations. Designing with
programmable gate arrays and complex programmable logic
devices: Xilinx 3000 series FPGAs, Xilinx 4000 series FPGAs.
8
Digital System Design using VHDL/Verilog
0 1 3
VDM 102
0
0 100 30 0 20
3
4
Autumn
Core
4
4 Memory models for memories and buses
Static RAM, a simplified 486 bus model, interfacing memory to
microprocessor bus.
8
5 Design example and DSP integrated circuits
UART design, FIR filters Design Using VHDL. DSP integrated
circuits: Introduction, Application –Specific ICs for DSP, DSP
System Design.
8
Total 42
11. Suggested Books:
SL.
No.
Name of Authors/Books/Publishers Year of
Publication/
Reprint
Text Books
1. Charles H Roth Jr, Digital System Design using VHDL, Thomson
Learning.
2002
2. Stephen Brown & Zvonko Vranesic, Fundamentals of digital logic
design with VHDL, TMH, 2nd Ed.
2007
Reference Books
1. John F. Wakerly, Digital design, 4th Ed., PHI.
2005
2. Lars Wanhammar, DSP Integrated Circuits, 2nd Ed., Academic Press. 1999
OR
* Details of the Course for Verilog:-
Sl.
No.
Contents Contact Hours
1 Basic Concepts: Lexical conventions, Data types, System tasks
and compiler directives.
Modules and ports: Modules, Ports, Hierarchical Names.
Gate-Level Modeling: Gate types,Gate delays.
8
2 Dataflow Modeling: Continuous Assignments, Delays,
Expressions, operators, and Operands.Operator types, Examples.
Behavioral Modeling: Stuctured Procedures, Procedural
Assignments, Timing Controls, Conditional Statements, Multiway
Branching, Loops, Sequential and Parallel blocks, Generate
Blocks, Examples.
10
3 Task and Functions: Differences between Tasks and Functions,
Tasks, Functions.
Useful Modeling Techniques: Procedural Continuous
Assignments, Overriding Parameters, Conditional Compilation and
Execution, Time scales, Useful System Tasks.
8
5
Timing and Delays: Types of Delay Models, Path Delay
Modeling, Timing Checks, Delay Back-Annotation
4 Switch-Level Modeling: Switch-Modeling Elements, Examples.
User-Defined Primitives: UDP basics, Combinational UDPs,
Sequential UDPs, UDP Table shorthand symbols,Guidelines for
UDP Design.
8
5 Writing Testbenches: Basic testbenches, testbench structure,
constrained random stimulus generation, object-oriented
programming, Assertion-based verification.
System Verilog Simulation: Event-Driven Simulation, System
Verilog simulation, Races, Delay models,Simulator tools.
System Verilog Synthesis: RTL Synthesis, Constraints,
Synthesis for FPGAs, Behavioral Synthesis,Verifying Synthesis
Results.
8
Total 42
11. Suggested Books:
SL.
No.
Name of Authors/Books/Publishers Year of
Publication/
Reprint
Text Books
1. Samir Palnitkar, Verilog HDL 2/e, Pearson Education. 2004
2. Mark Zwolinski, Digital System Design with System Verilog 1/e,
Pearson Education.
2010
Reference Books
1. J.bhasker, Verilog Synthesis Primer 1/e, B.S.Publications.
1998
2. J.bhasker, Verilog HDL Primer 3/e, Pearson Education. 2005
3. M.Ciletti, Advanced Digital Design with Verilog HDL 2/e, Pearson Education.
2010
6
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: - Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Electronics
9. Objective: To provide a thorough knowledge of digital VLSI circuit design from MOS
device to low power CMOS logic circuit design
10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Review of MOS Technology
MOS structure, MOS under external bias, MOSFET, Scaling of
MOS circuits, Small geometry effects, MOSFET capacitances. MOS
Circuit Design Processes: MOS Layers, Stick Diagrams, Design
Rule and Layout.
10
2 MOS Inverters
Static characteristics: Introduction, Resistive-Load Inverter,
Inverters with n-type MOSFET load, CMOS Inverter. Switching
characteristics and interconnect Effects: Introduction, Delay –Time,
Inverter design with Delay constraints, Estimation of Interconnect
Parasitic, Calculation of Interconnect Delay, Switching Power
Dissipation of CMOS Inverters .
8
3 MOS Logic Circuits
Combinational MOS Logic Circuits: MOS logic circuit with depletion
nMOS Loads, CMOS logic circuits, Complex Logic circuits, CMOS
Transmission Gates. Sequential MOS Logic Circuits: Behavior of
bistable elements, SR latch, Clocked latch and flip-flop, CMOS D
latch and flip-flop. CMOS Technologies: Layout design rules.
CMOS process enhancement. Technology related issues.
8
4 Dynamic Logic Circuits
Basic principles of pass transistor circuits, Voltage Bootstrapping,
Synchronous Dynamic Circuit Techniques, Dynamic CMOS circuit,
High performance Dynamic CMOS Circuits.
8
5 Low power CMOS Logic circuits
Overview of power consumption, Low power design through Voltage
Scaling, Estimation and optimization of switching Activity, Reduction
8
Digital VLSI Circuit Design
0 1 3
VDM 103
0
0 100 30 020
3
4
Autumn
Core
7
of switched capacitance, Adiabatic Logic Circuits.
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Ed., Prentice-Hall of India.
2006
2. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, 3 rd Ed., Tata McGraw-Hill.
2003
Reference Books
1. D. A. Pucknell and K. Eshraghian, Basic VLSI Design, 3rd Ed., Prentice-Hall of India.
1994
2. K. Eshraghian, D. A. Pucknell and S. Eshraghian, Essentials of VLSI Circuit and System, 2nd Ed., Prentice-Hall of India.
2005
3. N.H.E.Weste etal, CMOS VLSI Design (3/e), Pearson. 2005
8
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Electronics
9. Objective: To provide experimental expouser through HDL tools.
10. Details of the Course:-
Sl.
No.
Contents
1. Design and simulation of XOR gate using NAND gate only.
2. Design and simulation of comparator.
3. Design and simulation of Full Adder and Full Substractor.
4. Design and simulation of Multiplexer and Demultiplexer.
5. Design and simulation of Encoder and Decoder.
6. Design and simulation of Flip-Flops.
7. Design and simulation of UP-DOWN counter/Decade counter.
8. Design and simulation of different Shift Registers.
9. Design and simulation of Binary Multiplier.
10. Design and simulation of floating Point Divider.
Inovative
1. FPGA Implementation of Flip-Flops.
2. FPGA Implementation of Binary Multiplier.
3. FPGA Implementation of Full Adder and Full Substractor.
4. As suggested by staff/ lab incharge.
HDL Lab VDM 151
3 0 0
3 0
50 2525 0
4
Spring
Core
9
GRAPHIC ERA UNIVERSITY DEHRADUN
Elective I Name of Department: - Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Design
9. Objective: To provide knowledge of asynchronous circuits and their performance
analysis. So that course the students will be able to
design various control circuits and asynchronous systems.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Fundamentals Handshake protocols, Muller C-element, Muller pipeline, Circuit implementation styles, theory. Static data-flow structures: Pipelines and rings, Building blocks, examples
8
2 Performance A quantitative view of performance, quantifying performance, Dependency graphic analysis. Handshake circuit implementation: Fork, join, and merge, Functional blocks, mutual exclusion, arbitration and metastability.
10
3 Speed-Independent control circuits Signal Transition graphs, Basic Synthesis Procedure, Implementation using state-holding gates, Summary of the synthesis Process, Design examples using Petrify. Advanced 4-phase bundled data protocols and circuits: Channels and protocols, Static type checking, More advanced latch control circuits.
10
4 High-level languages and tools Concurrency and message passing in CSP, Tangram program examples, Tangram syntax-directed compilation, Martin’s translation process, Using VHDL for Asynchronous Design.
8
5 An Introduction to Balsa Basic concepts, Tool set and design flow, Ancillary Balsa Tools The Balsa language: Data types, Control flow and commands, Binary/Unary operators, Program structure. Building library Components: Parameterized descriptions, Recursive definitions. A simple DMA controller: Global Registers, Channel Registers, DMA
6
Asynchronous System Design
0 1 3
VDM-111
0
0 100 30 0 20
3
4
Autumn
Major Elective
10
control structure, The Balsa description. Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Chris. J. Myers, Asynchronous Circuit Design, John Wiley & Sons.
2001
2. Berkel, Handshake Circuits An Asynchronous architecture for VLSI programming, Cambridge University Pres.
2004
Reference Books
1. Jens Sparso, Steve Furber, Principles of Asynchronous Circuit Design, Kluver Academic.
2001
11
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Basic Microprocessors, Assembly Language Programming, C Programming
9. Objective: To understand the architectures of popular microprocessors and microcontrollers as well as the Hardware and Software development environment for microprocessors and microcontrollers. 10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction
Microprocessors and Microcontrollers – Differences – Typical
application environments - Historical Evolution of Microprocessors
– Evolution of Internal Microprocessor Architectures - Tools
available for Microprocessor based development – Historical
Evolution of Microcontrollers – Evolution of Internal Microcontroller
Architectures –Tools available for Microcontroller based
development. Processor Memory Interface: Von-Neumann and
Harvard Architectures- Memory Addressing: Real mode,
Protected Mode, Memory paging – Addressing Modes: Data,
Program, Stack – Cache and cache coherence - TLBs
Instruction Set: Data movement, Program control instructions,
Arithmetic and Logic, Others - Implementation of Instructions –
Control Unit, Microprogramming. Speedup Techniques: Pipelining,
Branch prediction, ultithreading, Multicore.
8
2 Programming and its Concepts
Programming Tools - Modular programming – Object Oriented
Programming – Program Compilation and Linking – Program Flow
Control - Using keyboard and video display – Interrupts and
Interrupt Hooks –Data Conversions- Disk files- Interrupt hooks-
Using assembly languages with C/ C++- Exception Handling -
Microcontroller extras – Timers – I/O Ports – LED, LCD, ADC,
DAC interfacing and control.
8
3 Processor Architecture Case Studies: PENTIUM, POWERPC
(RISC), ARM, CELL, CUDA
10
Advanced Microprocessors and Microcontrollers
0 1 3
VDM-112
0
0 100 30 0 20
3
4
Autumn
Major Elective
12
Architecture Overview–Registers- ALU- Instructions – Memory
management –Special features – Lineage- Speedup techniques –
Architecture advantages and limitations – Memory and I/O
Interfacing - Tools and usage
4 Microcontroller Case Studies: 8051, ARM, AVR, PIC
Architecture Overview-Registers –ALU- Instructions - Memory
Management - Timers-High speed Input and Output –Serial
Interface-I/O ports –Interrupts –A/D converter-Watch dog timer –
Power down feature –External memory and I/O Interfacing –
Architecture advantages and limitations - Tools and Usage.
8
5 Emerging Areas: Multicore, low power, test and debug
support
Multicore architectures and challenges – Multicore programming –
Low Power Techniques – Test and Debug Support within
Microprocessors – JTAG - - Special purpose microprocessors –
DSPs, Network Processors, DIPs.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Barry B. Brey, The Intel Microprocessors 8086/8088, 80, 86,
80286, 80386 80486, Pentium, Pentium Pro Processor,
Pentium II, Pentium III, Pentium 4, Architecture,
Programming and interfacing, Prentice Hall of India Private
Limited, New Delhi.
2003
2. John Peatman, Design with Microcontroller McGraw Hill
Publishing Co Ltd, New Delhi.
2002
Reference Books
1. Alan Clements, “The principles of computer Hardware”, Oxford University Press, 3rd Edition.
2003
13
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Microwave Engineering
9. Objective: After going through this course student will understand the Microwave
Devices, Optoelectronic Devices and Display Devices.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction:Microwave frequencies, microwave transistor,
microwave field effect transistor, tunnel diode, backward diode,
and MIS tunnel diode, Transferred electron devices-Gunn Diode.
Avalanche Transit Time Devices: IMPATT Diode, BARRITT
Diode, DOVETT Diode, and TRAPATT Diode.
10
2 Microwave Integrated Circuit: Introduction, Circuit Forms,
Transmission lines for MICs, Lumped Elements for MICs, Material
for MICs: Substrate, Conductor, dielectric and resistive Materials,
Fabrication techniques, Typical example of fabrication, Hybrid
fabrication
10
3 Microwave Tubes:Klystron, Reflex Klystron and Magnetron,
Traveling wave tubes, microwave detection diodes, application of
microwave.
8
4 Introduction of Optoelectronic Devices: Photovoltaic devices,
Solar Radiation, PN-Homojunction solar cells, Antireflection
coatings, Ideal conversion efficiency, Spectral response, I-V
Characteristics, Temperature and radiation effects, Heterojunction
solar cells, Schottky barrier solar cell, Thin film and amorphous
silicon solar cell, Solar arrays.
8
5 Display Devices: Characterization of displays, drawbacks of
cathode ray tube, Flat panel display: Electroluminescence
displays (Powder and thin films), Plasma display, LCD,
Electronchromic display and electrophoretic display.
6
Total 42
Microwave and Optoelectronic Devices
0 1 3
VDM-113
0
0 100 30 0 20
3
4
Autumn
Minor Elective
14
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices,
3rd Ed., Wiley-Interscience.
2006
2. J. Wilson & JFB Hawkers, Optoelectronics: An introduction,
PHI, New Delhi.
1995
Reference Books
1. S. Y. Liao, Microwave Devices and Circuits,3rd Ed., Pearson
Education.
1990
15
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: - Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Basic Engineering Mathematics
9. Objective: To understand the concept of various soft computing tools, technique and
their application.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction to Soft Computing Concepts, Importance of tolerance in imprecision and uncertainty, Soft Computing Constituents and Conventional Artificial Intelligence, From Conventional AI to Computational Intelligence, Fuzzy logic , Neural Networks and Evolutionary Computation. Basic model of a neuron. Neural network topologies: Feed forward topology and Recurrent topology; Neural network activation functions; Neural network learning algorithms: Supervised learning, Un-supervised learning, Reinforcement learning; Fundamentals of connectionist modeling.
10
2 McCulloach – Pitts Neural model, Perceptron: Sturcture, Linear seprability, XOR Problem, Pattern Classifiers: Hebb Networks, Perceptrons, Adaline, Madaline. Pattern Associators: Auto-associative, Hetro-associative, Hopfield network, Bidirectional Associative Memory. Cometitive Neural Networks: Maxnet, Kohenen’s self-organising network, Learning vector Quantization, Adaptive Resonance Theory.
8
3 Multi-layer Feedforward Network, Generalized Delta rule, Backpropagation learning algorithm, Applications and limitations of Multi layer perceptron. Classification of Neural networks; Radial Basis Function networks: Topology, learning algorithm for RBF, Applications; Industrial commercial applications of Neural networks: Semiconductor manufacturing processes, Communication, Process monitoring and optimal control, Robotics, Decision fusion and pattern recognition.
8
4 Introduction to Fuzzy systems; Crisp Sets, Fuzzy sets and member ship functions, operations on Fuzzy sets; basics of Fuzzy relations; Fuzzy extension principal, Fuzzy logic, Fuzzy rules, Fuzzy reasoning, Fuzzy Inference system, Fuzzification,
8
Neural network & Soft Computing
0 1 3
CSM-111
0
0 100 30 0 20
3
4
Autum
Electiv
16
defuzzification: Centroid Method, Center-of-sums method, Mean-of-Maxima Method, Applications of Fuzzy controllers.
5 Evolutionary Computation: Natural Evolution: a brief review, Genetic Algorithms and Genetic Programming, different operators of Genetic Algorithms, analysis of selection operations, convergence of Genetic Algorithm Hybrid Systems: Neural-Network-Based Fuzzy Systems, Genetic Algorithm for Neural Network Design and Learning, Fuzzy Logic and Genetic Algorithm for Optimization, Applications.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Samir Roy, Udit Chakarborty, “Introduction to Soft Computing Neuro-fuzzy and Genetic Algorithms”, Pearson Education, South Africa.
2013
1. Fakhreddine O. Karray and Clarence De Silva., “Soft Computing and Intelligent Systems Design, Theory, Tools and Applications”, Pearson Education, India.
2009
2. Satish Kumar, “Neural Networks: A Classroom approach”, McGraw Hill.
2004
Reference Books
1. K.H. Lee; First Course on Fuzzy Theory and Applications, Springer.
2005
2. Simon Haykin; Neural Networks- A Comprehensive Foundation, Pearson Education Asia, 2nd ed.
2001
17
GRAPHIC ERA UNIVERSITY DEHRADUN
Elective II Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Antenna and Wave propagation
9. Objective: To acquaint the students with the Interconnection in VLSI, cross talk in
VLSI interconnections and power consideration of various circuits.
10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Signal Propagation on Transmission Lines
Transmission line equations, wave solution, wave vs. circuits, initial
wave, delay time, Characteristic impedance , wave propagation,
reflection, and bounce diagrams Reactive terminations – L, C ,
static field maps of micro strip and strip line cross-sections, per unit
length parameters, PCB layer stackups and layer/Cu thicknesses,
cross-sectional analysis tools, Zo and Td equations for microstrip
and Stripline Reflection and terminations for logic gates, fan-out,
logic switching , input impedance into a transmission-line section,
reflection coefficient, skin-effect, dispersion.
8
2 Multi-Conductor Transmission Lines and Cross Talk
Multi-conductor transmission-lines, coupling physics, per unit
length parameters, Near and far-end crosstalk, minimizing cross-
talk (stripline and microstrip) Differential signaling, termination,
balanced circuits ,S-parameters, Lossy and Lossles models.
9
3 Non-Ideal Effects
Non-Ideal Signal Return Paths – Gaps, Bga Fields, Via Transitions
, Parasitic Inductance And Capacitance , Transmission Line
Losses – Rs, Tanδ, Routing Parasitic, Common-Mode Current,
Differential-Mode Current , Connectors.
9
4 Power Considerations and System Design
Ssn/Sso , Dc Power Bus Design , Layer Stack Up, Smt Decoupling
,, Logic Families, Power Consumption, And System Power Delivery
, Logic Families And Speed Package Types And Parasitic ,Spice,
8
Signal Integrity for High Speed Design
0 1 3
VDM-115
0
0 100 30 0 20
3
4
Autumn
Minor Elective
18
Ibis Models ,Bit Streams, Prbs And Filtering Functions Of Link-Path
Components , Eye Diagrams , Jitter , Inter-Symbol Interference Bit-
Error Rate ,Timing Analysis.
5 Clock Distribution and Clock Oscillators
Timing margin, Clock slew, low impedance drivers, terminations,
Delay Adjustments, canceling parasitic capacitance, Clock jitter.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. H. W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall.
1993
2. Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall.
2003
Reference Books
1. S. Hall, G. Hall, and J. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Wiley.
2000
2. Eric Bogatin , Signal Integrity – Simplified , Prentice Hall. 2003
19
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department:- Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Basic Computer Architecture
9. Objective: To acquaint the students with various ideas of different techniques used to
improve performance in modern computational systems and Quantitative
understanding of design and practical trade-offs involved in the
development of computer architecture.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction to Advanced Computer Architecture and Parallel
Processing
Four Decades of Computing, Flynn’s Taxonomy of Computer
Architecture, SIMD Architecture, MIMD Architecture,
Interconnection Networks.
Multiprocessors Interconnection Networks
Interconnection Networks Taxonomy, Bus-Based Dynamic
Interconnection Networks, Switch-Based Interconnection
Networks, Static Interconnection Networks, Analysis and
Performance Metrics
8
2 Performance Analysis of Multiprocessor Architecture
Computational Models, an Argument for Parallel Architectures,
Interconnection Networks Performance Issues, Scalability of
Parallel Architectures, Benchmark Performance.
Shared Memory Architecture
Classification of Shared Memory Systems, Bus-Based Symmetric
Multiprocessors, Basic Cache Coherency Methods, Snooping
Protocols, Directory Based Protocols, Shared Memory
Programming.
9
3 Message Passing Architecture
Introduction to Message Passing, Routing in Message Passing
Networks, Switching Mechanisms in Message Passing, Message
Passing Programming Models, Processor Support for Message
8
Advanced Computer Architecture and Parallel Processing
0 1 3
VDM-116
0
0 100 30 0 20
3
4
Autumn
Major Elective
20
Passing, Example Message Passing Architectures, Message
Passing Versus Shared Memory Architectures.
Abstract Models
PRAM Model and Its Variations, Simulating Multiple Accesses on
an EREW PRAM, Analysis of Parallel Algorithms, Computing Sum
and All Sums, Matrix Multiplication, Sorting, Message Passing
Model, Leader Election Problem, Leader Election in Synchronous
Rings
4 Network Computing
Computer Networks Basics, Client/Server Systems, Clusters,
Interconnection Networks, Cluster Examples, Grid Computing.
Parallel Programming in the Parallel Virtual Machine:
PVM Environment and Application Structure, Task Creation, Task
Groups, Communication among tasks, Task Synchronization,
Reduction Operations.
8
5 Message Passing Interface (MPI)
Communicators, Virtual Topologies, Task Communication,
Synchronization, Collective Operations, Task Creation, One-Sided
Communication.
Scheduling and Task Allocation
Scheduling Problem, Scheduling DAGs without Considering
Communication, Communication Models, Scheduling DAGs with
Communication, The NP-Completeness of the Scheduling
Problem, Heuristic Algorithms, Task Allocation, Scheduling in
Heterogeneous Environments
9
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach,5th Ed., Elsevier.
2011
2. Hesham El-Rewini and Mostafa Abd-El-Barr, Advanced Computer Architecture and Parallel Processing, John Willy & Sons.
2005
Reference Books
1. Dasgupta, S., Computer Architecture: A Modern Synthesis, vol. 2; Advanced Topics, John Wiley.
1989
2. Decegama, A., The Technology of Parallel Processing: Parallel Processing Architectures and VLSI Hardware, Vol. 1, Prentice-Hall.
1989
21
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Engineering Mathematics
9. Objective:To understand the random variable, random process, stationary & non stationary process and their use in solving engineering and scientific problems.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Probability, review of set theory, joint & conditional probability, Independent event, Random variables and random vectors. Distributions and densities. Conditional distribution & density function, Statistical independence. Mean and variance of random variable, Expectations, moments and characteristic functions.
10
2 Operation on Two random variables, correlation, covariance, vector space of random variables, Multiple random variables, operation on multiple random variable, central limit theorem, Infinite sequences of random variables. Convergence concepts. Laws of large numbers, Tchebycheff inequality and estimation of unknown parameters.
10
3 Stochastic processes, stationarity & independence, Stationarity in the strict and wide senses. Ergodicity in the q.m.sense. Widesense stationary processes. Herglotz’s and Bochner’s theorems, wide-sense stationarity, ergodicity, correlation functions & its properties, Gaussian random process, Covariance functions and their properties, Separability and measurability.
10
4 Spectral characteristic of random process, power spectral density & their properties, relation between PSD & autocorrelation function, cross power spectrum density, Wiener-Chirchiff theorem.
6
5 Linear system with random inputs, random signal response of
linear system, spectral characteristics of system, bandpass,
bandlimited and narrowband process, white noise process,
modeling of noise source.
6
Total 42
Probability and Stochastic Processes
0 1 3
CSM-102
0
0 100 30 0 20
3
4
Autumn
Minor Elective
22
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Peyton Z. Peebles, Probability, random variable, and random signal principle, , 4th Edition, McGraw-Hill.
2000
2. R.B.Ash & C.Doleans-Dade, Probability and Measure Theory (2/e), Elsevier.
2005
Reference Books
1. E.Wong & B.Hajek, Stochastic Processes in Engineering systems, Springer.
1985
2. B. G. Streetman and S. Banerjee, Solid State Electronic Devices, 6th Ed., Prentice Hall of India.
2005
23
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Data Network
9. Objective: To acquaint the students with importance of Computer Networks, different switching technique, various protocols and their applications. 10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction
Building a Network; Requirements- Connectivity, Cost-Effective
Resource Sharing, Support for Common Services; Network
Architecture- Layering and Protocols, OSI Architecture, Internet
Architecture; Performance- Bandwidth and Latency, Delay×
Bandwidth Product, High-Speed Networks.
10
2 Direct Link Networks
Hardware Building Blocks-nodes, links; error Detection- Two-
dimensional Parity, Internet checksum Algorithm, cyclic
Redundancy Check; reliable Transmission- Stop-and-Wait, Sliding
Window, Concurrent Logical Channels; Rings (802.5, FDDI) –
Token Ring Media Access Control, Token Ring Maintenance,
FDDI.
10
3 Packet Switching:
Switching And Forwarding Datagrams,Virtual Circuit Switching,
Source Routing; Bridges and LAN Switches – Learning Bridges,
Spanning Tree Algorithm, Broadcast and Multicast, Limitations of
Bridges; cell switching (ATM) – Cells, Segmentation and
Reassembly, Virtual Paths, Physical Layers for ATM.
10
4 Internetworking
Simple internetworking (IP) – What Is an Internetwork?, Service
Model, Global Address, Datagram Forwarding in IP, Address
Translation(ARP), Host Configuration(DHCP), Error
Reporting(ICMP), Virtual Networks and Tunnels; Routing –
Network as a Graph, distance Vector(RIP), Link State(OSPF),
6
0 1 3
CSM-118
0
0 100 30 0 20
3
4
Autumn
Minor Elective
Computer Network CSM-118
24
Metrics, Routing for Mobile Hosts, Global Internet – Subnetting,
Classless Routing(CIDR), Interdomain Routing(BGP), Routing
Areas, IP Version 6(IPv6).
5 End to End Protocols
Simple demultiplexer (UDP); Reliable byte stream (TCP) – End-to-
End Issues, Segment Format, Connection Establishment and
Termination, Sliding Window Revisited, Triggering Transmission,
Adaptive Retransmission, Record Boundaries, TCP Extensions,
Alternative Design Choices. Issues in resource allocation ,
Taxonomy, Evaluation Criteria; Queuing discipline, Fair Queuing;
TCP Congestion Control, Slow Start, Fast Retransmit and Fast
Recovery; Congestion-Avoidance mechanisms – DECbit, Random
Early Detection (RED), Source-Based Congestion Control.
6
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Larry L. Peterson and Bruce S. Davie: Computer Networks – A Systems Approach, 4th Edition, Elsevier.
2007
2. Alberto Leon-Garcia and Indra Widjaja: Communication Networks -Fundamental Concepts and Key Architectures, 2nd Edition Tata McGraw-Hill.
2004
Reference Books
1. Behrouz A. Forouzan: Data Communications and Networking, 4th Edition, Tata McGraw Hill.
2006
2. William Stallings: Data and Computer Communication, 8th Edition, Pearson Education.
2007
25
GRAPHIC ERA UNIVERSITY DEHRADUN
SEMESTER-II
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Signal Processing
9. Objective: To acquaint the students with fundamentals of digital signal
processing and various structures which are useful in digital signal
processor implementation.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction
Linear System Theory- Convolution- Correlation - DFT- FFT-
Basic concepts in FIR Filters and IIR Filters- Filter Realizations.
Representation of DSP Algorithms-Block diagram-SFG-DFG.
8
2 Iteration Bound
Data-Flow Graph Representations, Loop Bound and Iteration
Bound, Algorithms for Computing Iteration Bound, Iteration Bound
of Multirate Data-Flow Graph. Pipelining and Parallel Processing:
Pipelining of FIR Digital Filters, Parallel Processing, Pipelining and
Parallel Processing for Low Power.
8
3 Retiming
Definitions-Properties and problems- Solving Systems of
Inequalities, Retiming techniques
Fast Convolution
Cook-Toom Algorithm, Winograd Algorithm, Iterated Convolution,
Cyclic Convolution, Design of Fast Convolution Algorithm by
Inspection.
8
4 Algorithmic Strength Reduction in Filters and Transforms
Parallel FIR filters, Discrete Cosine Transform and Inverse DCT,
Parallel architectures for Rank Order filters-Odd Even Merge sort
architecture, Rank Order filter architecture, Parallel Rank Order
filters-Running Order Merge Order Sorter, Low power Rank Order
9
Digital Signal Processing Structures for VLSI
0 1 3
VDM 201
0
0 100 30 0 20
3
4
Spring
Core
26
filter.
Pipelined and Parallel Recursive Filters
Pipeline Interleaving in Digital Filters- Pipelining in 1st Order IIR
Digital Filters- Pipelining in Higher-order IIR Filters-Clustered Look
ahead and Stable Clustered Look ahead-Parallel Processing for
IIR Filters and Problems.
5 Scaling and Round off Noise
Scaling and Round off Noise- State Variable Description of Digital
Filters, Scaling and Round off Noise Computation, Round Off
Noise in pipelined IIR Filters, Computation Using State Variable
Description, Slow-Down, Retiming and Pipelining.
9
Total 42
11. Suggested Books:
SL.
No.
Name of Authors/Books/Publishers Year of
Publication/Reprint
Text Books
1. K. K. Parhi ,VLSI Digital Signal Processing , John-Wiley. 1999
2. John G. Proakis, Dimitris G. Manolakis, Digital Signal
Processing, Prentice Hall of India.
1995
Reference Books
1. Richard J. Higgins, Digital signal processing in VLSI, Prentice
Hall.
1990
27
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Electronics Devices and Circuits
9. Objective: To acquaint the students with the frequency response for MOS configurations, design of multistage amplifier and the feedback configurations. 10. Details of the Course:-
Sl.
No.
Contents Contact Hours
1 Models for Integrated Circuit Active Devices
The depletion region of a P-N junction, depletion region
capacitance and junction breakdown, small signal models of MOS
transistor, MOS transistor frequency response.
6
2 Single-Transistor and Multiple-Transistor Amplifier
Common source stage with Resistive Load, CS stage with diode
connected load, CS stage with current source load, CS stage with
triode load, CS stage with source generation, source follower and
common gate configuration
9
3 Multistage Amplifier and Differential amplifier
Darlington configuration and cascade configuration, Introduction
to the small signal analysis of differential amplifier, small signal
characteristics of balanced differential amplifier and OPAMP
design.
9
4 Current Mirrors, Active Loads and References
Simple current mirror, cascade current mirror, Wilson current
mirror, Common source amplifier with complementary load,
voltage and current references.
9
5 Feedback
General consideration, properties of feedback circuits, feedback
configuration, Nonlinear analog circuits: Precision rectification,
phase locked loop.
9
Total 42
CMOS Analog VLSI Design
0 1 3
VDM 202
0
0 100 30 0 20
3
4
Spring
Core
28
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Paul R. Gray and R. G. Meyer, Analysis and design of analog
integrated circuits John Wiley and Sons, USA, (4th Edition).
2001
2. Mohammed Ismail and Terri Faiz, Analog VLSI signal and
information process, McGraw-Hill Book Company.
1994
Reference Books
1. B. Razavi, Design of analog CMOS integrated circuits,
McGraw-Hill Edition.
2002
2. R. Jacob Baker, H. W. Li, and D.E. Boyce, CMOS circuit
design, layout and simulation, Prentice-Hall of India, 1998.
1998
29
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: - Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: VLSI Design and Technology
9. Objective: To acquaint the students with fabrication techniques used for VLSI devices
and various steps involved in fabrication process.
10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Wafer preparation and oxidation
Electron grade silicon, Crystal growth, Wafer preparation,
processing considerations, Vapor phase epitaxy and molecular
beam epitaxy, Film characteristics, SOI structure, Oxide formation,
kinetics, oxidation systems, dry and wet oxidation, masks properties
of SiO2, Oxidation defects
10
2 Lithography and etching
Optical, electron, X-ray and ion lithography methods, positive and
negative photo resist. Plasma properties, size, control, etch
mechanism, etch techniques and equipments.
8
3 Deposition and diffusion
Deposition process and methods, Diffusion in solids, Diffusion
equation and diffusion mechanisms, Ion implantation, damage and
annealing, ion implantation systems.
8
4 Metallization and IC fabrication
Metallization and its applications, Process simulation of ion
implementation, diffusion, oxidation, epitaxy, lithography, etching
and deposition, NMOS, CMOS and bipolar IC technologies and IC
fabrication.
8
5 Packaging
Analytical and assembly techniques and Packaging of VLSI
devices.
8
Total 42
VLSI Technology
0 1 3
VDM 203
0
0 100 30 0 20
3
4
Spring
Core
30
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. S. M. Sze, VLSI Technology (2/e) , McGraw Hill. 1988
2. W. Wolf, Modern VLSI Design, (3/e), Pearson. 2002
Reference Books
1. S. K. Gandhi, VLSI Fabrication Principles Silicon And Gallium
Arsenide (2/e) , Wiley-INDIA.
1994
2. Wai Kai Chen, VLSI Technology, CRC press. 2003
31
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Semiconductor Devices and Modeling
9. Objective: To provide experimental exposure through various simulation and process tools. 10. Details of the Course:-
Sl.
No.
Contents
1. AN INVERTER
a) To create a library and build a schematic of an Inverter and create a symbol
for the Inverter.
b) To set up and run simulations on the Inverter_Test design.
i. Simulation
ii. Creating Layout View of Inverter
iii. Parasitic Extraction
iv. Creating the Configuration View 2. A 2 INPUTS NAND GATE
a) To create a library and build a schematic of a two inputs NAND Gate and
create a symbol for the NAND gate.
b) To set up and run simulations on the NAND_Test design.
i. Simulation
ii. Creating Layout View of NAND Gate
iii. Parasitic Extraction
iv. Creating the Configuration View 3. MOS DIFFERENTIAL AMPLIFIER
a) To create a new cell view and build Differential Amplifier and create a
symbol for the Differential Amplifier.
b) To build Differential Amplifier Test circuit using your Differential Amplifier.
c) To set up and run simulations on the Differential Amplifier Test design.
i. Analog Simulation
ii. Creating a Layout View of Diff_ Amplifier
iii. Physical Verification
4. COMMON SOURCE AMPLIFIER
a) To create a new cell view and build Commom Source Amplifier and
3 0 0
CSM-118
3
50 0 25 25 0
0
2
Spring
Core
Analog Circuit Design Lab VDM-251
32
create a symbol for the Commom Source Amplifier.
b) To build cs_amplifier_test circuit using your cs_amplifier.
c) To set up and run simulations on the cs_amplifier_test design.
i. Analog Simulation
ii. Creating a Layout View of Common Source Amplifier
iii. Physical Verification
5. COMMON DRAIN AMPLIFIER
a) To create a new cell view and build Commom Drain Amplifier and
create a symbol for the Commom Drain Amplifier.
b) To build cd_amplifier_test circuit using your cd_amplifier.
c) To set up and run simulations on the cd_amplifier_test design.
i. Analog Simulation
ii. Creating a Layout View of Common Drain Amplifier
iii. Physical Verification
6. OPERATIONAL AMPLIFIER
d) To create a new cell view and build Operational Amplifier and create a
symbol for the Operational Amplifier.
e) To build op-amp_test circuit using your op-amp.
f) To set up and run simulations on the op-amp_test design.
i. Analog Simulation
ii. Creating a Layout View of Common Drain Amplifier
iii. Physical Verification
Inovative
1. Perform a 2D/3D simulation of PN Junction and analyze its application as a rectifier.
2. Design and Simulation of 2D/3D NMOS channel length 20 nm or higher and also
extract its performance parameters.
3. As suggested by staff/ lab incharge.
33
GRAPHIC ERA UNIVERSITY DEHRADUN
Elective III
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Semiconductor device modeling; organic and
inorganic electronic materials, electronics devices and circuits,
9. Objective:To analysis and modeling of organic devices and circuits based on organic materials and acquaint the students with the conducting polymers, small molecules, organic materials, different structures of OFETs, Study of OLEDs and various applications of OFET. 10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Organic Materials and Device Physics
Introduction; Organic Materials: Conducting Polymers and Small
molecules, Organic Semiconductors: p-type and n-type
semiconductors, Charge Transport and Injection in Organic
Semiconductors, Energy Band Diagram, Source and Drain
Electrodes, Gate Dielectrics, Substrate, Gate Electrode materials,
Comparison between Organic and Inorganic Semiconductors.
9
2 Organic Field Effect Transistors (OTFTs)
Overview of Organic Field Effect Transistor (OFET); Operating
Principle; Classification of Various Structures of OFETs; Output
and Transfer Characteristics; Analysis of Electrical and Thermal
properties, Different Models, Effect of Self Assemble Monolayer
(SAM); OFETs Performance Parameters: Impact of Structural
Parameters on OFET; Extraction of Various Performance
Parameters, Merits and Demerits, Stability Issues, Future Scope.
8
3 Analysis and Modeling of Organic Devices
Various Defects and Effects in Organic Devices; Contact
Resistance: Origin of Contact Resistance, Contact Resistance
Extraction, Modeling of OTFT Different Structures, Analysis,
Validation and Comparison of OFET, Analysis and Simulation of
OFET Electrical Characteristics.
8
4 Organic Light Emitting Diodes (OLEDs) and Solar Cells
Introduction; Different Organic Materials; Classification of OLEDs,
Output and Transfer Characteristics; Analysis and Modeling of
7
Organic Electronics Devices and Circuits
0 1 3
VDM 221
0
0 100 30 0 20
3
4
Spring
Minor Elective
34
OLEDs: Optical, Electrical and Thermal properties, Merits and
Demerits; Stability Issues; OLEDs as display Applications, Solar
cell: Materials, Characteristics, Applications and Future Scope.
5 Applications
Organic Complementary Technology: Organic Inverters; Organic
Complementary Inverter Circuits, Hybrid Complementary
Inverters, Comparison between All P-Type, Fully Organic and
Hybrid Complementary Inverter Circuits; Logic Circuit
Implementation; Organic Memory: Organic Static Random Access
Memory (OSRAM) and other Important Organic Memory Designs.
10
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Hagen Klauk, Organic Electronics: Materials, Manufacturing and Applications, Wiley-VCH Verlag Gmbh & Co. KGaA, Germany.
2006
2. Klaus Mullen, Ullrich Scherf, Organic Light Emitting Devices: Synthesis, Properties and Applications, Wiley-VCH Verlag Gmbh & Co. KGaA, Germany.
2005
Reference Books
1. Hagen Klauk, Organic Electronics II: More Materials and Applications, Wiley-VCH Verlag Gmbh & Co. KGaA, Weinheim, Germany, 2012
2012
2. Flora Li, Arokia Nathan, Yiliang Wu, Beng S. Ong, Organic Thin Film Transistor Integration: A Hybrid Approach, Wiley-VCH, Germany; 1st Ed.
2011
3. Wolfgang Brutting, Physics of Organic Semiconductors, Wiley-VCH Verlag Gmbh & Co. KGaA, Germany.
2005
35
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Biomedical Instrumentation
9. Objective: To acquaint the students with the neurochemical and neuropotential
circuits and analyse CMOS circuits for biomedical devices.
10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Introduction
Wireless Integrated Neurochemical and Nuropotential circuits:
Introduction, Neurochemical Sensing, Neuropotencial Sensing,
RF Telemetry and Power Harvesting in implanted Devices,
Multimodal Electrical and Chemical Sensing. Visual Cortical
Neuroprosthesis: A System Approach: Introduction, System
Architecture, Prosthesis Exterior Body Unit and Wireless Link,
Body Implantable Unit, System Prototype.
9
2 CMOS Circuits for Biomedical Implantable Devices
Introduction, Inductive Link to Deliver Power to Implants, High
Data Rate Transmission through Inductive Links, Energy and
Bandwidth Issues in Multi-Channel Bio-potential Recording.
Towards Self –Powered Sensors and Circuits for Biomedical
Implants: Introduction, Stress, Strain and fatigue Predication, In
Vivo strain measurement and motivation. Fundamental of
Piezoelectric-Transduction and power delivery, Sub-Microwatt
Piezo-Powered VLSI circuits, Design and Calibration of a
complete Floating –Gate Array.
9
3 CMOS Circuits for Wireless Medical Application
Introduction, Spectrum Regulations for Medical use, Integrated
receiver and transmitter Architecture, Radio Architecture, System
Budget, Low Noise Amplifier, Mixer, Polyphase Filter, Power
Amplifier, PLL. Error Correcting Codes for In Vivo RF wireless
Links.
8
4 Microneedles
Introduction, Fabrication Methods for Hollow out –of –plane
Microneedles, Application for Microneedles. Integrated Circuit for
Neural Interfacing: Introduction, Nature of Neural signals, Neural
Signal Amplification.
8
VLSI Circuits for Biomedical Application
0 1 3
VDM 222
0
0 100 30 0 20
3
4
Spring
Minor Elective
36
5 Integrated Circuits for neural Application
Integrated Circuit for Neural Interfacing (Neurochemical
Recording), Integrated Circuit for Neural Interfacing (Neural
Stimulation): Introduction, Electrode Configuration and Tissue
Volume Conductor, Electrode- Electrolyte interface, Efficacy,
Stimulus Generator, Stimulation Front End Circuits.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Kris Iniewski, VLSI Circuit Design for Biomedical Application, Artech House Publishers.
2008
2. D. A. Hodges, H. G. Jackson and R. A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd Ed., Tata McGraw-Hill.
2005
Reference Books
1. Parag. K. Lala, Digital circuit testing and testability, Academic Press.
1997
2. Ashok K. Sharma, Semiconductor memories technology, testing and reliability, Prentice-Hall of India Private Limited, New Delhi.
1997
37
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital communication
9. Objective: To determine the modulation techniques for RF circuits, VLSI Implementation of RF systems and acquainted with the RF Synthesizer.. 10. Details of the Course:-
Sl.
No.
Contents Contact
Hours
1 Introduction
Introduction to RF and wireless technology: Complexity, design
and applications, choice of technology. Basic concepts in RF
design: Nonlinearly and time variance, intersymbol interference,
random processes and noise.
8
2 Modulation techniques for RF circuits
Definition of sensitivity, dynamic range, conversion gains and
distortion. Analog and digital modulation for RF circuits:
Comparison of various techniques for power efficiency. Coherent
and non-coherent detection.
10
3 Detectors and transistor modeling
Mobile RF communication systems and basics of multiple access
techniques. Receiver and transmitter architectures and testing
heterodyne, homodyne, image-reject, direct-IF and sub-sampled
receivers. Direct conversion and two steps transmitters. BJT and
MOSFET behavior at RF frequencies, modeling of the transistors
and SPICE models.
8
4 Mixers and oscillators
Noise performance and limitation of devices. Integrated parasitic
elements at high frequencies and their monolithic implementation.
Basic blocks in RF systems and their VLSI implementation: Low
Noise Amplifiers design in various technologies, Design of mixers
at GHz frequency range. Various mixers, their working and
implementations, Oscillators: Basic topologies VCO and definition
of phase noise. Noise-Power trade-off. Resonator less VCO
design. Quadrature and single-sideband generators.
8
5 RF Synthesizer
Radio frequency synthesizes: PLLS, various RF synthesizer
architectures and frequency dividers, Power Amplifiers design.
8
RF Microelectronics
0 1 3
VDM 223
0
0 100 30 0 20
3
4
Spring
Minor Elective
38
Linearization techniques, Design issues in integrated RF filters.
Some discussion on available CAD tools for RF VLSI designs.
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. B. Razavi, RF Microelectronics, Prentice-Hall PTR. 1998
2. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press.
1998
Reference Books
1. R. Jacob Baker, H. W. Li, and D.E. Boyce, CMOS circuit design, Layout and simulation, Prentice-Hall of India
1998
2. Y. P. Tsividis, Mixed analog and digital VLSI devices and technology, McGraw Hill, 1996.
1996
39
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital Electronics
9. Objective: To acquaint the students with the various aspects of memory architecture, memory cell design, fault modeling and testing. 10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction
Static random access memories (SRAMs): SRAM cell structures,
MOS SRAM architecture, MOS SRAM cell and peripheral circuit
operation, bipolar SRAM technologies, silicon on insulator (SOL)
technology, advanced SRAM architectures and technologies,
application specific SRAMs.
Dynamic random access memories (DRAMs): DRAM technology
development, CMOS DRAM, DRAMs cell theory and advanced cell
structures, bicmos DRAMS, soft error failures in DRAMS, advanced
DRAM designs and architecture, application specific DRAMs.
9
2 Memories
Masked read-only memories (ROMs), high density ROMs,
programmable read-only memories (PROMs), bipolar PROMs, CMOS
PROMs, erasable (UV) programmable read-only memories
(EPROMs), floating gate EPROM cell, one-time Programmable (OTP)
EPROMs, electrically erasable PROMs (EEPROMs), EEPROM
technology and architecture, nonvolatile SRAM, flash memories
(EPROMs or EEPROM), advanced flash memory architecture.
10
3 Fault modeling and testing
RAM fault modeling, electrical testing, pseudo random testing, megabit
DRAM testing, nonvolatile memory modeling and testing, IDDQ fault
modeling and testing, application specific memory testing.
8
4 Reliability Issues and Radiation
General reliability issues- RAM failure modes and mechanism,
nonvolatile memory reliability, reliability modeling and failure rate
prediction, design for reliability, reliability test structures, reliability
9
Design of Semiconductor Memories
0 1 3
VDM 224
0
0 100 30 0 20
3
4
Spring
Major Elective
40
screening and qualification. Radiation effects-Single event
phenomenon (SEP), radiation hardening techniques, radiation
hardening process and design issues, radiation hardened memory
characteristics, radiation hardness assurance and testing, radiation
dosimetry, water level radiation testing and test structures.
5 Random access memories and testing
Ferroelectric random access memories (FRAMs), gallium arsenide
(GaAs) FRAMs, analog memories, Magneto- resistive random access
memories (MRAMs), experimental memory devices. Memory hybrids
and MCMs (2D)-memory stacks and MCMs (3D)-memory MCM testing
and reliability issues, memory cards, high density memory packaging
future directions.
6
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Ashok K. Sharma, Semiconductor Memory Technology, Testing And Reliability, Prentice-Hall of India Private Limited, New Delhi.
1997
2. Brent Keeth and R. Jacob Baker, DRAM Circuit Design: A tutorial,Wiley- IEEE press.
2000
Reference Books
1. Betty Prince, High performance memories: New architecture DRAMs and SRAMs- Evolution and function, Wiley.
1999
41
GRAPHIC ERA UNIVERSITY DEHRADUN
Elective IV
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Basic Microprocessor, C Programming, Assembly Programming 9. Objective: To provide an understanding of the different Processors and controller
architecture, Hardware and Software development environment for
embedded systems.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction: Examples of Embedded Systems, Concepts of
Embedded Systems Design, Design challenges, Processor
technology, IC technology, Design technology, Custom single
purpose processor hardware.
General Purpose Processor: Introduction, basic architecture,
operation, super-scalar and VLSIIW architecture, application
specific instruction set processors (ASIPS), microcontrollers, digital
signal processors, selecting a microprocessor.
8
2 Memory: Introduction, Memory write ability, Storage performance,
Tradeoffs, Common memory types Memory hierarchy and cache,
Multi level caches, TLBs
AVR 8515 microcontroller: Architecture and Programming in
assembly and C
Interfacing Analog and digital blocks: Analog-to-Digital
Converters (ADCs), Digital to Analog Converters (DACs),
Communication basics and basic protocol concepts,
Microprocessor interfacing: I/O addressing, Port and Bus based,
I/O, Memory mapped I/O, Standard I/O interrupts, Direct Memory
Access(DMA), Advanced communication principles parallel, serial
and wireless.
10
3 Peripheral devices: Buffers and latches, Crystal, Reset circuit,
Chip select logic circuit, timers and counters and watch dog timers,
Universal asynchronous receiver, transmitter (UART), Pulse width
modulators, LCD controllers, Keypad controllers. Design tradeoffs
due to thermal considerations.
8
Embedded System
0 1 3
VDM 225
0
0 100 30 0 20
3
4
Spring
Major Elective
42
4 Embedded software development environments: Real time
operating systems,
Kernel architecture: Hardware, Task/process control subsystem,
Device drivers, File subsystem, System Calls, Embedded
operating systems,
Task scheduling in embedded systems: task scheduler, first in
first out, shortest job first, round robin, priority based scheduling,
Context switch and Task Synchronization: Mutex, Semaphore,
Timers, Types of Embedded Operating Systems,
Programming Languages: Assembly Languages, High level
languages.
8
5 Development for embedded systems: Embedded system
development process, Determine the requirements, Design the
system architecture, Choose the operating system, Choose the
processor, Choose the development platform, Choose the
programming language, Coding issues, Code optimization,
Efficient input/output, Testing and debugging, Verify the software
on the host system, Verify the software on the embedded system.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Frank Vahid /Tony Givargis, Embedded System Design- A unified Hardware/software introduction, John Wiley & Sons.
2002
2. David E Simon,An embedded software primer, Pearson education Asia.
2001
Reference Books
1. Dasgupta, S., Computer Architecture: A Modern Synthesis, vol. 2; Advanced Topics, John Wiley.
1989
43
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital VLSI Design 9. Objective:To provide thorough knowledge of VLSI physical design algorithms for placement, routing and floor planning and use of Design Automation Tools. 10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 VLSI Design Automation Tools
Design cycle, design styles, algorithms and system design,
Structural and logic design, Transistor level design, Layout
design, Verification methods, Design management tools.
10
2 Layout Compaction, Placement and Routing
Design rules, symbolic layout, Applications of compaction,
Formulation methods, Algorithms for constrained graph
compaction, Circuit representation, Wire length estimation,
Placement algorithms, Partitioning algorithms.
8
3 Floor Planning and Routing
Floor planning concepts, Shape functions and floor planning,
Sizing, Local routing, Area routing, Channel routing, global routing
and its algorithms.
8
4 Simulation and Logic Synthesis
Gate level and switch level modeling and simulation.
Introduction to combinational logic synthesis, ROBDD principles,
implementation, construction and manipulation, Logic synthesis.
8
5 High-Level Synthesis
Hardware model for high level synthesis, internal representation of
input algorithms, Allocation, assignment and scheduling,
Scheduling algorithms. Aspects of assignment.
8
Total 42
11. Suggested Books:
VLSI Physical Design Automation
0 1 3
VDM 226
0
0 100 30 0 20
3
4
Spring
Major Elective
44
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. S. H. Gerez, Algorithms for VLSI Design Automation, John
Wiley.
1998
2. N. A. Sherwani, Algorithms for VLSI Physical Design
Automation, (3/e), Kluwer.
1999
Reference Books
1. M. Sait, H. Youssef, VLSI Physical Design Automation,
World scientific.
1999
2. M. Sarrafzadeh, Introduction to VLSI Physical Design,
McGraw Hill (IE).
1996
45
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Signal and System, Digital Signal Processing 9. Objective: To acquaint the students with methods and techniques for implementation
of Digital Signal Processing systems.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Unfolding
An algorithm for Unfolding, Properties of Unfolding, Critical Path,
Unfolding and Retiming, Applications of Unfolding.
8
2 Folding
Folding Transformation, Register Minimization Techniques, Lifetime
analysis, Data Allocation using forward-Backward register Allocation,
Register Minimization in Folded Architectures- Folding of Multirate
Systems. Parallel Multipliers, Interleaved Floor-plan and Bit-Plane-
Based Digital Filters, Bit-Serial Multipliers, Bit-serial Filter Design and
Implementation, Canonic Signed Digit Arithmetic, Distributed
Arithmetic.
10
3 Redundant Arithmetic
Redundant Number Representations, Carry-Free Radix-2 Addition
and Subtraction, Hybrid Radix-4 Addition, Radix-2 Hybrid Redundant
Multiplication Architectures, Data Format Conversion, Redundant to
Non redundant Converter.
8
4 Numerical Strength Reduction
Subexpression Elimination, Multiple Constant Multiplication, Sub
expression sharing in Digital Filters, Additive and Multiplicative
Number Splitting. Synchronous Pipelining and Clocking Styles, Clock
Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs,
Wave Pipelining, Constraint Space Diagram and Degree of Wave
Pipelining, Implementation of Wave-Pipelined Systems,
Asynchronous Pipelining, Signal Transition Graphs, Use of STG to
Design Interconnection Circuits, Implementation of Computational
Units.
8
5 Theoretical Background, Scaling Versus Power Consumption, Power
Analysis- Power Reduction Techniques, Power Estimation
Approaches, Simulation Based Approach.
8
VLSI Digital Signal Processing Systems
0 1 3
VDM 227
0
0 100 30 0 20
3
4
Spring
Major Elective
46
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. K.K Parhi , VLSI Digital Signal processing , John-Wiley.
1999
Reference Books
2. John G. Proakis, Dimitris G. Manolakis, Digital Signal
Processing, Prentice Hall of India.
1995
47
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite:Basic Engineering Mathematics, Signals and Systems, Digital Signal Processing 9. Objective: To understanding the process of image formation and representation and the popular techniques for enhancement, restoration, compression and analysis of images.
10. Details of the Course:-
Sl. No.
Contents Contact Hours
1 Introduction to Digital Image Processing & Applications: Image
representation and Image processing devices, Overview of image
processing systems, Image formation and Visual perception.
Sampling and Quantization: uniform and non-uniform, Visual
quantization (dithering).
8
2 Imaging Geometry: Coordinate transformation, geometric warping
for image registration.
Image Transforms: Continuous and discrete-time Fourier
Transforms in 2D and their properties, and linear convolution in 2D,
Hough transform.
Image Enhancement: Linear and non-linear stretching, Histogram-
modification techniques, Smoothing and sharpening.
10
3 Image Restoration: Algebraic approach, inverse filtering,
Geometric transformations.
Image Segmentation: Thresholding, Edge detection, Boundary
following, Region growing, Motion detection.
7
4 Morphological Image Processing: Median filtering and
Morphological filtering.
Shape Representation and Description: Chain codes, Shape
descriptors, Object Recognition and Image Understanding
9
5 Image Data Compression: Encoding process and criteria, Lossless
compression and lossy compression, Entropy and Huffman coding;
Run-length coding for bi-level images, transform coding; JPEG
image compression standard. Texture, Image Analysis, Color
representation and display, Motion Picture Analysis.
8
Total 42
Digital Image Processing
0 1 3
CSM 226
0
0 100 30 0 20
3
4
Spring
Minor Elective
48
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Rafael C. Gonzalez, Richard E. Woods, Digital Image
Processing, 3rd Edition, Prentice Hall; ISBN: 013168728X.
2007
2. Anil K. Jain, Fundamentals of digital image processing,
Englewood Cliffs, NJ : Prentice Hall.
1989
Reference Books
1. Rafael C. Gonzalez, Richard E. Woods, S. L. Eddins, Digital
Image Processing Using MATLAB, Prentice Hall.
2004
2. Al Bovik editor, Handbook of Image & Video Processing, ISBN
0-12-119790-5, Academic Press, San Diego.
2000
3. Oppenheim A, V., Schafer, R. W., Discrete Time Signal
Processing, Prentice Hall.
1999
49
GRAPHIC ERA UNIVERSITY DEHRADUN
SEMESTER-III
Elective-V
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: VLSI Technology, Digital Design Fundamentals
9. Objective: To provide thorough knowledge of the process flow involved in the Development of a SOC, verification and testing requirements of SOCs and techniques involved in implementing test benches during the various stages of the SOC development process.
10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Introduction:
Importance of System-on-Chip Testing, Basics of SOC Testing,
Basics of Memory Testing, SOC Design Examples. Digital Test
Architectures:
Scan Design, Logic Built-In Self-test, Test Compression,
Random-Access Scan Design.
Fault-Tolerant Design:
Fundamentals of Fault Tolerance, Fundamentals of Coding
Theory, Fault Tolerance Schemes
8
2 System/Network-on-Chip Test Architectures:
System-on-Chip (SOC) Testing, Network-on-Chip (NOC) Testing,
Design and Test Practice: Case Studies.
SIP Test Architectures:
Introduction, Bare Die, Functional System Test, Test of
Embedded Components.
Delay Testing:
Delay Test Application, Delay Fault Models, Delay Test
Sensitization, Delay Fault, Delay Fault Test Generation, Pseudo-
Functional Testing to Avoid Over-Testing
8
3 Low-Power Testing:
Introduction, Energy and Power Modeling, Test Power Issues,
Low-Power Scan Testing, Low-Power Built-In Self-Test, Low-
Power Test Data Compression, Low-Power RAM Testing.
8
System-On-Chip Design VDM 331
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
50
Coping with Physical Failures, Soft Errors, and Reliability
Issues:
Signal Integrity, Manufacturing Defects, Process Variations, and
Reliability, Soft Errors, Defect and Error Tolerance.
4 Design for Manufacturability and Yield:
Introduction, Yield, Components of Yield, Photolithography, DFM
and DFY, Variability, Metrics for DFX.
Design for Debug and Diagnosis:
Introduction, Logic Design for Debug and Diagnosis (DFD)
Structures, Probing Technologies, Circuit Editing, Physical DFD
Structures, Diagnosis and Debug Process.
8
5 Software-Based Self-Testing:
Introduction, Software-Based Self-Testing Paradigm, Processor
Functional Fault Self-Testing, Processor Structural Fault Self-
Testing, Processor Self-Diagnosis, Testing Global Interconnect,
Testing Nonprogrammable Cores, Instruction-Level DFT, DSP-
Based Analog/Mixed-Signal Component Testing.
Field Programmable Gate Array Testing:
Overview of FPGAs, Testing Approaches, BIST of Programmable
Resources, 12.4 Embedded Processor-Based Testing
10
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, System-On-Chip Test Architectures (Nanometer Design For Testability), Elsevier
2010
Reference Books
2. Erik Larsson, Introduction to Advanced system- on- chip test design and optimization, Springer
2005
51
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: VLSI Design and Technology, Digital VLSI Circuit Design , Basics of MOS circuits or Equivalent 9. Objective: To acquaint the students with the fundamentals of low power VLSI design, static and dynamic power analysis, advanced low power design techniques. After going through this course student will be able to design low power devices for VLSI digital circuits. 10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Introduction to Basic Fundamentals of Low Power:
Overview, Need for Low Power VLSI Digital Integrated Circuits,
Basic Principles of Low Power Design, Physics of Power
Dissipation; Technology and Device Effect on Low Power:
Transistor Sizing, Gate Oxide Thickness, Impact of Technology
Scaling, Technology & Device innovation.
10
2 Sources of Power Dissipation:
Power Estimation, Dynamic Power Dissipation: Short Circuit
Power, Switching Power, Gliching Power; Static Power
Dissipation, Probabilistic Power Analysis, Degrees of Freedom.
8
3 Logic Circuits and Advanced Techniques:
Logic circuits, Special Techniques: Architecture and Systems;
Emerging Low power Techniques, Physics of Power Dissipation in
CMOS FET Devices; Design of Low Power CMOS Circuits,
Supply Voltage Scaling Approaches; Switched Capacitance
minimization Approaches.
8
4 Leakage Power Minimization Approaches:
Synthesis in Low Power Design, Test of Low Voltages CMOS
Circuits; Variable threshold Voltage CMOS (VTCMOS) Approach,
Multi threshold Voltage CMOS (MTCMOS) approach,Power
gating Transistor Stacking, Dual- threshold Voltage (Vt)
8
Low Power VLSI Design VDM 332
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
52
Assignment Approach (DTCMOS).
5 Low Power Techniques:
Low Power Static RAM Architectures, Low Power SRAM/DRAM
Design, Low Energy Computing using Energy Recovery
Techniques, Software Design for Low Power, CAD Tools for Low
Power Synthesis.
8
Total 42
11. Suggested Books:
SL.
No.
Name of Authors/Books/Publishers Year of
Publication/Reprint
Text Books
1. Gary Yeap, Practical Low Power Digital VLSI Design,
Springer.
1998
2. Kaushik Roy and Sharat Prasad, Low Power CMOS VLSI
Circuit Design,1st E.
2000
Reference Books
1. J. B. Kuo and J. H. Lou, Low Voltage CMOS VLSI Circuits,
Wiley.
1999
2. J. M. Rabaey, A. P. Chandrakasan and B. Nikolic, Digital
Integrated Circuits: A Design Perspective, second edition,
Pearson.
2003.
53
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Basic knowedge of Microprocessor and Digital Signal Processing.
9. Objective: To acquaint the students with various architecture of Digital Signal Processors and their utilization in scientific applications. 10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Overview:
Overview of Digital Signal Processing, Advantages of DSP over
analog systems, salient features and characteristics of DSP systems,
applications of DSP systems.
8
2 Introduction to DSP Processor:
Common features of DSP processors, numeric representations in
DSP processor, data path of a DSP processor, memory structures in
DSP processors
8
3 VLIW Architecture:
special addressing modes in DSP processors, pipelining concepts,
on-chip peripherals found in DSP processors.
8
4 Architecture of TMS320C5X Processors:
Assembly Instructions- Addressing Modes- Pipelining and
Peripherals, Architecture of TMS320C3X- Instruction Set-
Addressing Modes- Data Formats- Floating Point Operation-
Pipelining and Peripherals
10
5 Introduction to Black Fin Processor:
Architecture overview-processor core-addressing modes-instruction
sets-Targeted applications, VLIW Architecture- SHARC- SIMD-
MIMD Architectures.
Application:
Adaptive filters-DSP based biometry receiver-speech processing-
position control system for hard disk drive-DSP based power meter.
8
Total 42
11. Suggested Books:
Digital Signal Processor
Architectures and Applications VDM 333
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
54
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. B.Venkatramani & M.Baskar, Digital Signal Processor, McGraw Hill
2000
2. Avatar Singh and S.Srinivasan, "Digital signal processing", Thomson books
2004
Reference Books
1. K.K Parhi, VLSI DSP Systems, John Wiley 1999
55
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Electronics Devices & Circuits or Equivalent
9. Objective: To acquaint the students with nanoscale systems,fundamentals of single electron transistors,quantum confinement of electrons and molecular techniques. 10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Quantum Mechanics
Quantum confinement of electrons in semiconductor nano
structures, Two dimensional confinement (Quantum wells), Band
gap engineering, Epitaxy, Landaeur – Buttiker formalism for
conduction in confined geometries
10
2 Introduction:
Introduction to nanoscale systems, Length energy and time
scales, Top down approach to Nano lithography, Spatial
resolution of optical, deep ultraviolet, X-ray, electron beam and ion
beam lithography, Single electron transistors, coulomb blockade
effects in ultra small metallic tunnel junctions
8
3 Transistor
Single electron transistors, coulomb blockade effects in ultra small
metallic tunnel junctions
8
4 One dimensional confinement, Quantum point contacts, quantum
dots and Bottom up approach, Introduction to quantum methods
for information processing.
8
5 Molecular Techniques
Molecular Electronics, Chemical self assembly, carbon nano
tubes, Self assembled mono layers, Electromechanical
techniques, Applications in biological and chemical detection,
Atomic scale characterization techniques, scanning tunneling
microscopy, atomic force microscopy
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Quantum Computing and Nano Technology VDM 334
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
56
Text Books
1. Beenaker and van Houten “Quantum Transport in semiconductor Nanostructurenes insolid state Physics” Ehernereich and Turnbell,Academic press.
1991
2. Edward L. Wolf, Quantum Nanoelectronics: An introduction to electronic nanotechnology and quantum computing,Wiley-VCH.
2009
Reference Books
1. Supriyo Datta ,Quantum Transport: Atom to Transistor,Cambridge university press.
2005
57
GRAPHIC ERA UNIVERSITY DEHRADUN
Elective -VI
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: VLSI design and technology
9. Objective: To provide thorough knowledge of test generation, test economics,logic testing, memory testing , system testing and fundamentals of IDDQ, DFT and ATPQ. 10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Introduction:
Role of Testing,Digital and Analog VLSI Testing, VLSI Technology
Trends Affecting Testing.
VLSI Testing Process and Test Equipment:
Types of Testing, Automatic Test Equipment, Advantest Model
T6682 ATE ,LTX Fusion ATE, Multi-Site Testing, Electrical
Parametric Testing.
Test Economics and Product Quality:
Defining Costs ,Production Benefit-Cost Analysis, Economics of
Testable Design,The Rule of Ten, yield, Test Data Analysis,
Defect Level Estimation.
Fault Molding:
Defects, Errors, and Faults,Functional Versus Structural Testing,
Levels of Fault Models,A Glossary of Fault Models, Single Stuck-
at Fault,
Logic and Fault Simulation:
Simulation for Design Verification,
Simulation for Test Evaluation,Modeling Circuits for Simulation
10
2 Testability Measures:
SCOAP Controllability and Observability, High-Level Testability
Measures.
Combinational Circuit Test Generation:
Algorithms and Representations, Redundancy Identification
(RID),Testing as a Global Problem , Definitions, Test Generation
Systems,Test Compaction,Significant Combinational ATPG
Algorithms and sequential circuit test generation.
8
Testing of VLSI Circuits VDM 335
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
58
3 Memory Test:
Memory Density and Defect Trends, Faults, Memory Test
Levels,March Test Notation ,Fault Modeling, Memory Testing.
Analog and Mixed Signal Test, Delay Test and IDDQ test.
8
4 Fundamental Techniques for Logic Testing:
DFT fundamentals, ATPQ fundamental, scan architecture and
technique.
8
5 Embedded Core Test Fundamentals:
Introduction to Embedded Core Testing,Core,Core-Based
Design,Reuse Core Deliverables,Core DFT Issues,Development
of ReUsable Core,DFT Interface Considerations - Test
Signals,Core DFT Interface Concerns - Test Access,DFT
Interface Concerns - Test Wrappers,The Registered Isolation Test
Wrapper,The Slice Isolation Test Wrapper,The Isolation Test
Wrapper - Slice Cell, The Isolation Test Wrapper - Core DFT
Interface,Core Test Mode Default Values,DFT Interface Wrapper
Concerns, DFT Interface Concerns - Test Frequency,Core DFT
Development,Core Test Economics,Chip Design with a Core,Scan
Testing the Isolated Core,Scan Testing the Non-Core Logic,User
Defined Logic Chip-Level DFT Concerns,Memory Testing with
BIST,Chip-Level DFT Integration Requirements,Embedded Test
Programs, Selecting or Receiving a Core,Embedded Core DFT
Summary.
8
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Viswani D. Agarval Michael L. Bushnell, Essentials of electronic testing for digital memory & mixed signal vlsi circuit, Kluwer Academic Publications.
1999
2. Alfred L. Crouch, Design for test for digital IC's and embedded core systems, PHI .
1999
Reference Books
1. Parag. K. Lala, Digital circuit testing and testability, Academic Press
1997
2. Ashok K. Sharma, Semiconductor memories technology, testing and reliability, Prentice-Hall of India Private Limited, New Delhi
1997
59
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: VLSI design and technology
9. Objective: To provide thorough knowledge of various fabrication steps of MEMS design, Micro Sensors and their applications. 10. Details of the Course:
Sl.
No.
Contents Contact
Hours
1 Microfabrication and Micromachining:
Integrated Circuit Processes, Bulk Micromachining , Isotropic
Etching and Anisotropic Etching, Wafer Bonding, High Aspect-Ratio
Processes (LIGA)
10
2 Physical Microsensors:
Classification of physical sensors, Integrated, Intelligent, or Smart
sensors, Sensor Principles and Examples : Thermal sensors,
Electrical Sensors, Mechanical Sensors, Chemical and Biosensors
8
3 Microactuators:
Electromagnetic and Thermal microactuation, Mechanical design of
microactuators, Microactuator examples, microvalves, micropumps,
micromotors Microactuator systems, Success Stories, Ink-Jet printer
heads, Micro-mirror TV Projector.
8
4 Surface Micromachining:
One or two sacrificial layer processes, Surface micromachining
requirements, Polysilicon surface micromachining, Other compatible
materials, Silicon Dioxide, Silicon Nitride, Piezoelectric materials,
Surface Micromachined Systems : Success Stories, Micromotors,
Gear trains, Mechanisms.
8
5 Application Areas:
All-mechanical miniature devices, 3-D electromagnetic actuators
and sensors, RF/Electronics devices, Optical/Photonic devices,
Medical devices e.g. DNA-chip, micro-arrays. MEMS for RF
Applications: Need for RF MEMS components in communications,
space and defense applications.
8
Total 42
11. Suggested Books:
Micro-Sensors and MEMS VDM 336
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
60
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Ristic L ,Sensor Technology and Devices, Artech House,
London
1994
2. Sze S.M., Semiconductor Sensors, John Wiley, New York. 1994
Reference Books
1. Gabriel M. Rebeiz, RF MEMS: Theory, Design, and
Technology, Wiley
2003
2. Marc Madou, Fundamentals of Microfabrication, CRC Press 1997
61
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Soft computing, VLSI Design
9. Objective: To acquaint the students with different Modeling style , their performance analysis, various optimization techniques and their applications in VLSI design. 10. Details of the Course:
Sl. No.
Contents Contact Hours
1 Statistical Modeling: Modeling sources of variations, Monte Carlo techniques, Process variation modeling- Pelgrom’s model, Principal component based modeling, Quad tree based modeling, Performance modeling-Response surface methodology, delay modeling, interconnect delay models
8
2 Statistical Performance, Power and Yield Analysis: Statistical timing analysis, parameter space techniques, Bayesian networks Leakage models, High level statistical analysis, Gate level statistical analysis, dynamic power, leakage power, temperature and power supply variations, High level yield estimation and gate level yield estimation
8
3 Convex Optimization: Convex sets, convex functions, geometric programming, trade-off and sensitivity analysis, Generalized geometric programming, geometric programming applied to digital circuit gate sizing, Floor planning, wire sizing, Approximation and fitting- Monomial fitting, Maxmonomial fitting, Posynomial fitting.
9
4 Genetic Algorithm Introduction, GA Technology-Steady State Algorithm-Fitness Scaling-Inversion GA for VLSI Design, Layout and Test automation- partitioning-automatic placement, routing technology, Mapping for FPGA- Automatic test generation- Partitioning algorithm Taxonomy-Multiway Partitioning Hybrid genetic-encoding-local improvement-WDFR Comparison of Cas-Standard cell placement-GASP algorithm-unified algorithm.
9
5 GA Routing Procedures and Power Estimation Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame work-test generation procedures.Power estimation-application of GA-Standard cell placement-GA for ATG-problem encoding- fitness function-GA vs Conventional algorithm.
8
Optimization Techniques in VLSI Design VDM 337
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
62
Total 42
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. Ashish Srivastava, Dennis Sylvester, David Blaauwi, Statistical Analysis and Optimization for VLSI:Timing and Power, Springer
2005
2 Kalyanmoy Dev, Optimization for Engineering Design: Algorithms and Examples, PHI Learning
2010
Reference Books
1. Pinaki Mazumder, E.Mrudnick, Genetic Algorithm for VLSI Design,Layout and test Automation, Prentice Hall
1998
63
GRAPHIC ERA UNIVERSITY DEHRADUN
Name of Department: Electronics and Communication Engineering
1. Subject Code: Course Title:
2. Contact Hours: L: T: P:
3. Examination Duration (Hrs): Theory Practical
4. Relative Weight: CWS PRS MTE ETE PRE
5. Credits:
6. Semester:
7. Subject Area:
8. Pre-requisite: Digital VLSI Design
9. Objective: To acquaint the students with fundamental of Application Specific Integrated Circuits, programmable ASIC and their interconnects. 10. Details of the Course:
Sl. No.
Contents Contact Hours
1 Introduction:
Introduction To ASICs, CMOS Logic And ASIC Library Design
Types of ASICs - Design flow - CMOS transistors CMOS Design
rules - Combinational Logic Cell – Sequential logic cell - Data path
logic cell - Transistors as Resistors - Transistor Parasitic
Capacitance- Logical effort -Library cell design - Library
architecture. Review of VHDL/Verilog: Entities and architectures.
10
2 ASIC:
Programmable Asics, Programmable ASIC Logic Cells And
Programmable ASIC I/O Cells Anti fuse - static RAM - EPROM
and EEPROM technology - PREP benchmarks -Actel ACT - Xilinx
LCA - Altera FLEX - Altera MAX DC & AC inputs and outputs -
Clock & Power inputs - Xilinx I/O blocks.
8
3 Programmable ASIC Interconnect:
Programmable ASIC Design Software and Low Level Design
Entry Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and
7000 - Altera MAX 9000 - Altera FLEX - Design systems - Logic
Synthesis - Half gate ASIC -Schematic entry - Low level design
language - PLA tools - EDIF- CFI design representation.
10
4 ASIC Construction, Floor Planning, Placement and Routing
System Partition:
FPGA partitioning - partitioning methods - floor planning -
placement - physical design flow - global routing - detailed routing
- special routing - circuit extraction - DRC.
8
5 Design using Xilinx family FPGA 6
Total 42
ASIC Design and FPGA VDM 338
0 1 3
0
100 30 0 20 0
3
4
Autumn
Major Elective
64
11. Suggested Books:
SL. No.
Name of Authors/Books/Publishers Year of Publication/Reprint
Text Books
1. M.J.S .Smith, Application - Specific Integrated Circuits , Addison –Wesley Longman Inc.
1997
2. Skahill, Kevin, VHDL for Programmable Logic, Pearson Education
1996
Reference Books
1. John F. Wakherly, Digital Design: Principles and Practices, Prentice Hall
1994