T.H.Pan C.L.Wey

Indexing terms: Technology mapping, Logic synthesis, Networks

Abstract: Technology mapping is an important logic synthesis task transforming a multi-level logic network onto a set of library gates. Its primary goal is to achieve a realisable circuit which meets design constraints. Inverter pairs are generally inserted to all internal nodes of a network to increase the flexibility of mapping the subject network onto the library gates, but introducing inverter pairs may also increase the number of unwanted inverters in the mapped network. Thus, inverter minimisation is used during or after technology mapping to reduce the unwanted inverters and to further improve the quality of the mapped network. An efficient gate reassignment algorithm GRASS is presented for inverter minimisation in post technology mapping. Minimisation is achieved by re- assigning a gate to one of its NPN-equivalent gates to reduce the number of inverters and/or to use a smaller gate. Simulation results show that GRASS achieves 5.1% area improvement and 5.6Y0 delay improvement for the recommended MCNC benchmark circuits. GRASS also achieves more than 25% inverter reduction over that in a former system.

1 Introduction

Various technology mapping algorithms have been reported [1-91. The logic optimisers MIS [2] and SIS [4] employ a tree-matching algorithm which first selects a set of patterns and identifies the matches among these patterns, and then selects a cover which meets design constraints. More specifically, given a collection of library gates, a library gate is represented by a graph and decomposed using 2-input nand gates and invert- ers. A logic network under mapping is also represented by a graph and decomposed in the same way. Fig. 16 shows a network which is decomposed into 2-input nand gates and inverters for a set of Boolean equations given in Fig. la. Using the SIS-1.2 technology mapper [4], a mapped network, as shown in Figs. 2a and b may

Q IEE, 1997 IEE Proceedings online no 19971 517 Paper first received 19th September 1996 and in final revlsed form 3rd April 1997 The authors are wth the Department of Electrrcal Engineering, Michigan State University, East Lansing, ME 48824-1226

be obtained, where the MOSIS SCMOS gate library, SCMOS-GENLIB [4], was used. It should be men- tioned that inverter pairs, as shown in Fig. 2a, are gen- erally inserted to all internal nodes to increase the flexibility of mapping the subject network library gates. However, introducing inverter pairs may also increase the number of unwanted inverters.

.

INOROER = VO VI v ~ V ~ V L , OUTORDER:v12 1, v121:vo '~12021 +'111121, I IZOZI 4 v 2 , [I1121 .IllLcsl 111201*v3 [IILOI. [12OLl=!vL, [11L01=~1120L1+~v1. 111 201 =I I1202 1 + ' vo.

a

VL V I

v2 vo

1

b Fig. 1 a Boolean equation for target network b Decomposed network

SIS Technology Mupping example

a

V4

b Fig.2 SIS Technology Mapping example Mapped networks

Inverter minimisation can be carried out during or after technology mapping. The SIS logic optimiser pro- vides two options for inverter minimisation: Quzck-

348

Phase and GoodPhase. QuickPhase is based on computing inverter savings for each gate and selecting the gate with the maximum inverter savings for replace- ment by its dual gate. However, it may terminate after finding a local minimum. GoodPhase uses a partial hill climbing scheme and obtains better results but at the expense of CPU time. An alternative method for inverter minimisation was reported in [lo], in which the library is mapped into a set of phase-constraint graphs. A logic network is processed to derive a polarity graph which states how the logic network differs from the phase-constraint graphs. The inverter minimisation problem is mapped into a problem of eliminating a minimum number of vertices from the polarity graph, so as to make the remaining graph 2-colourable [lo]. Two algorithms, GoodColor and Quickcolor, were developed for achieving inverter minimisation. Results show that the scheme provides a better inverter reduc- tion than both GoodPhase and Quickphase. However, the algorithms only apply to andlor and andlorinandl nor gate libraries.

Arealdelay reduction can be achieved by eliminating the unwanted inverters which result from the technol- ogy mapping process. However, blindly minimising the number of inverters may result in greater area and a longer delay. For example, if some inverters associated with a non-inverting gate can be eliminated and the non-inverting gate can be substituted by an inverting gate, then eliminating the inverters will definitely reduce both area and delay. On the other hand, if elim- inating some inverters will cause the use of non-invert- ing gates instead of inverting gates, the inverter minimisation may not gain any improvement in area nor delay. Therefore, inverter minimisation processes should be performed under certain design constraint(s). An efficient gate re-assignment algorithm for inverter minimisation is therefore proposed, emphasising inverter minimisation under area constraint. The devel- oped algorithm has been implemented in a C program called GRASS (Gate Re-Assignment), on a SPARC 20 workstation. Here, the gate library, scmos.genlib, in SIS is used. However, it is readily applied for any other gate libraries. For the sake of comparison, all MCNC benchmark circuits have been tested.

2 Algorithm development

A Boolean network G(V, E) is a directed acyclic graph (DAG). Associated with each node of the graph is a variable yi and a representation of a logic function J;. A directed arc from node vi to node vj is in the graph if node vi uses the variable y i explicitly in the representa- tion J; [2]. A function g ( 2 ) with 2 as input vector is said to be NI"-equivalent to XX') if g ( 2 ) can be obtained from Ax') by any combination of the follow- ing three operations 1121: (i) Negation operator N,: negation of one or more input variables of f ( 2 ) . (ii) Permutation operator P: permutation of input vari- ables. (iii) Negation operator No: negation off(?). That is, f ( 2 ) and g ( 2 ) arc in the same NPN class if operators Ni, P, and No exist such that

g ( 2 ) = N,f(PN,Z)

is a tautology.

IEE Proc.-Comput. Digit. Tech., Vol. 144, No. 5, September 1997

Let Gg and Gj be logic gates in gate library L with functions g and f , respectively. Gg and Gf are said to be NPN equivalent gates in L if g and f a r e NPN equiva- lent. For example, the NPN-equivalent gates of AND are AND, OR, NAND, and NOR in most standard cell libraries. The gate re-assignment problem is to find an NPN equivalent gate Gg for each gate Gj except inverted in a Boolean network such that the mapped network has minimum area and its function is equiva- lent to that of the original circuit. Therefore, the circuit structure will be maintained except for the inclusion of inverters.

Double-phase logic network is a logic network with a label on each edge. Let e = (vi, vj) be an edge from ver- tex vi to vi. A label denoted A(e) E { 1, 0} is associated with edge e. Let the function of vj be,f(x,, ..., xn). Let vi connect to the kth input of vj. If A(vi, vj) = 1, vi = f( ..., vir ...). If A(v , vj) = 0, vi = f ( ..., vi), ...). That is, if A(e) = 0, edge e implies an inverting operation. Edge e with A = 1 is called a positive edge, and il = 0 is known as a negative edge. Since negative edges can represent the inverters in the double-phase logic network, the invert- ers in the network are removed by changing the labels of the edges without changing the logic function of the network. The reduced network is known as a reduced double-phase logic network. Consider the example cir- cuit in Figs. 3a [lo]. Fig. 36 shows the reduced double- phase logic network of the circuit; the boldfaced lines represent the negative edges while the non-boldface lines represent the positive edges.

Q 1 '12

Q3 a4

'11 '12

a3 Q4

a

b Fig. 3 Example circuit U Original double-phase logic network circuit [lo] b Reduced double-phase logic network

2. I Gate re-assignment The basic concept behind this development is to re- assign a node with one of its NPN equivalent gates so that we can either reduce the numbers of inverters used in its fan-in and fan-out edges, or use a smaller NPN- equivalent gate by moving the inverters to different locations. In other words, area reduction can be made either by inverter minimisation, or the use of smaller NPN-equivalent gate. These two sources of area reduc- tion may sometimes contradict each other. Reducing an inverter may force the use of larger NPN-equivalent gates. On the other hand, using a smaller NPN-equiva- lent gate may require extra inverter(s). Therefore, the purpose of this study is to develop a gate re-assignment algorithm which minimises the number of inverters

349

while keeping the overall area minimum. Since invert- ers are represented by negative edges in the reduced double-phase logic network, the inverter minimisation problem is equivalent to minimising the number of neg- ative edges. The gate re-assignment algorithm GRASS uses two approaches to minimise the overall area. The first approach, TreeGRASS, considers the relationship among the gates and tries to re-assign each gate based on the global view. The second approach, Quick- GRASS, only considers the local information of each gate.

2.1. I TreeGRASS: TreeGRASS uses a dynamic pro- gramming method as in DAGON [SI. The tree covering algorithm [SI can be used if the cost of a match at a gate can be determined by examining the cost of the match and the cost of the inputs to the match. For gate re-assignment problems, each gate in the reduced dou- ble-phase network has a set of equivalent gates which correspond to matches in the tree covering algorithm. However, in gate re-assignment problems, the cost of an equivalent gate depends not only on the transitive fan-in of the gate, but also on area cost implied by the polarity of fan-out edge. Since the polarity of the fan- out edge cannot be given in advance, both possibilities must be kept track of. Two traversals, postorder traversal and preorder traversal, are needed, where the postorder traversal is used to determine the best gates for both positive and negative fan-out phases, while the preorder traversal determines the specific gates by choosing the best output phase. For simplicity, the net- work is assumed to be a tree. The alternative case is discussed shortly.

The routine PostorderTraversal begins with the pri- mary inputs of the tree, and traverses to the primary outputs. For each node, the accumulated area (Acc[G,,, fanout jhase]) for each NPN-equivalent gate of the node and for both positive and negative fan-out phases is computed. The accumulated area includes the small- est total area of the transitive fan-in nodes including the implied inverters, the area of the equivalent gate, and the possible inverter at the fan-out. The equivalent gate (BestGate[v, phase]) with the smallest area (BestAr- ea[v, phase]) is then selected. After the first traversal, the best equivalent gates for both positive and negative phases are recorded. Routine PreorderTraversal deter- mines the best phase for each node based on the fan- out phase in the tree case, and the areas for both phases, starting from the primary outputs.

In the event that circuits are not trees, the accumu- lated area of the nodes with multiple fan-outs is divided by the fan-out count of that node. For exam- ple, consider the circuit network in Fig. 4a. For the A N D gate g l , it has BestGate[gl, 11 = and for a positive fan-out edge, and BestGate[gl, 01 = nand for a negative fan-out edge. Note that the unit values of two-input AND and N A N D gates in scmos.genlib are 34 and 26, respectively. (The unit value for the standard cell library in scmos.genlib indicates the height of the cell.) Since g l has a fan-out of 3, BestArea[gl, 13 = 3413, or 11.33, and BestArea[gl, 01 = 2613, or 8.67. As shown in Fig. 4a, (BesGate(v, O), BestArea(v, 0); BestGate(v, l ) , BestArea(v, 1 ) ) = (nand, 8.67; and, 11.33) is assigned to g l . Similarly, (nand, 8.67; and, 11.33) is also assigned to g2. For 83, it has BestGate[g3, 01 = nand and Best- gatek3, 11 = nor. When g3 has a positive fan-out edge, BestGute[g3, 11 = nou can be chosen if g3 has all nega-

350

tive fan-in edges. On the other hand, when g3 has a negative fan-out edge and two positive fan-in edges, BestGate[g3, 01 = nand will be selected. As a result, Best Area[g3, 01 = BestArea[gl, 11 + BestAuea[g2, 11 + 26 = 48.67, and BestArea[g3, 11 = 43.34. Thus, (nand, 48.67; nor, 43.34) is assigned to 83. The values of the remain- ing nodes are assigned in a similar way. The values of BestArea are accumulated for assigning to the fan-out gates.

(nand, C8.67; (nand,8.67; nor. C3.3C)

"1 0 2

nor, b.7 1

a

1 1

b Fig. 4 a With assigned BestArea and BestGate b Resultant double edge network

Minimisation procedure in TreeGRASS

In the PreorderTraversal routine, starting from the primary output a l l , the gate re-assignment of g7 is determined. Even though BestArea[g7, 01 = 187.33 < 192.67 = BestAreatg7, 11, choosing the negative edge requires the use of an extra inverter to keep the circuit functionality. Since BestArea[g7, 01 + inverter = 187.33 + 18 = 205.33 > 192.67 = BestArea[g7, 11, the positive edge is chosen i.e. g7 = nor. Once g7 is chosen, it requires two negative fan-in edges. This forces us to choose BestGatek6, 01 = nand, and BestGate[gS, 01 = nor. Further, BestGate[g3, 01 = nand and BestGate[g4, 01 = nand are chosen. Consider the BestGate for g l , choosing g3 = nand and g4 = nand requires positive edges from both gl and g2, while selecting g5 = nor requires negative edges from both gl and 82. As a result, assigning BestGate[gl, 11 = and and BestGatek2, 01 = nand provides the least area and number of nega- tive edges, as shown in Fig. 4b, where only one inverter is required, as illustrated in Fig. S.

Fig.5

"1 a 2

a3 '14

Minimisation procedure in TreeGruss a Final network

Fig. 6a shows the resultant network generated by Goodcolor. Fig. 66 summarises the area and timing results for the original circuit, the result from Good- Color, and the result from TveeGRASS. In this instance, Goodphase has the same result as Goodcolor.

IEE Proc -Comput Diglt Tech, Vol 144, No 5, September 1997

However, GRASS reduces the overall area and improves the timing performance significantly, by transforming some of the gates into inverting gates. Note that inverting gates usually have a smaller area and delay than their non-inverting gates. The improve- ment over the original circuit is about 25% in both area and delay. The complexity of TreeGRASS is linear in terms of the number of edges

Area

Delay

O3 04

Original Good Color GRASS G I 0 ratio

281 2 ~ a 208 0.73

5.27 5.17 3.97 0.75

y/ a

b

Fig. 6 Resultant mapped network by GoodColar

2.1.2 QuickGRASS: A heuristic algorithm called AreaSaved, based on a local search that calculates the variations in area due to the NPN operations on a node, can be calculated by inspecting the local connec- tions of the node and the gate which implements the node. The algorithm is similar to the approach pro- posed by [IO]. However, the number of operations that can be applied to a node is extended and the probabil- ity of achieving better results is increased.

When converting a gate to its NPN equivalent, the fan-in and fan-out edge polarities of the gate need to be changed in order to maintain the same circuit func- tionality. Therefore, in addition to the area change due to gate re-assignment, the area change resulting from the change in the number of inverters also needs to be considered. Routine AreaSaved computes the area change when a gate is converted to its equivalent gate. This area change includes the area difference between the gate and its equivalent gate and the area changes due to the addition or removal of the inverters on fan- in and fan-out of the gate, to maintain the circuit func- tion. FanoutInvertersSaved [lo] calculates the change in the number of inverters needed if the negation operator No is applied to the gate (i.e. the output of the gate is inverted). FaninInvertersSaved computes the change in the number of inverters if the negation operator N, is applied to an input of the gate. The procedure used(x, F, determines whether x is used in E;. Used(x, &+) means that there is a positive edge from x to F and used(x', F, indicates a negative edge from x to F.

3 Experimental results

These procedures have been implemented in a C pro- gram called GRASS on a SPARC 20 workstation. The 74 MCNC benchmark circuits have been tested. For comparison, the simulation results of the 13 circuits suggested in [4, 1 I] are listed in Table 1. Each circuit is first optimised using the script file scriptmgged and then mapped using the technology mapper in SIS-1.2. The area and delay figures for the resultant network

IEE Proc -Comput Digit Tech, Vol 144, No. 5, September 1997

are listed in the second column of Table la. The SIS- resultant networks are then processed by Goodphase and GRASS, respectively. Results show that GRASS has 5.5% improvement over SIS-1.2 compared to an area improvement of 1.9% by Goodphase. Table 16 lists the averages of the areas and delays of the 74 circuits. Results indicate that GRASS has a 3.3% improvement in area, while GoodPhase has 1.3%. GRASS has 3.9% delay improvement, and Goodphase has almost none.

Table 1: Experimental results: area and delay

(a) for 13 suggested MCNC benchmark circuits

Circuit

b9

C432

rot

C1355

C1908

C2670

dalu

C3540

t481

k2

C6288 C7552

des

Average (ratio)

SIS area

2318

3380 11849

7328

8305

11383

12919

21294

644

19390

561 52

36201

54993

18935 (100%)

delay

13

50 33

26

41

33

36

63

5

29

173

73

130

54 (100%)

GoodPhase GRASS area delay area delay

2318 13 2264 12

3130 51 3344 47 11813 35 11415 30

7328 26 7164 22

8287 41 8266 41

11239 33 11127 32

12487 37 11820 34

21204 63 20781 57

644 5 644 5

19354 29 18666 25

53092 172 49652 179

36129 73 35850 67

54435 72 52072 110

18590 49 17911 51 (98.1%) (90.7%) (94.5%) (94.4%)

~~ ~

(b) for all 74 MCNC benchmark circuits

Average 7390 26 7291 26 7145 25 (ratio) (100%) (100%) (98.7%) (100%) (96.7%) (96.1%)

Table 2: Experimental results: gate and inverter counts ~~~~~~~~~~~ ~

(a) for 13 suggested MCNC benchmark circuits

SIS Circuit

area

b9 80

C432 113

rot 393

C1355 193

C1908 255

C2670 342 dalu 420

C3540 655

t48 1 23

k2 596

C6288 1887

C7552 1099

des 1679

Average 595

Good Phase GRASS delay area delay area delay

21 80 21 78

29 111

104 39 1

19 193

39 254

70 334

119 396

114 650

8 23

97 594

463 1717

218 1095

394 1648

130 575

27 101

102 382

19 194

38 270

62 334

95 357

109 653

8 23

95 638

293 1534

214 1102

363 1635

111 561

19

17

93

20

54

62 56

112

8

139

110

221

350

97 (ratio)- (100%) (100%) (96.6%) (85.3%) (94.2%) (74.6%)

(b) for all 74 MCNC benchmark circuits

Average 232 54 227 49 219 41 (ratio) (100%) (100%) (97.8%) (90.7%) (94.3%) (75.9%)

Table 2a lists the gate and inverter counts for the selected 13 circuits, and their averages, where GRASS achieves a 5.8% improvement in gate count and an

351

25.4% improvement in inverter count, compared to GoodPlzase improvements of 3.3% and 14.7%, respec- tively. There are four circuits, C1355, C1908, k2, and C7552, that have more inverters in GRASS than in SIS. As mentioned, GRASS minimises the inverter count under area constraint. GRASS-resultant net- works for these four circuits have a much smaller area than those in SIS-resultant networks. For circuit C6288, the GRASS-resultant network achieves an 11.6% improvement in area, an 18.7% improvement in gate count, and a 76.2% improvement in inverter count. Even with the 74 circuits, as summarised in Table 2b, GRASS also achieves 5.7 and 14.1% improvements, while GoodPhase has improvements of only 2.2% and 9.3%. GRASS takes 1.84s of CPU time for C6288, 7.48s for des, and less than 1s for most of the remainder.

A routine called GoodGRASS has also been imple- mented, and uses a Kernighan-Lin style hill-climbing scheme to escape the local minimum. However, little improvement over the existing scheme was found.

4 Conclusions

Inverter and area minimisations for post technology mapping are achieved by re-assigning a gate to its NPN equivalent to reduce the number of inverters and/or to use a smaller NPN equivalent gate. Simulation results have shown that the proposed algorithm, GRASS, achieves a 5.1% area improvement and a 5.6% delay improvement, for the recommended MCNC bench- mark circuits. GRASS achieves more than a 25% inverter reduction over that in SIS-1.2. In this imple- mentation, the emphasis was placed on the inverter and area minimisations, where the delay improvement is its

by-product. The algorithm is currently being modified so that it can handle the inverter and area minimisation under a delay constraint.

5

1

2

3

4

5

6

7

8

9

References

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352 IEE Proc -Compul. Digit Tech , Vol. 144, No. 5, September 1997