December 2007 Visit us at www.e-GRID.net Page 1 GRID.pdf Visit us at e-GRID.net December 2007 CHAPTER MEETINGS SF-IAS - 11/27 | Digital Paralleling & System Design - load sharing, synchronization, genset protection issues, system topologies ... [more] SF-PES - 11/27 | Solar Energy Technologies: Emphasis on Concentrating Photovoltaic Technologies - overview and deployment of optical systems that concentrate sunlight ... [more] SCV-PSES - 11/27 | Switch Safety - It's a Snap! (Or is it?) - making sure they can do it safely ... [more] OEB-PES - 11/29 | Selection and Applications Of Power Factor Correction Equipment for Industrial/Commercial Facilities ... [more] SCV-CE - 12/4 | "TV 2.0" - Digital TV in the Networked Home - commercial and behavioral challenges ... [more] SCV-LEOS - 12/4 | Mondo Magnets! Attractive (and Repulsive!) Devices and Demonstrations - holiday event for the family ... [more] SCV-SPS - 12/10 | Re-Live the Movie "The Matrix": From Harry Nyquist to Image-Based Rendering - multiview imaging for informative visualization ... [more] SCV-CNSV - 12/11 | Wireless Standards: A History and Perspective / CNSV Annual Meeting - the 802.11 standards family and issues ... [more] SF-PES - 12/13 | Electrical Out-of-Step Protection - loss of synchronism during stressed power system conditions ... [more] SCV-MTT - 12/13 | PLL Design Essentials for Wireless Systems - modeling and quantifying expected performance ... [more] SCV-LEOS - 12/13 | Nanowires and Nanolasers: How Small can a Laser be? - smaller than the wavelength in all 3 dimensions ... [more] SCV-Nano - 12/18 | Small Stuff in Search of the Big Bucks: Nanotechnology Commercialization by Sector - shifting from research labs to markets ... [more] SCV-Ed - 12/19 | Educating Engineers in Advanced Silicon Processes - aggressive process scaling create challenges ... [more] SCV-CPMT - 1/16 | Flexible/Printable Electronics / Organic LED (OLED) Display Technology - next-generation light, power and circuitry products ... [more] SCV-CAS - 1/21 | Variation Robustness for Analog/Mixed-Signal, Custom Digital, and Memory Design - addressing systematic and random sources of variation; time for a new approach ... [more] SCV-Mag - 1/29 | The Spin on Electronics! - generating, manipulating and detecting spin-valves and magnetic tunneling junctions ... [more] SCV-Mag - 2/12 | Patterned Nanomagnetic Bits and Devices - approaches for enabling higher areal recording density ... [more] Support our advertisers MARKETPLACE – Services page 3 Associate/Assistant Professor positions page 6 Professional Skills Courses [more] - Transitioning from Individual Contributor to Mgr - Interviewing and Hiring the Best Talent - Breakthrough Project Management - Mastering Your Presentation Skills Technical Skills Courses/Seminars [more] - MATLAB & Simulink for Design & Digital Signal Processing - Design of Radio Frequency Integrated Circuits - Analog CMOS Integrated Circuit Design - Statistical Process Control (SPC) - Practical Considerations for Low Power Design Implementation in CMOS - Design-for-Yield & Design-for-Manufact-uring (DFY/DFM) Workshops and Seminars Vibro-Acoustics Simulation Seminar - Dec 13 - Santa Clara Marriott [more]
Transcript
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1
GRID.pdf
Vis i t us at e-GRID.netDecember 2007
CHAPTER MEETINGS
SF-IAS - 11/27 | Digital Paralleling & System Design - load sharing, synchronization, genset protection issues, system topologies ... [more]
SF-PES - 11/27 | Solar Energy Technologies: Emphasis on Concentrating Photovoltaic Technologies - overview and deployment of optical systems that concentrate sunlight ... [more]
SCV-PSES - 11/27 | Switch Safety - It's a Snap! (Or is it?) - making sure they can do it safely ... [more]
OEB-PES - 11/29 | Selection and Applications Of Power Factor Correction Equipment for Industrial/Commercial Facilities ... [more]
SCV-CE - 12/4 | "TV 2.0" - Digital TV in the Networked Home - commercial and behavioral challenges ... [more]
SCV-LEOS - 12/4 | Mondo Magnets! Attractive (and Repulsive!) Devices and Demonstrations - holiday event for the family ... [more]
SCV-SPS - 12/10 | Re-Live the Movie "The Matrix": From Harry Nyquist to Image-Based Rendering - multiview imaging for informative visualization ... [more]
SCV-CNSV - 12/11 | Wireless Standards: A History and Perspective / CNSV Annual Meeting - the 802.11 standards family and issues ... [more]
SF-PES - 12/13 | Electrical Out-of-Step Protection - loss of synchronism during stressed power system conditions ... [more]
SCV-MTT - 12/13 | PLL Design Essentials for Wireless Systems - modeling and quantifying expected performance ... [more]
SCV-LEOS - 12/13 | Nanowires and Nanolasers: How Small can a Laser be? - smaller than the wavelength in all 3 dimensions ... [more]
SCV-Nano - 12/18 | Small Stuff in Search of the Big Bucks: Nanotechnology Commercialization by Sector - shifting from research labs to markets ... [more]
SCV-Ed - 12/19 | Educating Engineers in Advanced Silicon Processes - aggressive process scaling create challenges ... [more]
SCV-CPMT - 1/16 | Flexible/Printable Electronics / Organic LED (OLED) Display Technology - next-generation light, power and circuitry products ... [more]
SCV-CAS - 1/21 | Variation Robustness for Analog/Mixed-Signal, Custom Digital, and Memory Design - addressing systematic and random sources of variation; time for a new approach ... [more]
SCV-Mag - 1/29 | The Spin on Electronics! - generating, manipulating and detecting spin-valves and magnetic tunneling junctions ... [more]
SCV-Mag - 2/12 | Patterned Nanomagnetic Bits and Devices - approaches for enabling higher areal recording density ... [more]
Support our advertisers
MARKETPLACE – Services page 3 Associate/Assistant Professor positions page 6
Professional Skills Courses [more]- Transitioning from Individual Contributor to Mgr - Interviewing and Hiring the Best Talent - Breakthrough Project Management - Mastering Your Presentation Skills
Technical Skills Courses/Seminars [more]- MATLAB & Simulink for Design &
Digital Signal Processing - Design of Radio Frequency Integrated Circuits - Analog CMOS Integrated Circuit Design - Statistical Process Control (SPC) - Practical Considerations for Low Power Design
Implementation in CMOS - Design-for-Yield & Design-for-Manufact-uring
(DFY/DFM)
Workshops and Seminars Vibro-Acoustics Simulation Seminar - Dec 13 - Santa Clara Marriott [more]
IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition
residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.
Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net
From the editor . . . It’s amazing how much computer performance can
be bought at the “modest end” of the curve, for those willing to do some assembly!
I certainly wasn’t going to get up at 4 AM to shop the “Black Friday” sales, but I wasn’t above heading to Frys later in the day. I was shopping for the “pieces” for a new, moderate-speed PC. Here’s what I ended up getting (mind you, lots of items are at ridiculously low prices on that day!)
Motherboard with PCI-E, SATA, DDR2 $26 AMD dual-core processor, 1.9 GHz/45W $33 2 GBytes of DDR2 800MHz DRAM $20 256MB Video board, PCI-E16 $30 18X 2-layer DVD/CD writer $30 300 GByte SATA Drive $50 PC case with power supply $25
This entailed only two rebates (for $70). So, for $214 (plus tax) I have a complete editing and work computer. Fantastic!
As I look over this assortment of goodies (before starting actual assembly), I find that the processor (in a 65nm process) comes from a fab in Dresden, Germany. The motherboard is from Taiwan, while the video card, both drives, the power supply and the case are from China. Much of the design, however, is from Silicon Valley.
And with this low-power processor (under 45 watts, with their “3800+” speed range), this system should run quite cool and quiet; with its power-reduction system, it is supposed to cut back to a 1 GHz clock when quiescent. Reports on this chip indicate that I can overclock it by 25%, if I need to. In regular use, I’ll plan to use only the single exhaust fan in the power supply for air flow. It’s part of the “greening” of electronics.
Paul Wesling, editor
NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net
DIRECTORS
Santa Clara Valley Fred Jones
Tom Coughlin
Oakland East Bay Bill DeHope
Victor Stepanians
San Francisco Sandra Ellis Dan Sparks
OFFICERS Chair: Tom Coughlin
Secretary: Bill DeHope Treasurer: Dan Sparks
IEEE-SFBAC PO Box 2110
Cupertino, CA 95015-2110
IEEE GRID
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 3
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
IEEE-CNSV Consultants' Network
of Silicon Valley
Become a member Find a Consultant Submit a Project
CaliforniaConsultants.org
M E S OIn t eg r at io n
Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 4
Based on AutoSEA2, the industry standard for mid and high frequency noise and vibration analysis, VA One offers a unique and unprecedented combination of all standard vibro-acoustics simulation methods: Statistical Energy Analysis (SEA), Finite Element Analysis (FEA) and the Boundary Element Method (BEM).
Who Should Attend? • Current AutoSEA2 and SEA users and managers, • Current BEM users and managers, • Current FE acoustic software users and managers, • Vibration, acoustics and dynamics engineers, • Structural Analysts, • CAE professionals
Applications • Vibro-acoustics • Dynamic Environ-ments • Random Vibration Analysis • Structure-borne Vibration • Pre-test Simulation • Mid-Frequency Analysis Co-Sponsor: Santa Clara Valley Section, IEEE
MATLAB & Simulink for Design & Digital Signal Processing 12 week course, M/W 6:00PM-9:00PM (Starts Jan 7) Hands-on, from basic concepts in discrete time systems, filter design and implementation all the way to advanced concepts of multi-rate systems; balanced mix of theory and practice.
Design of Radio Frequency Integrated Circuits 12 week course, T/TH 6:00PM-9:00PM (Starts: Feb 5) A balance of communications, physics and IC design. Includes high-speed amplifiers, LNA, Mixer, VCO, PA, PLL and other RF blocks.
Analog CMOS Integrated Circuit Design 12 week course, M/W 6:00PM-9:00PM (Starts Feb 11) A detailed review of the principles, concepts, and design methods used for current state-of-the-art analog circuits; common analog building blocks; more complex analog circuits. HSPICE simulations are used extensively to augment the text/lecture material.
IEEE Members save $40 on courses.
Thursday, December 13
10:00 AM - 2:30 PM
Santa Clara Marriott
No cost – lunch will be provided
9:30AM: Registration Opens 10:00AM: VA One: Introduction & Overview 10:30AM: Low Frequency Deterministic Methods 11:15AM: SEA 12:00PM: Lunch 1:00PM: Hybrid Methods (FE/BEM/SEA) 2:30PM: Close
Discover why, with these latest developments, VA One is the ONE tool you need for full spectrum vibro-acoustic simulation. Please join us for this FREE seminar and automatically enter to win an Apple iPod nano!
Access is limited, and pre-registration is highly recommended. Visit: www.esi-group.com (select “Events”)
Download the Seminar flyer to register by FAX:
www.e-grid.net/docs/0712-esi.pdf Upcoming 1- and 2-day Seminars:
Dec 6: Statistical Process Control (SPC) - Principles and Applications
Jan 24: Practical Considerations for Low Power Design Implementation in CMOS
Jan 25: Design-for-Yield & Design-for-Manufact-uring (DFY/DFM) - Principles and Challenges
Feb 21-22: Advance Semiconductor Technology & Fabrication
Discount of $30 for IEEE Members on Seminars. Get more information:
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 6
UNIVERSITY OF CALIFORNIA, SANTA CRUZ COMPUTER ENGINEERING
Associate/Full Professor
The Computer Engineering Department, UC Santa Cruz, invites applications for a faculty position:
Position #808: The Computer Engineering Department invites applications for a tenured (Associate or Full Professor) position in Autonomous Systems. Potential areas of specialization include robotics, control, mechatronics, and assistive technology. The department is launching an initiative in autonomous systems and mechatronic engineering, and seeks an individual to join our core faculty in this area and lead the development of new research and degree programs.
MINIMUM QUALIFICATIONS: Ph.D. in Computer Engineering, Mechanical Engineering, Electrical Engineering, or related field; demonstrated excellence in innovative research; a strong record of publications; proven distinction in university teaching at the graduate and undergraduate levels; and a proven track record for securing extramural funding.
MORE DETAILS: www.soe.ucsc.edu/jobs, Position #808. To ensure full consideration, applications must arrive by Jan. 1, 2008. EEO/AA/IRCA Employer.
Submit: CV, statement of research and teaching plans, URLs of selected reprints, and names of three people who are willing to write letters of recommendation, by Jan. 1, 2008. We prefer electronic applications: www.soe.ucsc.edu/jobs/faculty/apply. Alternatively, applications may be mailed to: Computer Engineering Search Committee, University of California, 1156 High Street MS: SOE3, Santa Cruz, California 95064.
Clearly indicate position: #808 (Associate/Full Professor, Assistive Technology). UCSC is the UC campus nearest to Silicon Valley and has close research ties with the local industry. For
further details about the Baskin School of Engineering at UCSC, see www.soe.ucsc.edu
San José State University Faculty Positions in Electrical Engineering
Analog Circuits, Biomed, Power/Energy Systems
San José State University invites applications for tenure track assistant professor positions with specialization in Analog Circuits (JOID: 013180), Biomedical Electronics and Systems (JOID: 013181), or Power/Energy Systems (JOID: 013181). Applicants must hold a PhD or equivalent degree in Electrical Engineering with research emphasis in their specialization areas. The selected candidates will teachundergraduate and graduate Electrical Engineering courses, conducting research and develop courses and labsin their areas of expertise. The positions will be available from August 2008. Employment is contingent upon proof of eligibility to work in the United States. For detailed information see
fa.sjsu.edu/employment/employment.htm
For consideration, send a letter of application (referring JOID number), curriculum vitae, statement of teaching interests/philosophy, research plans, and contact information for at least three references by January 15, 2008 to: Dr. Avtar Singh, Chair
Electrical Engineering Department San José State University One Washington Square San José, CA 95192-0084
SJSU is an Equal Opportunity/Affirmative Action Employer committed to nondiscrimination on the bases of race, color, religion, national origin, sex, sexual orientation, gender status, marital status, pregnancy, age, disability, or covered veteran status consistent with applicable federal and state laws.
Member of the IEEE Power Engineering Society. His 25 years experience in various phases of the power industry includes acting as a trainer for paralleling systems at ASCO Emerson Network Power, and at the Engine Generators Systems Association (EGSA). He also has 13 years at Emerson Network Power / ASCO through various jobs as an application engineer, project manager, marketing manager. He spent 2 Years with GE Zenith as Western Regional Sales Manager. He started with Cummins Power Generation April, 2004 as Western Regional Sales Manager for Power Electronics. George has a BA in Management from St. Mary’s College in Moraga California, 1999, an Associate Of Business North Arkansas Community College, 1979, On-the-Job Training Electrical Power Training AP&L, Alltel, ASCO, and Cummins Power Generation.
Our speaker will review paralleling basics for
gensets, such as, but not limited to, load sharing, synchronization, and genset protection issues. He will then compare the conventional hardware requirements for paralleling with digital control alternatives that include discussion of master control functions. Finally, our speaker will conclude his presentation by describing various system topologies and design considerations, more notably with respect to switchgear vs. switchboards.
Please join us in welcoming our speaker to San Francisco for what is sure to be an interesting and productive session.
Kevin Fine, Director of Product Development at GreenVolts, spent six years in engineering, marketing, and project management at Agilent Technologies. Kevin leads a growing team of engineers and brings particular strengths in the areas of product design and development of opto-mechanical systems. He has an MS and BS in Mechanical Engineering from Stanford.
GreenVolts is an early-stage solar startup developing concentrated photovoltaic technology for the utility market. Its unique technology will deliver clean, reliable energy to utility companies on a massive scale – so that they can provide green energy to the public economically and with only a flick of the switch. The Green Volts system will allow everyone to enjoy green energy directly from their regional power grid. Current projects include a 2 MW high concentration PV system being deployed for PG&E.
It’s an exciting time for solar energy. A confluence of events – technological developments, financing opportunities, political and consumer openness, climate concerns, and the rise in price of other fuel sources – makes solar energy particularly attractive at this time.
This presentation will offer an overview of the various types of solar technology in development today and where they play in the market. There will be a special focus on the discussion of concentrating photovoltaics (the use of an optical system to concentrate light from an aperture onto a smaller solar cell), as this technology can be particularly well suited to utility scale deployment. The talk will conclude with an overview of the GreenVolts system and a discussion of LCOE – the Levelized Cost of Energy – as it relates to the system design of high concentration photovoltaic systems.
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 9
Switch Safety - It's a Snap! (Or is it?) - and
election of 2008 officers Speaker: Ian McDonald, Underwriters Laboratories Time: Dinner at 5:45 PM; Presentation at 7:00 PM Cost: none for presentation Place: Optional dinner at El Torito Mexican
Restaurant, 2950 Lakeside Drive, Santa Clara; Presentation at Applied Materials, Bowers Cafe, 3090 Bowers Ave, Santa Clara
RSVP: not required Web: www.ewh.ieee.org/r6/scv/pses
Ian McDonald has spent the last 10 years at Underwriters Laboratories working with the industrial group. For the last 4 years he has been the Principal Engineer for Switches and Appliance Controls, recently designing new lab test equipment.
He serves as the North American technical representative to the IEC working committee 23j for 61058-1 (Standard for Appliance Switches) and a member of the ASTM F01.18 working group for membrane switches. Most recently he has been involved in the harmonization efforts between the legacy North American switch standards and IEC 61058-1 standard.
Before completing his BSEE at CSU Fresno, Ian had a 1 1/2 year stint at NASA's Thermal lab at Dryden Flight Research Center. So... perhaps switch safety is rocket science!?
One of the most basic electrical components is the switch. All it has to do is open and close, right? What could be so difficult or interesting about that? When you realize that everything from computers to circuit breakers depends on opening and closing switches, you may reconsider!
November's presentation is back to the basics: what switches really have to do and how we make sure they can do it safely. The speaker will consider various types of switches, when and where they should be used, applicable standards and tests, and also touch on some of the issues that can arise if switches are not given the serious consideration they deserve.
Come and find out about what turns on almost every piece of electrical equipment in the world. It might turn you on, too!
Special Notice: Chapter Officers--
nominations and elections Officer positions for 2008 will have nominations
accepted at the November meeting, followed by a vote by PSES member attendees. If you wish to stand for office but cannot attend the November meeting, please send your name, the position sought and a brief election statement to the chapter chair.
from the University of Calcutta, India and M.E.E degree from the University of South Carolina, Columbia, SC. Presently, he is working as Power Quality Product & Application Engineer in PQ Solution Group of Square D Company, San Francisco Field Office. Prior to that, he worked for 17 years, as a Power Conditioning & Advanced Motor-Drives Manager, in the Power Quality Business Group of Electric Power Research Institute (EPRI), Palo Alto, where he was responsible for technology and application development for power quality mitigation hardware system, advanced energy storage for power quality solutions, and advanced motors and drives system for end-user sectors. Prior to joining EPRI, he was Order Engineering Manager for Square D Company, Columbia, SC. In this position, he was responsible for the design and applications of products such as LV and MV MCCs, motor controllers for material handling, & VFDs. He has participated in NEMA Standards Subcommittees, organized EPRI-sponsored National motors & Drives Steering Committee, and is author/ co-author of several IEEE technical papers. His R& D work at EPRI has generated more than thirty patents for EPRI and about eighty EPRI technical reports.
The vast majority of the total load connected to today’s industrial and commercial distribution systems is inductive in nature and generally has a poor operating power factor. If properly selected and installed, Power Factor Correction Equipment including Capacitors (PFCCs) provides an economical and practical means for improving the system power factor.
PFCCs reduce energy costs, increase electric system capacity, and raise voltage levels intentionally, and can reduce power distribution system losses.
This presentation will focus on the applications of shunt capacitor and will cover topics such as power factor fundamentals including displacement and total power factors, selection and sizing of power factor correction capacitor, cost benefits and utility rate structures. It will also discuss other related application issues like proper location of capacitor in the facility distribution system, effects of harmonics, fixed vs. automatic banks, selection of circuit protection and isolation devices, applicable standards and codes, various considerations for capacitor banks connected at MCC or at motor terminals, PF impact by distributed generation, PF correction benefits using harmonic filters, and certain aspects of storage, maintenance, and installation of the power factor correction equipment.
Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 11
"TV 2.0" - Digital TV in the Networked Home
Speaker: Paolo Siccardo, President, Digital Keystone Time: Refreshments at 6:30 PM; Presentation at
7:00 PM Cost: $5 for IEEE members, and $10 for non-
members Place: Hewlett Packard Oak Room, 19447
Pruneridge Avenue (Building 48), Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/ce
Paolo Siccardo is the President and Chief Executive Officer of Digital Keystone, a world leader in digital entertainment solutions that bridge the personal computer, consumer electronics and content industries. Paolo Siccardo has over 20 years of experience in General Management and Business Development of high technology products. Prior to the inception of Digital Keystone, Paolo Siccardo was Executive Vice President and General Manager of Digital Television products with SCM Microsystems, a leading OEM supplier of security technology. Previously Paolo Siccardo held positions as Senior Vice President of Marketing and Business Development with SunUp, a leader in content management software for the satellite and cable-TV industry; Vice President of Engineering and then General Manager with Hyundai Electronics, where he launched the world's first Open TV Set Top Box; and Project Manager at Hewlett-Packard, where he managed the development of the world's first Video on Demand Server. With Compression Labs, Paolo Siccardo developed the world's first AT&T videophone and PC video conferencing product. Paolo Siccardo holds a MSEE degree from the University of Genoa, Italy. Several U.S and International patents have been awarded or are pending in his name.
TV 2.0 - Digital TV in the networked home: technical, commercial and behavioral challenges.
TUESDAY December 4SCV Consumer Electronics
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 12
Mondo Magnets! Attractive (and Repulsive!) Devices
and Demonstrations Speaker: Dr. Fred Jeffers, IEEE Fellow and past
Distinguished Lecturer Time: Networking and food at 7:00 PM;
Presentation at 8:00 PM Cost: see website Place: National Semiconductor Building E
Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: Reserve in advance at mondomagnets.eventbrite.com
Web: www.ewh.ieee.org/r6/scv/leos
Entertaining and Educational Presentation for the
Whole Family! Dr. Fred Jeffers, IEEE Fellow, Distinguished
Lecturer, and author of Mondo Magnets! Attractive (and Repulsive!) Devices and Demonstrations performs amazing demonstrations of magnetism. You and your family will be awed and amazed by Dr. Jeffers' surprising and seemingly impossible demonstrations.
Each time Dr. Jeffers has come to the Bay Area to give his presentation, he has had an overwhelming audience response. Don't miss this opportunity to see his presentation yourself, and bring your family and friends!
This event is part of the IEEE LEOS Santa Clara Valley Chapter's Annual Holiday Lecture Series. The Holiday Lecture Series is humbly modeled after the popular Faraday Lectures of the Royal Society of London.
A sell-out crowd is expected. Be sure to register in advance! Online registration closes after Nov. 30.
TUESDAY December 4SCV Lasers and Electro Optics & Santa Clara Valley Section
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 13
Re-Live the Movie "The Matrix": From Harry Nyquist to Image-
Based Rendering Speaker: Prof. Tsuhan Chen, Department of
Electrical and Computer Engineering, Carnegie Mellon University, and IEEE Distinguished Lecturer
Time: Fast Food & drinks at 6:30 PM; Presentation at 7:00 PM
Cost: $2 Donation Recommended towards Refreshments
Place: National Semiconductor (north end of Building E), 2900 Semiconductor Dr., Santa Clara
RSVP: not required Web: ewh.ieee.org/r6/scv/sps
Tsuhan Chen has been with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, since October 1997, where he is currently a Professor and Associate Department Head. From August 1993 to October 1997, he worked at AT&T Bell Laboratories, Holmdel, New Jersey. He received the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology in 1990 and 1993, respectively. He received the B.S. degree in electrical engineering from the National Taiwan University in 1987. Tsuhan served as the Editor-in-Chief for IEEE Transactions on Multimedia in 2002-2004. He also served in the Editorial Board of IEEE Signal Processing Magazine and as Associate Editor for IEEE Trans. on Circuits and Systems for Video Technology, IEEE Trans. on Image Processing, IEEE Trans. on Signal Processing, and IEEE Trans. on Multimedia. He co-edited a book titled Multimedia Systems, Standards, and Networks. Tsuhan received the Charles Wilts Prize at the California Institute of Technology in 1993. He was a recipient of the National Science Foundation CAREER Award, from 2000 to 2003. He received the Benjamin Richard Teare Teaching Award at the Carnegie Mellon University in 2006. He is elected to the Board of Governors, IEEE Signal Processing Society, 2007-2009 and is a member of the Phi Tau Phi Scholastic Honor Society. He is Fellow of the IEEE, and a Distinguished Lecturer for the Signal Processing Society.
In recent years, the field of visual computing has observed a convergence of image processing, computer vision, and computer graphics. Multiview imaging represents one central theme of the convergence. Now widely used in applications ranging from special effects (e.g., in the movie "The Matrix") to 3D object tracking, multiview imaging has become an essential tool for creating informative visualization and effective 3D analysis. In this talk I will introduce recent research on sampling, reconstructing, and relighting multiview images. I will present our mobile camera array, composed of 48 mobile platforms each carrying a video camera. These mobile cameras respond to 3D scenes and position themselves for the most effective 3D analysis. While discussing the mechanism for sampling the 7-dimensional plenoptic function, we will reveal the connection between multiview imaging and the Sampling Theorem discovered by Harry Nyquist almost 80 years ago!
MONDAY December 10SCV Signal Processing
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 14
Wireless Standards: A History and Perspective /
CNSV Annual Meeting Speaker: Bruce Himebauch, Atheros
Communications Time: 7:00 PM Cost: none Place: Silicon Valley Technical Institute, 1762
Technology Dr., Suite 227, San Jose RSVP: not required Web: www.CaliforniaConsultants.org
Bruce Himebauch is Director of Solution Product Engineering in the Software Research and Development Group of Atheros Communications. His 25 years of network industry experience at companies such as Symbol Technologies and Proxim Corporation has focused on LAN communications.
Bruce has worked on a variety of communication technologies including Binary Synchronous Communications Protocols, System Network Architecture/Synchronous Data Link Control protocols, and 802.11x.
Note that this event takes place on the 2nd (not the 3rd) Tuesday of the month. Note also the change of venue for this meeting only. The talk will be preceded by the CNSV Annual Meeting and election of 2008 officers.
Most commercial wireless networking products
conform to the 802.11b, 802.11a, 802.11g and 802.11n standards, collectively known as Wireless Fidelity (Wi-Fi). Wi-Fi has been accepted in businesses, schools, government and homes as an alternative to wired LANs. The 802,11 standards have similarities to the 802.3 Ethernet standard, but they must also deal with range limitations, unreliable media and dynamic topologies.
Bruce Himebauch will present a history of the 802.11 standards family, the 802.11n Task Group N (TGn) and the issues surrounding implementation of 802.11 products. He will also describe the driving forces behind the creation of each new standard, including regulations, bandwidth issues, popularity and cost.
TUESDAY December 11SCV Consultants' Network of Silicon Valley
Demetrios Tziouvaras is a Senior member of IEEE, a member of the Power System Relaying Committee (PSRC), and a member of CIGRE. He is a Senior Research Engineer with Schweitzer Engineering Laboratories, Inc. (SEL). Prior to joining SEL in 1998, he was a Principal Protection Engineer for Pacific Gas and Electric Company, where he spent 18 years in power system protection and was an important contributor to protection designs that are still in use today.
Demetrios authored more than 35 IEEE and protective relay conference papers and holds three patents in the area of power system protection, with several patents pending. He served as chairman of a PSRC working group that developed an IEEE PES tutorial on “EMTP Applications to Power System Protection” and as vice-chair of a PSRC working group that developed a report on “Power Swing and Out-of-Step Considerations on Transmission Lines.” Currently, Demetrios is the convenor of CIGRE WG B5.15 on “Modern Distance Protection Functions and Applications” and a member of several IEEE PSRC and CIGRE working groups.
Demetrios has taught numerous seminars in digital relaying, protective relaying, and EMTP at the University of Illinois at Urbana-Champaign, the California Polytechnic Institute in San Luis Obispo, IEEE PES, and SEL University.
Alternating current (AC) electrical networks can experience loss of synchronism (out-of-step, OOS) during stressed power system conditions. During an OOS event, large current and voltage excursions develop across the electrical connection between two diverging grid sections. Proper detection of the OOS condition and separation of asynchronous system areas to avoid widespread outages and a potential collapse of the entire electrical grid is imperative. Come to this IEEE SF PES technical presentation to learn conditions that cause electrical OOS and where the grid is most susceptible. Learn how quickly an OOS condition can develop and what existing and future technology is being deployed to detect the OOS phenomenon and mitigate its effects.
THURSDAY December 13SF Power Engineering
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 16
PLL Design Essentials for Wireless Systems
Speaker: Derek K. Shaeffer, RF Engineering
Manager, Beceem Communications Time: Refreshment and Social Hour at 6:00 PM,
Presentation at 6:30 PM Cost: none Place: National Semiconductor, Bldg #9,
Classroom #4, 2900 Semiconductor Dr., Santa Clara
RSVP: not required Web: www.mtt-scv.org
Derek K. Shaeffer received the BSEE degree
from the University of Southern California in 1993, the MSEE degree from Stanford University in 1995 and the Ph.D. degree from Stanford University in 1999, for which he did early work in the field of RF CMOS, demonstrating the world’s first CMOS GPS receiver. He is the author or co-author of eight issued patents and several pending patents, twenty papers and a book on CMOS RF design. He has worked professionally in the fields of test instrumentation, semiconductor memory, optical and wireless communications. He is currently an RF Engineering Manager with Beceem Communications, where his work is focused on wireless transceivers for mobile WiMAX applications. Dr. Shaeffer also serves as an Associate Editor for the IEEE Journal of Solid-State Circuits.
This talk provides an overview of PLL design
fundamentals and reviews performance considerations that typify wireless systems. By the end of the talk, attendees will understand how to translate system performance requirements into synthesizer design specifications and will be equipped with a “toolkit” of techniques for modeling and quantifying expected performance.
THURSDAY December 13SCV Microwave Theory and Techniques
M E S OIn t eg r at io n
Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com
Web: www.ewh.ieee.org/r6/scv/leos Dr. Cun-Zheng Ning obtained his PhD in Physics
from University of Stuttgart, Germany. He was a Senior Scientist, group leader, or task manager at NASA Ames Center for Nanotechnology, NASA Ames Research Center from 1997-2006. He joined Arizona State University in 2006, where he is a Professor of Electrical Engineering, Affiliate Professor of Physics and Materials, with the Center for Nanophotonics, Arizona Institute of NanoElectronics and Center of Solid State Electronics Research(CSSER).
Dr. Ning has been conducting research in the general fields of laser physics, semiconductor lasers, optoelectronic device modeling and simulation for the last 20 years. Recently, his group has been involved in growth and optical characterization of semi-conductor nanowires. His group was the first to grow antimonide nanowires and first to demonstrate a single-nanowire infrared laser. He has published over 120 scientific papers and given many conference presentations including over 50 invited talks. He has served on many international conference committees including SPIE Photonics West, OSA annual meetings, and CLEO. He was Associate Editor of IEEE J. Quantum Electronics (2001-2003) and a special topic editor for IEEE J. Special. Topics in Quantum Electron., J. Opt. Soc. Am., Optics Express, etc. For his research at NASA, he has won many NASA and NASA contractor awards, including NASA Group Achievment (1999) award and CSS Technical Excellence Award (2003). He was recently awarded the IEEE/LEOS Distinguished Lecturer (2007/2008).
The pursuit of nanotechnology in general and miniaturization of electronic devices in particular have seriously challenged the optoelectronics community to develop ever smaller lasers and optoelectronic devices compatible with the trend in microelectronics. Vertical-cavity surface emitting lasers measured a few microns were once the smallest lasers. The situation is now rapidly changing over the last 5 years with the demonstration of lasing capability of a single semiconductor nanowire of ~ 100 nanometers in diameter. The ultimate challenge to the community is: can one make a laser that is smaller than the wavelength in all 3 dimensions, or what is the ultimate size limit of a laser?
To answer this and related questions, my lecture will start with an overview of impressive recent progress in growth, fabrication, and characterization of semiconductor nanowires and demonstration of lasing activities in various wavelengths. These lasers represent one of the smallest lasers of any kind at present. We will show how this new type of miniaturized laser differs from conventional semiconductor lasers. To further reduce the dimension of nanowire lasers, a recent proposal to use metal coating of semiconductor wires will be evaluated by numerical simulation. We will show that a proper design of a metal coated semiconductor nanowire can achieve lasing threshold despite significant metal loss. Finally some recent novel ideas involving surface plasmonic excitations at metal-semiconductor interface will be discussed where much smaller lasers could be potentially made, with size independent of wavelengths of light emitted.
THURSDAY December 13SCV Lasers and Electro Optics
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 18
Small Stuff in Search of the Big Bucks: Nanotechnology
Commercialization by Sector
Speaker: Kristin Abkemeier, Ph.D., Analyst at Lux
Research, Inc. Time: Registration & Light Lunch 11:30 AM,
Presentation at Noon Cost: IEEE Members and Students $5. Non-
Members $10 Place: National Semiconductor Bldg E-1 CMA
Room. 2900 Semiconductor Drive, Santa Clara
RSVP: at the website Web: www.ieee.org/nano
Dr. Kristin Abkemeier is an Analyst at Lux Research where she covers a broad range of emerging technologies including nanotechnology, semiconductor memory, solar power, and alternative power and energy storage. Her research and analysis help Lux Research clients to form strategic decisions by providing information that expands upon traditional business metrics. Her scientific research experience includes experimental and computational investigations of phenomena in several different semiconductor systems of interest to the field of fundamental physics. Kristin has published several articles in leading physics journals and has also worked as an information technology software developer and science communicator. She holds a Ph.D. in experimental condensed matter physics from the University of Chicago and a bachelor’s degree in electrical engineering from Princeton University.
Nanotechnology is shifting from research labs to
markets, as world investments reached $12.6 billion in 2006. With the first applications in-market in the materials, electronics and energy, and life science sectors, the impact of nanotechnology in different industries varies from broad and incremental in nature, to high and narrow in scope. While material performance has already been transformed, disruptive technologies are still in development. Successful commercialization of nanotechnology applications depends on executing, finding market pull, and partnering.
TUESDAY December 18SCV Nanotechnology
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 19
Educating Engineers in Advanced Silicon Processes
Speaker: Dr. Kris Verma Time: dinner at 6:30 PM, Presentation at 7:00 PM Cost: none Place: Silicon Valley Technical Institute; 1762
Technology Dr., Suite 227, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/es
Dr. Kris Verma is a Sr. Faculty and Program
Director at SVTII since 2004. Prior to that, he spent 32 years in High Tech Corporations such as HP, Tektronix, Lockheed, National Semiconductor, and more recently Seagate Technology.
He has developed various Silicon Processes in R&D, transfers to Manufacturing, Product Development, and Reliability/Failure analysis. He has published over 17 papers in the Semiconductor Device/Process area.
IEEE awarded him the Millennium Medal in year 2000 for his vast engineering contributions in the Semiconductor Processing area, and significant contributions in various IEEE Conferences. Currently he is a Plenary Chair and Fellow for ISQED. In addition, he is Vice- chair for the Nanotechnology Council in the SF Bay Area IEEE and a Senior Life time IEEE Member.
He earned his Ph.D EE from University of Utah and M.B.A from University of Portland.
During the last two decades, the Semiconductor
Industry model has changed from Vertical (Design, Fab, Test, and Packaging) under one IDM (Integrated Device Manufacturer) to a Horizontal model (Fabless Design Houses, IP developers, Wafer Mega Foundries, and subcontractors for test and assembly) under different companies’ management. This new business model has created good business opportunities and growth, but created some challenges to young engineers for learning opportunities in various areas in the same company. The problem has been further compounded, since most of Silicon Process development (R&D) work and Manufacturing have now moved to Asia.
Due to very aggressive process scaling over the last 10 years (5 nodes in 10 years), nanoscale node process variations and impact on Design yield have forced designers and product engineers to learn Silicon Processes for successful product introduction to manufacturing. Extensive process simulations and TCAD tools expertise became necessary. This process knowledge allows them to interact with the Mega foundries (in ASIA) effectively.
This talk will cover advanced Silicon Processes (ITRS, NanoCMOS nodes, Life after CMOS) and some ideas on how to educate a new generation of engineers in this exciting Industry.
WEDNESDAY December 19SCV Education
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 20
Flexible/Printable Electronics /
Organic LED (OLED) Display Technology
Speakers: Dr. Chuck Bauer, TechLead Corporation;
and Dr. Johann Trujillo, DuPont Displays Time: Optional dinner at 6:30 PM, Presentation at
7:30 PM Cost: $25 for dinner, no cost for presentation Place: Ramada, 1217 Wildwood Ave (Fwy 101
frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale
Charles E. Bauer, Ph.D. serves as Senior Managing Director of TechLead Corporation, a technology management company specializing in the electronics packaging, interconnection and assembly industry. Dr. Bauer focuses in the areas of strategic technology planning, market analysis and business development, primarily in the international arena. With more than 20 years experience spanning the range from printed circuit board and hybrid fabrication through complex IC metallization, multilayer packaging, multichip modules (MCMs) and flat panel display packaging and assembly, he brings tremendous breadth and depth to his work. Dr. Bauer lectures throughout the world on technology, business and market topics as well as serving on several corporate boards and international corporate, government and educational institution advisory councils.
Chuck served ISHM as President of the NW Chapter, Technical Chair of the ISHM National Symposium in Seattle, National Technical Vice President of the Society and President of the Rocky Mountain Chapter. Dr. Bauer also served on the Board of Directors of the SMTA from 1997 through 2001 when elected President of IMAPS for 2001-2002. He now serves as Chair of the SMTA International Development Committee and remains active internationally with the SMTA, IEEE, IMAPS, JIEP and ASM Dr. Johann Trujillo, DuPont Displays
(biography to follow)
Flexible/Printable Electronics
The printed electronics market comprises next-generation light, power and circuitry products, including flexible displays, plastic solar cells and organic RFID tags. Special inks enable the formation of active electrical layers -- the key drivers for printed electronics. The printed electronics market comprises next-generation light, power and circuitry products, including flexible displays, plastic solar cells and organic RFID tags. The market for printed electronics was approximately $1 billion in 2006 and is expected to exceed $300 billion within 20 years. OLED Display Technology
This talk will discuss a unique manufacturing process utilizing solution processing of small molecule materials for OLED displays and a material set including DuPont™ HIL hole injection layer and DuPont light emitting and charge transport materials – the essential materials used to make an OLED display.
The OLED displays industry is under constant pressure to reduce manufacturing costs in order to compete with LCDs, This process should have the ability to overcome the cost barriers the industry has been facing.
We have measured accelerated lifetimes of the three primary colors that could translate in a display to 20,000 hours of white lifetime (which is extended by as much as 5 times when showing video) at a normal viewing brightness (200 cd/m2). At 1,000 cd/m2— the standard test luminance used in the industry — the DuPont materials have lifetimes (T50) of 14,000 hours for blue with CIE 1931 color coordinates of (0.14, 0.16), 230,000 hours for green with color coordinates of (0.29, 0.65), and 46,000 hours for red with color coordinates of (0.66, 0.34). In a review of widely available reports, these are the longest measured lifetimes for a solution material set with equivalent color coordinates.
The OLED materials are printed onto active-matrix thin-film transistor (TFT) backplanes supplied by leading TFT providers, and then protected from environmental degradation with encapsulation technology.
WEDNESDAY January 16SCV Components, Packaging and Manufacturing Technology
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 21
Variation Robustness for Analog/Mixed-Signal, Custom Digital, and Memory Design
Speaker: Patrick Drennan, Chief Technology Officer,
Solido Design Automation, Inc. Time: Fast Food & drinks at 6:30 PM, Presentation
at 7:00 PM Cost: none Place: Cadence Design Systems, Building 5, 655
Seely Avenue, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/cas
Patrick Drennan is Chief Technology Officer of Solido Design Automation, Inc. Prior to joining Solido, Patrick was a Distinguished Member of the Technical Staff at Freescale Semiconductor (formerly Motorola, Inc.). Patrick was one of the creators of the backwards propagation of variance (BPV) method for statistical characterization. This model guarantees consistency between simulation and silicon measurement and it is valid for all biases and geometries, which are significant attributes for design. His mismatch (local variation) model earned the Best Regular paper at the 2002 IEEE Custom Integrated Circuit Conference. He was the first to describe the impact of shallow trench isolation (STI) and well proximity effect (WPE) on design, demonstrating that the WPE produces a graded channel MOSFET. More importantly, he showed the catastrophic impact these unforeseen phenomena can have on circuit design. For this work, he received the Best Invited Paper at the 2006 IEEE Custom Integrated Circuit Conference. Patrick has extensive experience in measurement, modeling, characterization, test structure generation and design application of systematic and stochastic semiconductor variations. Patrick received the B.S. degree in microelectronic engineering and M.S. degree in electrical engineering from Rochester Institute of Technology and the Ph.D. degree in electrical engineering from Arizona State University.
As process technologies and supply voltages
shrink, designers are faced with a pressing need to address systematic and random sources of variation in a more deliberate and thorough way. Accounting for variation within the flow of design has not progressed commensurate with the process technologies. We still rely on best-, worst- case corners, mismatch plots and maybe a Monte Carlo verification if there is enough time. It is time for a new approach. This talk will begin with a brief review of the physical phenomena and industry-standard device models for variation sources, including random local and global variations and systematic proximity effects. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented.
MONDAY January 21SCV Circuits and Systems
D e c e m b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 22
The Spin on Electronics! Spin-valves and Magnetic
Tunneling Junctions Speaker: Stuart Parkin, IBM Almaden Research
Center, and 2008 IEEE Magnetics Society Distinguished Lecturer
Time: Cookies & Conversation at 7:30 PM, Presentation at 8:00 PM
Parkway, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Stuart Parkin is an IBM Fellow and Manager of the
Magnetoelectronics group at the IBM Almaden Research Center and a consulting professor in the Department of Applied Physics at Stanford University. He is also director of the IBM-Stanford Spintronic Science and Applications Center, which was formed in 2004. He received his BA and PhD degrees from the University of Cambridge and joined IBM as a postdoctoral fellow in 1982, becoming a permanent member of the staff the following year. In 1999 he was named an IBM Fellow, IBM’s highest technical honor. Parkin’s research interests have included organic superconductors, high-temperature super-conductors, and, for almost the past two decades, magnetic thin film structures and spintronic materials and devices for advanced sensor, memory, and logic application.
He is a Fellow of the Royal Society, the American Physical Society, the Institute of Physics (London), the Institute of Electrical and Electronics Engineers, and the American Association for the Advancement of Science. Parkin is the recipient of numerous honors, including a Humboldt Research Award (2004), the 1999-2000 American Institute of Physics Prize for Industrial Applications of Physics, the European Physical Society’s Hewlett-Packard Europhysics Prize (1997), the American Physical Society’s International New Materials Prize (1994), the MRS Outstanding Young Investigator Award (1991) and the Charles Vernon Boys Prize from the Institute of Physics, London (1991). In 2001, he was named R&D Magazine’s first Innovator of the Year and in October 2007 was awarded the Economist Magazine’s "No Boundaries" 2007 Award for Innovation. Parkin has been awarded Honorary Doctorates by the University of Aachen, Germany and the Eindhoven University of Technology, The Netherlands. Parkin has authored ~350 papers and has ~63 issued patents.
Today, nearly all microelectronic devices are based on storing or flowing the electron’s charge. The electron also possesses a quantum mechanical property termed "spin", that gives rise to magnetism. Electrical current is comprised of "spin-up" and "spin-down" electrons, which behave as largely independent spin currents. The flow of these spin currents can be controlled in thin-film structures composed of atomically thin layers of conducting magnetic materials separated by non-magnetic conducting or insulating layers. The resistance of such devices, so-called spin-valves and magnetic tunneling junctions, respectively, can be varied by controlling the relative magnetic orientation of the magnetic layers, giving rise to magnetoresistance tailored for different applications. Recent advances in generating, manipulating and detecting spin-polarized electrons and electrical current make possible new classes of spin based sensor, memory and logic devices, generally referred to as the field of spintronics. In particular, the spin-valve is a key component of all magnetic hard-disk drives manufactured today and enabled their nearly 1,000-fold increase in capacity over the past eight years. The magnetic tunnel junction allows for a novel, high performance random access solid state memory which maintains its memory in the absence of electrical power. The respective strengths of these two major classes of digital data storage devices, namely the very low cost of disk drives and the high performance and reliability of solid state memories,
may be combined in the future into a single spintronic memory-storage technology, the magnetic Racetrack. The Racetrack is a novel three dimensional technology which uses nanosecond long pulses of spin polarized current to move a series of magnetic domain walls along magnetic nanowires.
TUESDAY January 29SCV Magnetics
VOICE COIL MOTORS Design - Control - Fabricate - Test
Parkway, San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag
Bruce D. Terris received the B.S. degree in applied physics from Columbia University and the M.S. and Ph. D. degrees in physics from the University of Illinois at Urbana-Champaign. After receiving his doctorate, he was a post-doctoral fellow for two years at Argonne National Laboratory. In 1985, he joined IBM as a Research Staff Member at the Almaden Research Center, San Jose, and subsequently joined Hitachi GST when it was founded in 2003 and where he is currently the manager of Nanostructures group. His research interests have included thin film superconductivity and magnetism, contact electrification of insulators, and new types of scanning probe microscopes (STM, AFM, near-field optical, etc.). His current research is on nanoscale patterning of magnetic structures, thermally assisted magnetic recording, novel approaches to high density data storage and spin torque devices.
He has co-authored over 90 refereed publications and been issued more than 20 US patents. He has recently served as program co-chair for Intermag 2006 and program chair for the Nanoscale Science and Technology Division of AVS for 2005. He currently serves on the Administrative Committees of the IEEE Magnetic Society and the MMM conference and will serve as US program chair for Intermag 2008 and US Conference Chair for Intermag 2011 (Taipei). He is a Fellow of the APS and AVS, and is a member of IEEE.
As conventional magnetic recording technology
extends to ever higher areal density, it is possible the often predicted, and constantly increasing, density limit will be reached. This limit will likely be in the range of 750 - 1000 Gb/in2. The use of nano-fabrication to create patterned magnetic elements, or patterned media, is one of the proposed approaches with the promise of delaying the onset of superparamagnetism and thus enabling higher areal density. I will discuss many of the challenges that must be overcome for patterned media to be successful, including fundamental physics and material science issues, new fabrication technologies, nm-scale manufacturing tolerances, and low cost budgets.
One of these challenges is to controllably reverse one magnetic element, or bit, without affecting the neighboring elements. A narrow anisotropy distribution will be required, yet data suggest that as the element size shrinks, the distribution widens. This distribution arises from a number of sources, including shape and size distributions, edge effects, variations in the full film anisotropy and magnetostatic fields from neighboring elements. As will be discussed, understanding and controlling the switching properties of magnetic nanostructures is critical not only for patterned media, but for device applications such as MRAM cells and spintronic devices and, for current induced as well as field induced reversal.
