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8/12/2019 Handout CMOS Power Consumption
http://slidepdf.com/reader/full/handout-cmos-power-consumption 1/21
CMOS Inverter Power
Dissipation
8/12/2019 Handout CMOS Power Consumption
http://slidepdf.com/reader/full/handout-cmos-power-consumption 2/21
Why worry about power? -- Power
Dissipation
P6Pentium ®
486
386
2868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P o
w e r ( W a t t s )
Lead microprocessors power continues to increaseLead microprocessors power continues to increase
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
ource: Borkar, De Intel
8/12/2019 Handout CMOS Power Consumption
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Why worry about power? -- Chip
Power Density
40048008
8080
8085
8086
286386
486Pentium®
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
P o w e r D e n s i t y ( W / c m 2 )
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Sun’s
Surface
…chips might become
Source: Borkar, De Intel
8/12/2019 Handout CMOS Power Consumption
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CMOS inverter power
Power has three components – Static power : when input isn’t switching
– Dynamic capacitive power : due to charging and
discharging of load capacitance
– Dynamic short-circuit power : direct current
from VDD to Gnd when both transistors are on
8/12/2019 Handout CMOS Power Consumption
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CMOS inverter static power
• Static power consumption: – Static current: in CMOS there is no static current as long as Vin <
VTN or Vin > VDD+VTP
– Leakage current: determined by “off” transistor
– Influenced by transistor width, supply voltage, transistor threshold
voltages
VDD
VI<VTN
Ileak,n
Vcc VDD
Ileak,p
Vo(low)
VDD
8/12/2019 Handout CMOS Power Consumption
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Leakage (Static) Power Consumption
Sub-threshold current is the dominant factor.
All increase exponentially with temperature!
VDD Ileakage
Vout
Drain junction
leakage
Sub-threshold currentGate leakage
8/12/2019 Handout CMOS Power Consumption
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Dynamic Power Consumption
Vin Vout
CL
Vdd
8/12/2019 Handout CMOS Power Consumption
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Dynamic Capacitive Power and energy stored in the
PMOS deviceCase I: When the input is at logic 0: Under this
condition the PMOS is conducting and NMOS is in
cutoff mode and the load capacitor must be
charged through the PMOS device.
Power dissipation in the PMOS transistor is given by,
PP=iLVSD= iL(VDD-VO)
The current and output voltages are related by,
iL=CLdvO/dt
Similarly the energy dissipation in the PMOS device
can be written as the output switches from low to
high ,
Above equation showed the energy stored in the
capacitor CL when the output is high.
2
2
0
2
0
0000
2
1
)02
()0(,2
,)(
DD L P
DD L DD DD L P
V
O L
V
O DD L P
O
V
O L
V
O DD L P O
O DD L P P
V C E
V C V V C E C V C E
d C d V C E dt dt
d V C dt P E
DD
DD
DD DD
8/12/2019 Handout CMOS Power Consumption
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Power Dissipation and Total Energy Stored in the
CMOS DeviceCase II: when the input is high and out put is
low:
During switching all the energy stored in the load
capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in
cutoff mode. The energy dissipated in the NMOS
inverter can be written as,
The total energy dissipated during one switching
cycle is,
The power dissipated in terms of frequency can be
written as
2
2
1 DD L N V C E
222
2
1
2
1 DD L DD L DD L N P T V C V C V C E E E
2
DD LT T
T V fC fE P t
E P t P E
This implied that the power dissipation in the CMOS inverter is directly
proportional to switching frequency and V DD
2
8/12/2019 Handout CMOS Power Consumption
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Dynamic capacitive power
• Formula for dynamic power:
• Observations
– Does not (directly) depend on device sizes
– Does not depend on switching delay
– Applies to general CMOS gate in which:• Switched capacitances are lumped into CL
• Output swings from Gnd to VDD
• Input signal approximated as step function
• Gate switches with frequency f
f V C P DD Ldyn
2
Not a function of transistor sizes!
Data dependent - a function of switching activity!
8/12/2019 Handout CMOS Power Consumption
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Lowering Dynamic Power
Pdyn = CL VDD2 f
Capacitance:
Function of fan-out,wire length, transistorsizes
Supply Voltage:
Has been droppwith successivegenerations
Clock frequency:Increasing…
8/12/2019 Handout CMOS Power Consumption
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Short Circuit Power Consumption
Finite slope of the input signal causes a direct
current path between VDD and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Vin Vout
CL
Isc
8/12/2019 Handout CMOS Power Consumption
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Dynamic short-circuit power
• Short-circuit current flows from VDD to Gnd when both transistors are
on
• Plot on VTC curve:
VCC
VCCVin
Vout ID
Imax
Imax: depends on
saturation current
of devices
8/12/2019 Handout CMOS Power Consumption
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Dynamic short-circuit power
• Approximate short-circuit current as a triangular wave
• Energy per cycle:
f I V t t
P
I V t t t I
V t I
V E
CC
f r
sc
CC
f r f
CC r
CC sc
max
max
maxmax
2
222
Imax
8/12/2019 Handout CMOS Power Consumption
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Short Circuit Currents Determinates
• Duration and slope of the input signal, tsc
• I peak determined by
– the saturation current of the P and N transistors which
depend on their sizes, process technology, temperature,
etc.
– strong function of the ratio between input and output
slopes
• a function of CL
Psc = tsc VDD Ipeak f 01
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Impact of CL on Psc
Vin Vout
CL
Isc 0Vin Vout
CL
Isc Imax
Large capacitive load
Output fall time significantly
larger than input rise time.
Small capacitive load
Output fall time substantially
smaller than the input rise
time.
8/12/2019 Handout CMOS Power Consumption
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I peak as a Function of CL
-0.5
0
0.5
1
1.5
2
2.5
0 2 4 6
I p e a k
( A )
time (sec)
x 10-10
x 10-4
CL = 20 fF
CL = 100 fF
CL = 500 fF
500 psec input slope
Short circuit dissipatio
is minimized by
matching the rise/fall
times of the input and
output signals - slope
engineering.
When load capacitan
is small, Ipeak is large.
8/12/2019 Handout CMOS Power Consumption
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Inverter power consumption
• Total power consumption
leak CC
f r
CC CC Ltot
stat scdyntot
I V f
t t
I V f V C P
P P P P
2max
2
8/12/2019 Handout CMOS Power Consumption
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Power reduction• Reducing dynamic capacitive power :
– Lower the voltage (Vdd)!
• Quadratic effect on dynamic power
– Reduce capacitance
• Short interconnect lengths
• Drive small gate load (small gates, small fan-out)
– Reduce frequency
• Lower clock frequency -
• Lower signal activity
fV C P DD Ldyn
2
8/12/2019 Handout CMOS Power Consumption
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Power reduction
• Reducing short-circuit current:
– Fast rise/fall times on input signal
– Reduce input capacitance
– Insert small buffers to “clean up” slow input
signals before sending to large gate
• Reducing leakage current: – Small transistors (leakage proportional to
width)
– Lower voltage
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Retrospect on Design Trade-offs
• Design trade-offs dancearound the triangle, but
still important
• Fundamental improvemen
that shrinks the triangle:
– Scaling in technology
(lithographyimprovement)
– New functionality
– New architecture
– New algorithms
Good
Fast Cheap
(Lower-power and Robust)
(Short Delay) (Small Layout)