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Hardware description language(HDL) VHDL and Verilog considerents
Hardware description language(HDL)
VHDL and Verilog considerents
HDL Applications
Hardware description languages (HDL - Hardware Description Language) – are languages
developed and optimized to describe the behavior of digital systems.
the HDL model can be
reused for several projects
VHDL (VHSIC HDL - Very High Speed Integrated Circuit Hardware Description
Language) - IEEE standard 1076 since 1987. It was redone in 1993, becoming " IEEE
standard 1076 /1993".
Verilog HDL is older than VHDL and has been extensively used since 1983. It has become
IEEE standard 1364 I /1995.
There are 2 important aspects for hardware modeling in any HDL : abstract behavior and
hardware structure.
VHDL/Verilog – comparison
Capability:
The hardware structure can be modeled by both types of language. Choosing a languge type
is done based on personal preference, availability of development tools, etc.
Figure 1. HDL – modeling capabilities as a
function of abstraction level
Compiling VHDL.
Multiple design units (pairs entity/architecture), located in the same system file, can be
compiled separately. A good design will have each unit in a different file.
Verilog.
We must take into account the order in which the compiling of the code written in the same
file and the compiling of several files are done. The simulation results can change by simply
changing the order of the compiling.
Data types VHDL.
Several data types defined by the language, but also by the user can be used. There are
dedicated functions that perform the conversion from one data type to another. VHDL is
prefered due to the fact that it offers a larger flexibility.
Verilog.
Compared to VHDL, data types in Verilog are simple, easy to use and close to hardware
structure modeling oposed to abstract hardware modeling.
User defined data types are not allowed.
Data types example: net, wire, reg (register).
Reusing the design VHDL. Procedures and functions can be placed in a package so that they are available for any
design.
Verilog. The concept of package like in VHDL does not exist. The functions and procedures
used in a model have to be defined in a module. In order to make them accessible from
different modules, they are placed in separate files and included where necessary by using the
compiling directive „include”.
Ease of learning Verilog is probably easier to learn. VHDL can seem less intuitive, but after learning it, it is
more robust and stronger. There are more possibilities to model the same circuit, especially for
large, hierarchical structures.
High level constructions VHDL. There are more possibilities for high level modeling in VHDL than in Verilog. The
abstract data type can be used with the following declarations:
* package – for reusing the model,
* configuration - configuring the design structure,
* generate – for repetitive structures,
* generic – generic model that can be individualy characterized, for example the width of a
vector
All these language declarations are useful in synthesizing a model.
Verilog. Besides parameterization of a model by overloading the parameters, there is no
equivalent for high level modeling.
Language extension VHDL. It has an atribute called „foreign” which allows architectures and subprograms to be
modeled in other languages.
Verilog. It uses Programming Language Interface (PLI) – an interfacing mechanism between
the Verilog model and the Verilog development tools. A Verilog tools seller may specify
functions in C and call them from the Verilog source description.
Using these special functions will create nonstandard models and thus they probably cannot be
used by other Verilog tools. Using them is not recomanded.
Libraries
VHDL. A library is used to store compiled entities, architectures, packages and configurations.
They are useful for projects with multiple designs.
Verilog. The concept of library does not exist in Verilog. This is because at the origins this is an
interpretive languge.
“Low level” constructions VHDL. Simple logical operators for two inputs which are built in the language: NOT, AND,
OR, NAND, NOR, XOR and XNOR. Any time specification has to be done after the „after”
clause.
Verilog. Verilog was developed based on gate level modeling. Example: User Defined
Primitive(UDP), truth tables and blocks for specifying a delay in a module.
Managing large projects VHDL. The configuration, generate, generic and package declarations are used to manage large
projects.
Verilog. There are no declarations that can help manage large projects.
Operators Most operators are the same in both languages. Verilog has unary operators for reduction, which
in VHDL is done by using loops. VHDL has an operator module that does not exist in Verilog.
Model parameterization
VHDL. A specific model of a certain bit width can be instantiated through an n-bit generic
model using a generic type declaration. The generic model will not be synthesized unless it is
instantiated and the generic value is given.
Verilog. A specific bit width in a model can be instantiated from a generic n-bit model by
overwriting the parameters. The generic model has to have a defined implicid value.
Procedures and tasks
VHDL allows calling competing procedures. Verilog does not allow competing calls.
Ease of code understanding
VHDL is a concise language with its roots in Ada language. Verilog is closer to C due to the fact
that it is built based on 50% C and 50% Ada.
Structural replication
VHDL. The generate statement – allows the use of several instances of the same design and
proper connectivity between them.
Verilog. Does not have an equivalent for generate.
VHDL – Language basics
HDLs have two main atributions:
•Modeling (simulating)
•Descripting (synthesis)
VHDL has a lot of ways to describe the behavior of a lot of electronic components, from
logic gates to microprocessors. (We can describe the rising and falling slopes of signals, gate
delays, functional operations.).
VHDL offers 2 object classes
that can be used for hardware
modeling
Fundamental concepts: concurrence and hierarchy
VHDL – Area of use
•Hardware design
•ASIC: technology mapping
•FPGA: CLB mapping
•Standard solutions, models, behavior descriptions
•Software design
•VHDL - C interface (specific tools)
•research (hardware/software co-design). The question is which part should be
implemented in software and which in hardware. (the constraints are given by
performance, requirements and price)
Standards for VHDL
VHDL is build by using several IEEE standards:
• IEEE std 1076-1987 – the first VHDL standard. Referred to as VHDL’87.
• IEEE std 1076-1993 – the second VHDL standard. Referred to as VHDL’93.
• IEEE std 1164-1993 - package STD_LOGIC_1164. Includes types referring to hardware and
conversion functions.
• IEEE std 1076a - improves the use of shared variables.
• IEEE std 1076.1 VHDL-AMS, - extended standard for analogic.
• IEEE std 1076.2 – mathematical packages. It is divided into a package for real numbers and another
for imaginary ones.
• IEEE std 1076.3 – describes operators and types for synthesis.
• IEEE std 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries). – It is used, for example, to
specify the simulation time.
• IEEE std 1076.5 – modeling libraries in VHDL.
• IEEE std 1076.6 – defines the part necessary for RTL synthesis.
• Execution of
assignments:
• Sequential
• Concurrent
• Methodologies:
modeling techniques
• Abstraction
• Modularity
• Hierarchy
It is sequentially exectued, like in any programming language. The order in which
statements and atributions appear is important.
The statements are always active, the order is not important. They are used for parallel
models.
VHDL Concepts: concurency and hierarchy
Abstraction – allows describing different parts of the system. The information which is too
detailed and unimportant for the description is removed. The abstraction level is charcterized by
information common to all the models at this level.
Abstraction level in IC design
At the behavior level we describe the model functioning. There is no system clock, signal
transitions, etc. Usually, it can be simulated, but not synthsized.
Register Transfer Level (RTL) – the design is divided into combinational logic elements and
storage elements. Storage elements (Flip Flops (FFs), latches) are controlled by the system
clock. The description done at the RT level is called synthesized description.
At the logic level, the design is represented as a list of gate links (AND, OR, NOT,…) and
storage elements.
Behavior description in VHDL
o <= transport i1 + i2 * i3 after 100 ns;
RT Level in VHDL
In VHDL the functional behavior is modeled using processes.
In RT level:
•purely combinational process
•clock controlled process (it involves FF and can be described in state machine terms)
Gate Level in VHDL
Each element of the circuit (ex. U86) is instatiated as a component (ND2) and is connected
to the corresponding signals (n192, n191, n188). Each gate used is part of a library which
contains additional information such as surface, propagation delays, capacity, etc.
Modularity and hierarchy
Modularity – Larger functional blocks are partitioned into smaller units. The existance of subsystems
allows multiple designers to work in parallel at the same project.
Hierarchy – a design can be made up of modules which can ,in turn, contain sub-modules. An hierarchic
level can contain one or more modules with different dregrees of abstraction.
Modularity and hierarchy allow the organization of a project.
The design process begins with the specification phase. The designed component is defined in
terms of functions, interface, etc.
The contained modules have to be defined at system level. We describe the interface (inputs,
outputs, data format), clock dimension, reset mechanism. Based on this information we can
implement the simulation model. The behavioral model can be integrated in the system using the
already existing models.
Logic level - the model has to be described taking into account all the necessary aspects to make
it synthesizable. After the synthesis the boolean functions are derived from the abstract model
description and the elements are mapped in the logical blocks of the FPGA or in the gate library
for ASIC. The result is a list of connections, gate level netlist.
Each transition to a lower abstraction level will be checked through validation. For this purpose,
we simulate the description such that for all the stimuli (=simulation input signals) we compare
with the module’s responses.
VHDL is suitated for design from system level to gate level.
Only a subset of the VHDL language is synthesizable!
•Comments: '--' until the end of the line
•Statements end with ';‘
•List delimiter ','
•Signal assignment: '<='
•User defined names:
•Letters, numbers, underscores
•Start with a letter
Generalities
---------------------------------
-- Example VHDL Code --
----------------------------------
signal mySignal: bit; -- an example signal
MYsignal <= '0', -- start with '0'
'1' AFTER 10 ns, -- and toggle after
'0' after 10 ns, -- every 10 ns
'1' afTer 10 ns;
VHDL Structural elements
•Entity : desribes an interface made up of a list of ports
•Architecture : describes the function of the corresponding module
•Configuration : model, structure, hierarchy (generally it is used for simulation)
•Process : it allows a sequential execution – controlled event
•Package : for modular design. Contains: standard solutions, data types, constants
•Library : a colection of compiled VHDL units (object cod)
Statement placing for different objects in VHDL
Ex. Stating a
port is allowed
only in an
entity
Entity and architecture (Entitie / Architectures)
Each description of a VHDL design will contain at least one pair entity/architecture
( also reffered to as design entity).
•entity – describes the circuit as it appears from the outside, from the input/output interface perspective.
The complete interface of the circuit shall be provided (name, direction and data type for every port).
•architecture – every entity will have a corresponding architecture that will describe its function.
Anything declared in the entity will be automatically accessible in the architecture.
General structure of
the architecture
A module can be made up of several sub-modules. The connection between sub-modules is
defined in a “top module” architecture type. Example: a fulladder module can be made from 2
halfadders modules (module1, module2) and an OR gate (module3).
A structural architecture will contain a list of components and the interconnections definition.
Hierarchy connection
Component declaration and instantiation
Component instantiation: Associating signal names
A process which is regarded as a whole is
treated concurrently as any declaration
from an architecture
Example of a process:
Example of a process:
Example of a process:
package – collects globaly used statements for different design units. Made up of: type statements,
constants, sub-programs, etc. These will be visible in any design unit from the project and can be
compiled in a library for further use. It is composed of 2 parts: declarative part and optional corpus. With
the help of use we can use it in design units.
Exemplu:
Libraries
VHDL communication model
All the processes are parallely executed, without taking into account the entity or the
hierarchy level where they are located. They communicate through signals.
Objects, data types and operators
Objects – used to represent and store data.
Basic types (used to describe a design for synthesis or to create functional tests – test
waves): signals, variables and constants
Each declared object has a specific data type - data type (such as bit or integer) with a
unique set of possible values. Example: a bit type object can have only two possible
values, '0' and '1',
Note: VHDL symbol <= - represents the attribution operator (assignation) (assigns the value on the right
to the variable on the left )
Standard Logic data types
Standard Logic IEEE 1164
The std_logic_1164 package is compiled in a library called ieee, and includes the following
data types:
Type Std_ulogic – represents a single wire that can have different logic values
std_ulogic – is an enumerating type similar to the bit type from the 1076 standard. It is an
“unresolved” data type. This type of signal can have only a single driver,
Tipul std_ulogic_vector
Reprezinta o colectie de fire (wire) sau un bus de marime arbitrara.
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
Std_ulogic_vector – represents an area of std_ulogic, and is equivalent to the bit_vector
standard type.
Std_logic type
Is a “resolved” data type based on std_ulogic (it is a sub-type), with the following
statement: subtype std_logic is resolved std_ulogic;
In the case of multiple drivers, the nine std_logic values are solved using values as
shown: ("std_logic" allows the existance of multiple drivers for a simple signal)
Std_logic_vector type type std_logic_vector is array ( natural range <>) of std_logic;
Standard operators:
The values, signals and variables of a port can be combined in expressions by using operators
Example: Describing a comparator using IEEE 1164 standard logic
comment
declarare library – the IEEE library is loaded.
Use - specifies what part of the ieee library is
available for the made design (declared through
antity and architecture). The general form
includes 3 fields, separated by dots.
std_logic and std_logic_vector, are standard
data types from the IEEE 1164 standard and in
the associated IEEE library
Describes the functionality of
the comparator
ANNEXES
Problem: Making an algorithm and a circuit that can find the greatest common divisor. We shall use
VHDL, Verilog, C languages.
1) At algorithm level we will make 3 algorithms that determine the greatest common divisor (GCD) – in C
and in 2 hardware description languages: VHDL and Verilog.
2) At RTL level the GCD algorithms will be modeled for synthesis in both types of HDL languages, VHDL
and Verilog. The model has to be generic, in order to be useful for different types of bit widths.
Load Signal– indicates when the input data is valid
Done Signal (led) – will be activated once the ouptut data is valid
The Generic Model will be checked for 8 bit signals.
3) The models will be tested: 1) the same file will be used for the algorithm level 2) both RTL models will be
instantiated at synthesized gate level and will be simultaneously simulated and tested.
Test file:
file: gcd_test_data.txt file: gcd_test_data_hex.txt 21 49 7 15 31 7 // Decimal 21 49 7
25 30 5 19 1E 5 // Decimal 25 30 5
19 27 1 13 1B 1 // Decimal 19 27 1
40 40 40 28 28 28 // Decimal 40 40 40
250 190 10 FA 6E A // Decimal 250 190 10
5 250 5 5 FA 5 // Decimal 5 250 5
The algorithm used is the following:
C modeled algorithm: #include <stdio.h>
main ()
{
int A_in, B_in, A, B, Swap, Y, Y_Ref, Passed;
FILE *file_pointer;
file_pointer = fopen("gcd_test_data.txt", "r");
Passed = 1;
while (!feof(file_pointer))
{
/*------------------------------------*/
/* Read test data from file */
/*------------------------------------*/
fscanf (file_pointer, "%d %d %d\n", &A_in, &B_in, &Y_Ref);
/*----------------------------------*/
/* Model GCD algorithm */
/*----------------------------------*/
A = A_in;
B = B_in;
if (A != 0 && B != 0)
{
while (B != 0)
{
while (A >= B)
{
A = A - B;
}
Swap = A;
A = B;
B = Swap;
}
}
else
{
A = 0;
}
Y = A;
/*------------------------------*/
/* Test GCD algorithm */
/*------------------------------*/
if (Y != Y_Ref)
{
printf ("Error. A=%d B=%d Y=%d Y_Ref= %d\n", A_in, B_in, Y, Y_Ref);
Passed = 0;
}
}
if (Passed = 1) printf ("GCD algorithm test passed ok\n");
}
Algorithm described in VHDL
The VHDL model has the same principle as the one in C. When the integer values are read from the
test file, these are introduced into a variable, they cannot be read and assigned to a signal. The
results will be written in a file. Due to the fact that it is at algorithm level, the entity used won't
contain neither inputs nor outputs.
VHDL algorithmic level model
library STD;
use STD.TEXTIO.all;
entity GCD_ALG is
end entity GCD_ALG;
architecture ALGORITHM of GCD_ALG is
--------------------------------------------
-- Declare test data file and results file
--------------------------------------------
file TestDataFile: text open
read_mode is "gcd_ test_data.txt";
file ResultsFile: text open write_mode is
"gcd_alg _test_results.txt";
begin
GCD: process
variable A_in, B_in, A, B, Swap, Y, Y_Ref: integer range 0 to 65535;
variable TestData: line;
variable BufLine: line;
variable Passed: bit := '1';
begin
while not endfile(TestDataFile) loop
-------------------------------------
-- Read test data from file
-------------------------------------
readline(TestDataFile, TestData);
read(TestData, A_in);
read(TestData, B_in);
read(TestData, Y_Ref);
------------------------------------
-- Model GCD algorithm
------------------------------------
A := A_in;
B := B_in;
if (A /= 0 and B /= 0) then
while (B /= 0) loop
while (A >= B) loop
A := A - B;
end loop;
Swap:= A;
A := B;
B := Swap;
end loop;
else
A := 0;
end if;
Y := A;
---------------------------------
-- Test GCD algorithm
---------------------------------
if (Y /= Y_Ref) then -- has failed
Passed := '0';
write(Bufline, st ring'("GCD Error: A="));
write(Bufline, A_in);
write(Bufline, string'(" B="));
write(Bufline, B_in);
write(Bufline, string'(" Y="));
write(Bufline, Y);
write(Bufline, string'(" Y_Ref="));
write(Bufline, Y_Ref);
writeline(ResultsFile, Bufline);
end if;
end loop;
if (Passed = '1') then -- has passed
write(Bufline, string' ("GCD algorithm test has passed"));
writeline(ResultsFile, Bufline);
end if;
end process;
end architecture ALGORITHM;
Verilog algorithm
The Verilog model will also follow the same principles described in C.
A main difference is that Verilog cannot read decimal values from a file. The data read from a file can be:
1) reading using $readmemh or $readmemb and
2) storing in memory. The read data will be either in binary format or in hex. We will use the file:
"gcd_test_data_hex.txt"
Verilog algorithmic level model
module GCD_ALG;
parameter Width = 8;
reg [Width-1:0] A_in, B_in, A, B, Y, Y_Ref;
reg [Width-1:0] A_reg,B_reg,Swap;
parameter GCD_tests = 6;
integer N, M;
reg Passed, FailTime;
integer SimResults;
// Declare memory array for test data
// ----------------------------------
reg [Width-1:1] AB_Y_Ref_Arr[1:GCD_tests*3];
//----------------------------------
// Model GCD algorithm
//----------------------------------
always @(A or B)
begin: GCD
A = A_in;
B = B_in;
if (A != 0 && B != 0)
while (B != 0)
while (A >= B) begin
A = A - B;
Swap = A;
A = B;
B = Swap;
end
else
A = 0;
Y = A;
end
//------------------------------
// Test GCD algorithm
//-----------------------------
initial begin
// Load contents of
// "gcd_test_data.txt" into array.
$readmemh("gcd_test_data_hex.txt", AB_Y_Ref_Arr);
// Open simulation results file
SimResults = $fopen("gcd.simres");
Passed = 1;
/ Set to 0 if fails
for (N=1; N<=GCD_tests; N=N+1) begin
A_in = AB_Y_Ref_Arr[(N*3)+1];
B_in = AB_Y_Ref_Arr[(N*3)+2];
Y_Ref=AB_Y_Ref_Arr[(N*3)+3];
#TestPeriod
if (Y != Y_Ref) begin // has failed
Passed = 0;
$fdisplay (SimResults, " GCD Error:
A=%d B=%d Y=%d. Y should be %d", A_in, B_in, Y, Y_Ref);
end end
if (Passed == 1) // has passed
$fdisplay (SimResults, "GCD algorithm test has passed");
$fclose (SimResults);
$finish;
end
endmodule
Designing the model at RTL level in VHDL and Verilog
The model will have inputs and outputs.
Inputs: Clock, Reset_N and Load,
Output:Done.
When Load is logical 1, the input data is available at the output and are loaded in the separate registers, A_hold
and B_ hold.
When Done=1, the greatest common devisor was calculated.
The process will take a few clock periods.
The model is divided into 3 processes process (VHDL) and /always (Verilog)
I) first process/always LOAD_SWAP. It involves the use of two registers which operate as follows:
1) Reset_N = 0, A_hold and B_hold = zero.
2) When not 1) and Load = 1, the data in A and B is stored in A_hold and B_hold.
3) When not 1) or 2) and A_hold is smaller than B_hold, the values in A_hold and B_hold are switched,
4) When not 1), 2) or 3), A_hold is loaded with the same value. The value A_hold - B_hold, from the second
process/always statement, is loaded in B_hold.
II) the second process/always SUBTRACT_TEST.
The first if tests if A_hold is greater or equal to B_hold.
If so, the substraction A_hold – B_hold takes place, the result is stored in A_New which will be loaded in
B_hold on the next rising slope of the clock.
If A_hold is smaller than B_hold, the substraction does not take place, A_New will have the value B_hold,
the switch will be done after the next positive slope of the clock signal.
The second if – checks if B_hold is 0.
If so, the signal Done=1, the value A_ hold is loaded at the output Y with the help of a multiplexing function.
The problem is synthesized for a generic model with 8 bit signals.
In Verilog we set the parameter Width=8. There is no need for it to be separately instantiated before being
synthesized.
In VHDL – we use generic. The value is specified only when creating the instance.
VHDL RTL model
library IEEE;
use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;
entity GCD is
generic (Width: natural);
port (Clock,Reset,Load: in std_logic;
A,B: in unsigned(Width-1 downto 0);
Done: out std_logic;
Y: out unsigned(Width-1 downto 0));
end entity GCD;
architecture RTL of GCD is
signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0);
signal A_lessthan_B: std_logic;
begin
----------------------------------------------------
-- Load 2 input registers and ensure B_Hold < A_Hold
---------------------------------------------------
LOAD_SWAP: process (Clock)
begin
if rising_edge(Clock) then
if (Reset = '0') then
A_Hold <= (others => '0');
B_Hold <= (others => '0');
elsif (Load = '1') then
A_Hold <= A;
B_Hold <= B;
else if (A_lessthan_B = '1') then
A_Hold <= B_Hold;
B_Hold <= A_New;
else A_Hold <= A _New;
end if;
end if;
end process LOAD_SWAP;
SUBTRACT_TEST: process (A_Hold, B_Hold)
begin
-------------------------------------------------------
-- Subtract B_Hold from A_Hold if A_Hold >= B_Hold
------------------------------------------------------
if (A_Hold >= B_Hold) then
A_lessthan_B <= '0';
A_New <= A_Hold - B_Hold;
else
A_lessthan_B <= '1';
A_New <= A_Hold;
end if;
-------------------------------------------------
-- Greatest common divisor found if B_Hold = 0
-------------------------------------------------
if (B_Hold = (others => '0')) then
Done <= '1';
Y <= A_Hold;
else
Done <= '0';
Y <= (others => '0');
end if;
end process SUBTRACT_TEST;
end architecture RTL;
Verilog RTL model
module GCD (Clock, Reset, Load, A, B, Done,
Y);
parameter Width = 8;
input Clock, Reset, Load;
input [Width-1:0] A, B;
output Done;
output [Width-1:0] Y;
reg A_lessthan_B, Done;
reg [Width-1:0] A_New, A_Hold, B_Hold, Y;
//--------------------------------------------
---------
// Load 2 input registers and ensure B_Hold <
A_Hold
//--------------------------------------------
---------
always @(posedge Clock)
begin: LOAD_SWAP
if (Reset) begin
A_Hold = 0;
B_Hold = 0;
end
else if (Load) begin
A_Hold = A;
B_Hold = B;
end
else if (A_lessthan_B) begin
A_Hold = B_Hold;
B_Hold = A_New;
end
else
A_Hold = A_New;
end
always @(A_Hold or B_Hold)
begin: SUBTRACT_TEST
//--------------------------
------------------------
// Subtract B_Hold from
A_Hold if A_Hold >= B_Hold
//--------------------------
------------------------
if (A_Hold >= B_Hold) begin
A_lessthan_ B = 0;
A_New = A_Hold - B_Hold;
end
else begin
A_lessthan_B = 1;
A_New = A_Hold;
end
//--------------------------
--------------------
// Greatest common divisor
found if B_Hold = 0
//--------------------------
--------------------
if (B_Hold == 0) begin
Done = 1;
Y = A_Hold;
end
else begin
Done = 0;
Y = 0;
end
end
endmodule
Bibliography:
[1] Douglas J. Smith - VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in
VHDL, Verilog and C
[2] - http://www.vhdl-online.de/tutorial/englisch/t_13.htm
[3] - Accolade VHDL Reference Guide - http://www.acc-eda.com/vhdlref/
[4] Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 - Reconfigurable
Computing
[5] - Dr. Gilles SASSATELLI- Lecture on Reconfigurable Technologies, 2009
