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Hardware Description LanguageHardware Description LanguageUNIT 2

RTL H dCh t 2

2nd PartDigital Electronics

RTL Hardware Design by P. Chu

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Fall 2008

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Outline

Design by P. Chu

Outline

1 Overview on hardware description language1. Overview on hardware description language2. Basic VHDL Concept via an example3 VHDL in development flow3. VHDL in development flow

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1. Overview on hardware description 1. Overview on hardware description language

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Programming language RTL Hardware Design by P

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Programming language Design by P. Chu

• Can we use C or Java as HDL?• A computer programming languagep p g g g g▫ Semantics (“meaning”)▫ Syntax (“grammar”)

• Develop of a language▫ Study the characteristics of the underlying processes ▫ Develop syntactic constructs and their associated

semantics to model and express these characteristics.

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Traditional PL

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Traditional PL

• Modeled after a sequential process• Modeled after a sequential process▫ Operations performed in a sequential order

H l h ' thi ki t d l ▫ Help human's thinking process to develop an algorithm step by stepR bl th ti f b i t d l▫ Resemble the operation of a basic computer model

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HDL

Design by P. Chu

HDL

• Characteristics of digital hardware • Characteristics of digital hardware ▫ Connections of parts

C t ti▫ Concurrent operations▫ Concept of propagation delay and timing

h b d b• Characteristics cannot be captured by traditional PLstraditional PLs

• Require new languages: HDL

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Use of an HDL program

Design by P. Chu

Use of an HDL program

• Formal documentation• Formal documentation▫ Semantic and Syntax of an HDL are defined

rigorouslyrigorously• Input to a simulator▫ The simulator interprets HDL code and generates ▫ The simulator interprets HDL code and generates

responses accordingly• Input to a synthesizer• Input to a synthesizer▫ Takes a HDL program and realices the circuit

from the components of a given libraryfrom the components of a given library

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Modern HDL Design by P. Chu

• Capture characteristics of a digital circuit:▫ entity ▫ connectivity ▫ concurrency ▫ timing

• Cover description ▫ in Gate level and RT level▫ In structural view and behavioral view

• Highlights of modern HDL:RTL Hardware Design by P

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• Highlights of modern HDL:▫ Encapsulate the concepts of entity, connectivity,

concurrency and timing

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concurrency, and timing▫ Incorporate propagation delay and timing information▫ Consist of constructs for structural implementation Consist of constructs for structural implementation ▫ Incorporate constructs for behavioral description

(sequential execution of traditional PL)▫ Describe the operations and structures in gate level and

RT level.▫ Consist of constructs to support hierarchical design

process

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Two HDLs used today

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Two HDLs used today▫ VHDL and Verilog▫ VHDL and Verilog▫ Syntax and “appearance” of the two

l diff languages are very different ▫ Capabilities and scopes are quite similarp p q▫ Both are industrial standards and are

supported by most software toolssupported by most software tools

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VHDL

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VHDL▫ VHDL: VHSIC (Very High Speed Integrated VHDL: VHSIC (Very High Speed Integrated

Circuit) HDL▫ Initially sponsored by DoD as a hardware Initially sponsored by DoD as a hardware

documentation standard in early 80s▫ Transferred to IEEE and ratified it as IEEE

standard 1176 in 1987 (known as VHDL-87)▫ Major modification in ’93 (known as VHDL-93)j 93 ( 93)▫ Revised continuously

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IEEE Extensions

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IEEE Extensions▫ IEEE standard 1076.1 Analog and Mixed Signal g g

Extensions (VHDL-AMS)▫ IEEE standard 1076.2 VHDL Mathematical Packages▫ IEEE standard 1076 3 Synthesis PackagesIEEE standard 1076.3 Synthesis Packages▫ IEEE standard 1076.4 VHDL Initiative Towards ASIC

Libraries (VITAL)IEEE standard 1076 6 VHDL Register Transfer Level ▫ IEEE standard 1076.6 VHDL Register Transfer Level (RTL) Synthesis

▫ IEEE standard 1164 Multivalue Logic System for VHDL M d l I biliVHDL Model Interoperability

▫ IEEE standard 1029 VHDL Waveform and Vector Exchange to Support Design and Test Verification g pp g(WAVES)

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2. Basic VHDL Concept via an examplevia an example

RTL H dCh t 2 RTL Hardware Design by P. Chu

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Even parity detection circuitEven parity detection circuit

• Input: a(2), a(1), a(0)• output: even

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VHDL Listing 2 1

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VHDL Listing 2.1

Entity DeclarationInputsOutputs

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VHDL Code

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VHDL Code• Entity declarationEntity declaration▫ i/o ports (“outline” of the circuit)

• Architecture bodyy▫ Signal declaration▫ Each concurrent statement

Can be thought s a circuit partContains timing information

▫ Arch body can be thought as a “collection of parts”• What’s the difference between this and a C

program

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Conceptual interpretation

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Conceptual interpretation

VHDL Listing 2.2g

• Same entity declaration• Same entity declaration• Implicit δ-delay (delta delay)

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Structural description RTL Hardware Design by P

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Structural description• In structural view, a circuit is constructed by

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In structural view, a circuit is constructed by smaller parts.

• Structural description specifies the types of parts p p yp pand connections.

• Essentially a textual description of a schematic• Done by using “component” in VHDL▫ First declared (make known) ▫ Then instantiated (used)

ExampleExample

• Even detector using previously designed components (xor2 and not1)

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VHDL Listing 2 3RTL Hardware Design by P

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VHDL Listing 2.3 Design by P. Chu

Declaration

Instantiation

Somewhere in library RTL Hardware Design by P

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yDesign by P. Chu

“Behavioral” descriptionBehavioral description• No formal definition on “behavioral” in VHDL• VHDL “process”: a language construct to

encapsulate “sequential semantics”p q▫ The entire process is a concurrent statement▫ Syntax:y

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Listing 2.5 RTL Hardware Design by P

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Listing 2.5 Design by P. Chu

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Conceptual interpretation

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Conceptual interpretation

Listing 2 6RTL Hardware Design by P

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Listing 2.6 Design by P. Chu

TestbenchTestbench• a “virtual” experiment table▫ Circuit to be tested▫ Circuit to be tested▫ Input stimuli (e.g., function generator)▫ Output monitor (e.g., logic analyzer)p ( g , g y )

• e.g.,

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VHDL Listing 2.7 RTL Hardware Design by P

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VHDL Listing 2.7 Design by P. Chu

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Design by P. Chu

Configurationg• Multiple architecture bodies can be associated with an

i d l ientity declaration▫ Like IC chips and sockets

• VHDL configuration specifies the binding• VHDL configuration specifies the binding• E.g.,

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3 VHDL in development flow3. VHDL in development flowRTL H dCh t 2 RTL Hardware Design by P. Chu

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Scope of VHDL RTL Hardware Design by P

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Scope of VHDL Design by P. Chu

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Coding for synthesis

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Coding for synthesis

• “Execution” of VHDL codes• Execution of VHDL codes▫ Simulation:

Design “realized” in a virtual environment Design realized in a virtual environment (simulation software)All language constructs can be “realized”g g“realized” by a single CPU

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Coding for SynthesisDesign by P. Chu

▫ “SynthesisSynthesisDesign realized by hardware componentsMany VHDL constructs can be synthesized (e,g, file a y V co st ucts ca be sy t es ed (e,g, e operation, floating-point data type, division)Only small subset can be usedE.g., 10 additionsSyntactically correct code ≠ Synthesizable codeSynthesizable code ≠ Efficient codeSynthesis software only performs transformation

d l l h and local search

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• The course focuses on hardware, not VHDL (i e the “H” not “L” of HDL)

Design by P. Chu

(i.e., the H , not L of HDL)• Emphasis on coding for synthesis:▫ Code accurately describing the underlying ▫ Code accurately describing the underlying

hardware structure▫ Code providing adequate info to guide synthesis ▫ Code providing adequate info to guide synthesis

software to generate efficient implementation