ECS Group, TU Wien

Hardware Modeling

Hardware Description

Content of this course Hardware Specification Functional specification High Level Requirements Detailed Design Description

Realisation Hardware Description Hardware Implementation

Verification Review Formal verification Simulation

Hardware Description: Outline Design entry Levels of abstraction Schematic entry vs. text-based entry

VHDL History Motivation Range of application

One possible method to describe hardware

Y-Diagram (1)Behaviour of the circuit

Components inside the chip

Geometry of the chip

Y-Diagram (2)Behavior Structure

Geometry

system specification

CPU,memory

chips/board

System Level

B: Functionality and constraints

S: Partitioning into subsystems/processes

G: (Motherboard-) Layout

Y-Diagram (3)

algorithmsSubsystems (ALU),

bus systems

ICs/blocks

Algorithmic LevelBehavior Structure

Geometry

B: Operations and calculations

S: Scheduling and allocation

G: Chip-Layout

Y-Diagram (4)

register transfer

Register Transfer Level

Adder, Reg, MUX

macrocells

Behavior Structure

Geometry

B: Finite State Machines

S: Data and control paths

G: Refined chip layout

Y-Diagram (5)

boolean equations

standard-cells

Logic Level

and, or, flipflop

Behavior Structure

Geometry

B: Boolean functions

S: Gate-level Netlist

G: Position of standard cells

Y-Diagram (6)

Differential equations Transistors

Circuit Level

Mask

Behavior Structure

Geometry

B: Differential Equations

S: Transistor network

G: ASIC Mask

Y-Diagram (7)

Chip

• The three views describes the same system/chip

• The same system/chip can be defined on all levels of abstraction

Behavior Structure

Geometry⇒ Level of detail, information content

Hardware DescriptionBehavior Structure

Geometry

RTLLogic Level

Algoritmic Level

• State of the Art

while inputRead „Schilling“ Calulate Euro Display „Euro“

µP IO-Ctrl8 PS/2 Interface

Speicher16

RS232Interface

Y-TableSpeicher CPU IO

Control

System Level

Algorithmic Level

if A=`1` thenB:= B+1

else B:= B

end if

Register Transfer Level (RTL)

RAM Register

ALU

Counter

Logic Level

Circuit LeveldUdt

IC

dIdt

d2Idt2

R + L+=

Behavior Structure Geometry

D = NOT E

C = (D OR B) AND A

>1 &E

BC

A

Inputs : KeyboardOutput: Display Funktion: .....

IN

OUT

Trans-lator

INV

ORAND

IO-Ctrl

PS/2µP

RS232

REG

ALU

Counter

Hardware Description Languages

Verilog

Graphical Tools/Lang.

SystemC

VHDLVHDL

Very High Speed Integrated Circuit HDL

UML

ABEL

UDL/I

SysML

History of VHDL VHSIC ... Very High Speed ICVHDL ... VHSIC HDLIEEE ... Institute of Electrical and

Electronics Engineers

Motivation: Documentation

Documentation for :

• Complex systems

• Maintenance

• Reusability

• Different levels of abstraction

• Readable man-machine interface

Motivation: Data exchange

Data exchange between:

• Orderer and contractor

• Developers

• Tools

• Computing systems

Motivation: Complexity (1)

21%/Yr. Productivity growth rate

58%/Yr. Complexity growth rate

vs. Design Productivity Gap

Motivation: Complexity (2)

Intel 4004 (1971) Intel P4 (2001)• 2300 Transistors• 12 mm2 / 10µm• 108 kHz

• 42 Millionen Transistors• 217 mm2 / 0,18µm• 2 Ghz

Motivation: Complexity (3)

Trans. count ratio:

1: 18261

Testbench(VHDL)

Range application of VHDL

Speicher CPU IO

Control

System Level

Algorithmic Level

if A=`1` thenB:= B+1

else B:= B

end if

Register Transfer Level (RTL)

RAM Register

ALU

Counter

Logic Level

Circuit LeveldUdt

IC

dIdt

d2Idt2

R + L+=

Behavior Structure Geometry

D = NOT E

C = (D OR B) AND A

>1 &E

BC

A

Inputs : KeyboardOutput: Display Funktion: .....

IN

OUT

Trans-lator

INV

ORAND

µP IO-Ctrl8 PS/2 Interface

Speicher16

RS232Interface

IO-Ctrl

PS/2µP

RS232

REG

ALU

Counter

V H D L

while inputRead „Schilling“ Calulate Euro Display „Euro“

Testbench(VHDL)

Range application of VHDL

Speicher CPU IO

Control

System Level

Algorithmic Level

if A=`1` thenB:= B+1

else B:= B

end if

Register Transfer Level (RTL)

RAM Register

ALU

Counter

Logic Level

Circuit LeveldUdt

IC

dIdt

d2Idt2

R + L+=

Behavior Structure Geometry

D = NOT E

C = (D OR B) AND A

>1 &E

BC

A

Inputs : KeyboardOutput: Display Funktion: .....

IN

OUT

Trans-lator

INV

ORAND

µP IO-Ctrl8 PS/2 Interface

Speicher16

RS232Interface

IO-Ctrl

PS/2µP

RS232

REG

ALU

Counter

Generated by tools (Quartus, e.g.)

Generated by Tools

(Synplify, Synopsys)

V H D L

while inputRead „Schilling“ Calulate Euro Display „Euro“

Summary

• Hardware can be described from different view: Behavioral, Structural and Geometrical

• Hardware can be described on different Levels of Abstraction

• VHDL is one approach to describe hardware on RTL and Boolean Level