Hardware structures –Hardware structures –system bus,system bus,

internal (operational) memory.internal (operational) memory.

Piotr Mielecki Ph. D.Piotr Mielecki Ph. D.

Introduction to Computer SystemsIntroduction to Computer Systems (4)(4)

mielecki@wssk.wroc.pl

Piotr.Mielecki@pwr.wroc.pl

http://www.wssk.wroc.pl/~mielecki

1.1. System Bus concept and exampleSystem Bus concept and exampleimplementation.implementation.

The bus implemented in particular computer design for connecting The bus implemented in particular computer design for connecting its basic modules (not intended as widely used standard, like PCI, its basic modules (not intended as widely used standard, like PCI, AGP etc.) is usually called a AGP etc.) is usually called a System BusSystem Bus. .

The basic problem rests on the fact that usually The basic problem rests on the fact that usually the same data and the same data and address lines (contacts) of the CPU microcircuit are used to make address lines (contacts) of the CPU microcircuit are used to make connection with different devicesconnection with different devices. So the System Bus has to . So the System Bus has to separate separate form the CPU the devices which don’t take a part in particular form the CPU the devices which don’t take a part in particular connection (access cycle)connection (access cycle), enabling only those which are exchanging , enabling only those which are exchanging data right now.data right now.

The bus in hardware structure of computer consists of a set of wires which connect the CPU with other parts of computer (memory and Input / Output devices in von Neumann’s architecture based computer).

DEFINITION:

EEach implementation of the bus consists of ach implementation of the bus consists of 33 types of wires types of wires::

Address BusAddress Bus – set of – set of mm signals (usually named Asignals (usually named A00 – A – Am-1m-1) which pass ) which pass the binary address to the device accessed for the binary address to the device accessed for readread (RD) or (RD) or writewrite (WR) operation (address in physical memory or in Input / Output (WR) operation (address in physical memory or in Input / Output space). If the CPU has address bus of 16 bit length space). If the CPU has address bus of 16 bit length ((AA00 – A – A1515) it can ) it can address up to 2address up to 21616 = 65 536 different cells in memory, for example. = 65 536 different cells in memory, for example. The 32-bit address bus can address up to 4 GB (2The 32-bit address bus can address up to 4 GB (23232 = 4 294 967 296) = 4 294 967 296) different bytes if the basic word in memory has 1-byte length.different bytes if the basic word in memory has 1-byte length.

Data Bus Data Bus – set of – set of nn signals (D signals (D00 – D – Dn-1n-1) which can pass the binary value ) which can pass the binary value to or fromto or from the device accessed for the device accessed for readread or or writewrite operation (physical operation (physical memory or I/O port). The length of the Data Bus is usually (but not memory or I/O port). The length of the Data Bus is usually (but not always) equal to the basic machine word length of the particular CPU always) equal to the basic machine word length of the particular CPU (8, 16, 32, 64 bit for example) and determines the class of CPU (“8-(8, 16, 32, 64 bit for example) and determines the class of CPU (“8-bit CPU”, “64-bit CPU” etc.). The data signals are bit CPU”, “64-bit CPU” etc.). The data signals are bidirectionalbidirectional (inputs and outputs).(inputs and outputs).

Control BusControl Bus – set of logical signals used to drive particular devices – set of logical signals used to drive particular devices and access cycles like distinguishing between memory and I/O, and access cycles like distinguishing between memory and I/O, reading and writing etc. The System Clock signal (CLK) which reading and writing etc. The System Clock signal (CLK) which synchronizes all the devices is also a part of the Control Bus.synchronizes all the devices is also a part of the Control Bus.

Zilog Z-80 CPU (modification of Intel 8080) – example of CPU’s System Bus.Zilog Z-80 CPU (modification of Intel 8080) – example of CPU’s System Bus.

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

Vcc

GND

RESET

CLK

INT

NMI

WAIT

BUSRQ

M1

RFSH

HALT

BUSACK

MREQ

IOREQ

RDWR

303132333435363738394012345

1415128710913

11

29

26

6

16

17

24

25

27

28

18

23

19

20

2122

Z-80CPU

ADDRESS BUS

DATA BUS

CONTROL BUS

CONTROL BUS

(INPUTS)

(OUTPUTS)

To complete each data exchange cycle between the CPU and other To complete each data exchange cycle between the CPU and other device appropriate sequence of signals (“timing”) synchronized with device appropriate sequence of signals (“timing”) synchronized with CLK signal is needed. The control signals CLK signal is needed. The control signals ReadRead (RD), (RD), WriteWrite (WR) and (WR) and Memory RequestMemory Request (MREQ) of the Z-80 CPU (for example) drive the (MREQ) of the Z-80 CPU (for example) drive the attached memory circuits to enter read mode and complete the attached memory circuits to enter read mode and complete the Memory Read Memory Read access cycle or access cycle or Operation Code Fetch (M1)Operation Code Fetch (M1) cycle. cycle.

T1 T2 T3 T4 T1 T2 T3

M1 (FETCH) CYCLE MEMORY READ CYCLE

CLK

A0 – A15 PC

M1

R (refresh) Memory Address

MREQ

RD

D0 – D7 READING

RFSH

READING

Most important and/or interesting things seen on the diagram are:Most important and/or interesting things seen on the diagram are:

Control signalsControl signals in most of circuits used to build microcomputers are in most of circuits used to build microcomputers are active in “low” logical stateactive in “low” logical state (0 V). The signals MREQ and RD both have to (0 V). The signals MREQ and RD both have to be active to be active to read from memoryread from memory..

The The rising edge of the CLK pulserising edge of the CLK pulse causes the signals provided by the causes the signals provided by the memory circuit and seen on memory circuit and seen on Data BusData Bus (D (D00 – D – D77 lines) to be copied lines) to be copied (latched) to CPU’s internal data buffer register (see Lecture 3).(latched) to CPU’s internal data buffer register (see Lecture 3).

The lines DThe lines D00 – D – D77 are the CPU’s are the CPU’s inputs in reading cycleinputs in reading cycle, , the same lines the same lines are outputs in writing cyclesare outputs in writing cycles. When the CPU or other device attached to . When the CPU or other device attached to the bus doesn’t have any data to write or read, it keeps its data lines in the bus doesn’t have any data to write or read, it keeps its data lines in the logical “the logical “third statethird state” (also called the high-resistance state), which is ” (also called the high-resistance state), which is equivalent to electrically cut-off (R = ∞ Ω) from the external wires.equivalent to electrically cut-off (R = ∞ Ω) from the external wires.

The processors like Intel 8080 and Zilog Z-80 were designed to co-The processors like Intel 8080 and Zilog Z-80 were designed to co-operate with slow memory circuits, so they used to add entire CLK cycle operate with slow memory circuits, so they used to add entire CLK cycle (T2) between activation their MREQ and RD control signals and reading (T2) between activation their MREQ and RD control signals and reading the data lines Dthe data lines D00 – D – D77. It’s seen in both M1 and Memory Read cycles.. It’s seen in both M1 and Memory Read cycles.

Memory hardware can force the CPU to add additional “empty” CLK Memory hardware can force the CPU to add additional “empty” CLK cycles if memory circuits are not ready with data on Data Bus. It is cycles if memory circuits are not ready with data on Data Bus. It is possible with CPU’s possible with CPU’s WAITWAIT input. input.

During the M1 cycle (T3 and T4 CLK pulses) Z-80 CPU supports the During the M1 cycle (T3 and T4 CLK pulses) Z-80 CPU supports the RefreshRefresh cycle for dynamic RAM (Random Access Memory) integrated cycle for dynamic RAM (Random Access Memory) integrated circuits (circuits (today it’s not a common solutiontoday it’s not a common solution, the D-RAM modules have , the D-RAM modules have their own circuitry to do so). It is done by sending to 8 lower bytes of their own circuitry to do so). It is done by sending to 8 lower bytes of Address Bus (AAddress Bus (A00 – A – A77) the number of the entire raw in the RAM ) the number of the entire raw in the RAM structure and activating the structure and activating the RFSHRFSH control output. The short pulse of control output. The short pulse of MREQMREQ signal causes the dynamic RAM circuitry (physically organized in signal causes the dynamic RAM circuitry (physically organized in a different mode this time) to rewrite it’s contents in one raw of cells. a different mode this time) to rewrite it’s contents in one raw of cells. The CPU’s internal R register, which keeps the number of current raw The CPU’s internal R register, which keeps the number of current raw in D-RAM structure, is then incremented by 1 for another Refresh in D-RAM structure, is then incremented by 1 for another Refresh cycle.cycle.

The Memory Write CPU cycle looks in a bit different way. This time the The Memory Write CPU cycle looks in a bit different way. This time the WriteWrite (WR) control signal together with (WR) control signal together with MREQMREQ causes the memory causes the memory circuit (addressed by Address Bus lines Acircuit (addressed by Address Bus lines A00 – A – A1515) to read the data which ) to read the data which CPU wants to write. The falling or rising edge of the WR signal should be CPU wants to write. The falling or rising edge of the WR signal should be used by the memory circuit to latch the data from Data Bus.used by the memory circuit to latch the data from Data Bus.

T1 T2 T3

MEMORY WRITE CYCLE

CLK

A0 – A15 Memory Address

MREQ

WR

D0 – D7 DATA FOR WRITING

Finally we can say, that System Bus (and any other bus) is defined by Finally we can say, that System Bus (and any other bus) is defined by set of wires and sequences of control signalsset of wires and sequences of control signals which drive different which drive different hardware devices during data-exchange cycles.hardware devices during data-exchange cycles.

2. 2. The operational memory – hardwareThe operational memory – hardware implementationimplementation..

The The internal memoryinternal memory (“operational memory” or “primary level (“operational memory” or “primary level storage”) should be implemented as a linear array of binary words storage”) should be implemented as a linear array of binary words (bytes, for example) addressed by a unique binary addresses. So it (bytes, for example) addressed by a unique binary addresses. So it takes a part of “memory” in the von Neumann’s model of computer.takes a part of “memory” in the von Neumann’s model of computer.

To be compatible with the System Bus the memory circuitry should To be compatible with the System Bus the memory circuitry should havehave::

address inputs,address inputs,

data inputs / outputsdata inputs / outputs,,

some control inputs (sometimes outputs like WAIT alsosome control inputs (sometimes outputs like WAIT also)). .

In most of cases the set of control signals has to be passed trough In most of cases the set of control signals has to be passed trough additional logic circuits (decoders, logical gates etc.) to fit particular additional logic circuits (decoders, logical gates etc.) to fit particular CPU circuit with memory chips usedCPU circuit with memory chips used..

MEMORY CPU A0 – A15

D0 – D7

16

8

RD

WR

WAIT

MREQ

CLK CLK

RD

WR

WAIT

CS

System Clock

Simplified diagram of the Z-80 CPU attached to memory with System Bus.Simplified diagram of the Z-80 CPU attached to memory with System Bus.

From From technologicaltechnological point of view we should distinguish between several point of view we should distinguish between several types of memory circuits, for example:types of memory circuits, for example:

RAM (Random Access Memory)RAM (Random Access Memory) – the circuits that can be written or read. – the circuits that can be written or read. Von Neumann assigned entire memory as RAM. Most of RAM Von Neumann assigned entire memory as RAM. Most of RAM implementations are the electronic integrated circuits which looses their implementations are the electronic integrated circuits which looses their contents after power-off.contents after power-off.

SRAM (Static RAM)SRAM (Static RAM) – the RAM circuits which don’t need refresh cycle. – the RAM circuits which don’t need refresh cycle. They are much faster than Dynamic RAMs, but have much less level of They are much faster than Dynamic RAMs, but have much less level of integration. Today used first of all as cache buffers between CPU and integration. Today used first of all as cache buffers between CPU and DRAM.DRAM.

DRAM (Dynamic RAM)DRAM (Dynamic RAM) – RAM circuits of very high level of integration but – RAM circuits of very high level of integration but with very short time of “remembering” the data. They have to be with very short time of “remembering” the data. They have to be refreshed with special cycle provided by external generator (or CPU). The refreshed with special cycle provided by external generator (or CPU). The access time (speed) of standard DRAMs is much worse than in SRAM.access time (speed) of standard DRAMs is much worse than in SRAM.

SDRAM (Synchronous Dynamic RAM)SDRAM (Synchronous Dynamic RAM) – DRAM which has a synchronous – DRAM which has a synchronous interface, meaning that it interface, meaning that it waits for a clock signal before responding to waits for a clock signal before responding to its control inputsits control inputs (“normal” DRAMs have an asynchronous interface (“normal” DRAMs have an asynchronous interface which means that they react as quickly as possible to changes in which means that they react as quickly as possible to changes in control inputs like RD or WR). The CLK signal is used to drive an control inputs like RD or WR). The CLK signal is used to drive an internal sequential automat that internal sequential automat that pipelinespipelines incoming cycles. Pipelining incoming cycles. Pipelining means that means that the chip can accept a new access cycle before it has the chip can accept a new access cycle before it has finished processing the previous onefinished processing the previous one. In a pipelined write, the write . In a pipelined write, the write cycle can be immediately followed by another cycle without waiting for cycle can be immediately followed by another cycle without waiting for the data to be written to the memory array. In a pipelined read, the the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the requested data appears after a fixed number of clock pulses after the read instruction, at the same time additional access cycles can be sent read instruction, at the same time additional access cycles can be sent to memory.to memory.

DDR RAM (Double Data Rate RAM)DDR RAM (Double Data Rate RAM) – SDRAM which reads or writes two – SDRAM which reads or writes two words of data per clock cycle (one on rising edge, one on falling edge words of data per clock cycle (one on rising edge, one on falling edge of the CLK pulse).of the CLK pulse).

ROM (Read Only Memory)ROM (Read Only Memory) – the circuit which is written once (in the – the circuit which is written once (in the factory) and cannot be written with other data.factory) and cannot be written with other data.

PROM (Programmable ROM)PROM (Programmable ROM) – the ROM chip which can be programmed – the ROM chip which can be programmed by user (not inside the computer, with special device – programmer), by user (not inside the computer, with special device – programmer), but only once.but only once.

E-PROM (Erasable PROM)E-PROM (Erasable PROM) – the ROM which can be programmed and – the ROM which can be programmed and erased many times, but with external device (not inside the erased many times, but with external device (not inside the computer). Usually the ultra-violet (UV) lamp is the device which computer). Usually the ultra-violet (UV) lamp is the device which erases the contents of E-PROMerases the contents of E-PROM..

EE-PROM (Electrically Erasable PROM)EE-PROM (Electrically Erasable PROM) – ROM integrated circuit which – ROM integrated circuit which can be erased and programmed electrically (without UV lamp), but still can be erased and programmed electrically (without UV lamp), but still outside the computer.outside the computer.

NV-RAM (Non-volatile RAM)NV-RAM (Non-volatile RAM) – RAM memory which can preserve its – RAM memory which can preserve its contents after switching-off the power. In older constructions the contents after switching-off the power. In older constructions the battery was mounted inside or outside the NV-RAM integrated circuit. battery was mounted inside or outside the NV-RAM integrated circuit. Today the Today the flashflash technology makes it possible without the battery, but technology makes it possible without the battery, but we are distinguishing between NV-RAMs and we are distinguishing between NV-RAMs and flashflash memory making memory making different use – different use – flashflash technology is more suitable for large mass storage technology is more suitable for large mass storage instead of magnetic disks (SSD – Solid State Disk).instead of magnetic disks (SSD – Solid State Disk).

3. The operational memory – more3. The operational memory – more advanced organizations.advanced organizations.

In most of today’s computers the operational memory is not organized In most of today’s computers the operational memory is not organized exactly according to von Neumann’s concept. One of the first well-exactly according to von Neumann’s concept. One of the first well-known modifications was the known modifications was the segmentationsegmentation of the physical memory of the physical memory used by Intel in 16-bit processors 8086 and 8088 (introduced in first used by Intel in 16-bit processors 8086 and 8088 (introduced in first IBM-PC and XT in mid-1980-ties), now known as a “real mode” IBM-PC and XT in mid-1980-ties), now known as a “real mode” addressing in today’s Intel CPUs. addressing in today’s Intel CPUs. The idea of segmentation came from The idea of segmentation came from the different roles that parts of memory can playthe different roles that parts of memory can play::

The code of programThe code of program is read-only in most of cases and the CPU is read-only in most of cases and the CPU processes it instruction after instruction (with branches sometimes).processes it instruction after instruction (with branches sometimes).

The data processed The data processed (simple variables, arrays etc.) is read and written (simple variables, arrays etc.) is read and written not sequentially rather (variables are located in different addresses).not sequentially rather (variables are located in different addresses).

The stack The stack processed with CPU’s PUSH and POP operations is used in processed with CPU’s PUSH and POP operations is used in a different way than “normal” data area (we need to PUSH a different way than “normal” data area (we need to PUSH something to the stack before we can POP it back). But the stack something to the stack before we can POP it back). But the stack plays very important part in the execution of the program, for plays very important part in the execution of the program, for example:example:

the return address is PUSHed on the stack before calling the the return address is PUSHed on the stack before calling the subroutine and POPed from the stack on return from subroutinesubroutine and POPed from the stack on return from subroutine,,

the parameters for the called subroutine are PUSHed to the the parameters for the called subroutine are PUSHed to the stack by calling program and then POPed by subroutine,stack by calling program and then POPed by subroutine,

local (“automatic”) variables declared inside the subroutine are local (“automatic”) variables declared inside the subroutine are usually allocated on the stack.usually allocated on the stack.

Intel’s designers assumed that up to 4 different segments of memory Intel’s designers assumed that up to 4 different segments of memory can be used by program at the same time:can be used by program at the same time:

Code Segment Code Segment only for instructions (please notice that it corresponds only for instructions (please notice that it corresponds with the Harvard Architecture concept),with the Harvard Architecture concept),

Stack SegmentStack Segment only for (system or application) stack only for (system or application) stack,,

Data SegmentData Segment for global variables and large blocks of memory (not for global variables and large blocks of memory (not “automatic”),“automatic”),

Extra SegmentExtra Segment as the additional data segment as the additional data segment..

According to this the processor has four 16-bit According to this the processor has four 16-bit segment registerssegment registers to to support addressing in these independent segments:support addressing in these independent segments:

CSCS pointing to the Code Segment, pointing to the Code Segment,

SSSS pointing to the Stack Segment pointing to the Stack Segment,,

DSDS pointing to the Data Segment pointing to the Data Segment,,

ESES pointing to the Extra Segment. pointing to the Extra Segment.

The Address Bus in these processors was The Address Bus in these processors was 20-bit length20-bit length (could address (could address up to 1 MB of memory). The address itself was not quite up to 1 MB of memory). The address itself was not quite linearlinear. It was . It was calculated in each segment as the sum of two 16-bit values (calculated in each segment as the sum of two 16-bit values (segmentsegment + + displacementdisplacement) with 4-bit offset) with 4-bit offset::

s s s s s s s s s s s s s s s s

d d d d d d d d d d d d d d d d

a a a a a a a a a a a a a a a a a a a a

+

SEGMENT:

DISPLACEMENT:

20-bit physical address:

CPU

Segment

Displacement

Memory

64 kB segment

To address the current instruction in the program CPU must have To address the current instruction in the program CPU must have appropriate value in the CS register and in the dedicated appropriate value in the CS register and in the dedicated index registerindex register, , responsible for displacement in CS. This register is called responsible for displacement in CS. This register is called Instruction Instruction Pointer (IP)Pointer (IP) and it’s value is added to value of CS in the way shown and it’s value is added to value of CS in the way shown above. After each instruction cycle the value of IP is incremented by the above. After each instruction cycle the value of IP is incremented by the length of instruction code. Stack segment is addressed by SS segment length of instruction code. Stack segment is addressed by SS segment register and the displacement within this segment is pointed by index register and the displacement within this segment is pointed by index register Stack Pointer (SP) etc.register Stack Pointer (SP) etc.

This implementation of segmented memory (This implementation of segmented memory (only up to 16 fully only up to 16 fully separated, 64 kB segments was possibleseparated, 64 kB segments was possible) was too poor to support ) was too poor to support multitasking operation system with several programs loaded into multitasking operation system with several programs loaded into memory at the same time (although the CPM/86 or Concurrent DOS memory at the same time (although the CPM/86 or Concurrent DOS were designed, they were never widely used), so the MS-DOS was were designed, they were never widely used), so the MS-DOS was pure non-multitasking system.pure non-multitasking system.

First truly multitasking operating systems (OS/2, MS-Windows 3.0) First truly multitasking operating systems (OS/2, MS-Windows 3.0) were implemented on IBM-AT machines with Intel 80286 and newer were implemented on IBM-AT machines with Intel 80286 and newer processors, which could support memory in “processors, which could support memory in “virtualvirtual” (or “protected”) ” (or “protected”) mode mode by more advanced hardware mechanismsby more advanced hardware mechanisms..

44. Virtual memory – basic concepts.. Virtual memory – basic concepts.

The concept of virtual memory assumes that the application can “see” the memory space much larger than physical memory installed in the computer. Using the technique called pagination the operating system, supported by some hardware solutions implemented in CPU, can map the desired, constant length (4096 bytes for example) block (called “page”) of this huge, virtual space into a block of physical memory (called “frame”).

Page 0

Page 1

Page 2

Page 3

Logical (virtual) memory

1

4

3

?

Page Table

Page ?

Page 0

Page 2

Page 1

Frame 0:

Frame 1:

Frame 3:

Frame 4:

0:

1:

2:

3: 0

1

1

1

Frame No valid

Physical memory

Page 4 ? 4: 0

The idea of paginated virtual memory supported by Page Table.The idea of paginated virtual memory supported by Page Table.

CPU P D

Logical (virtual) address

F

F D

Page Table

Physical memoryPhysical address

Page No Frame No

Calculating of the physical address in paginated virtual memory.Calculating of the physical address in paginated virtual memory.

The CPU has the hardware mechanism which can detect, whether a The CPU has the hardware mechanism which can detect, whether a desired desired pagepage of virtual memory is present somewhere in the physical of virtual memory is present somewhere in the physical RAM (in any RAM (in any frameframe) or not (support for ) or not (support for validvalid flag in the Page Table flag in the Page Table record, for example). record, for example).

If not (If not (validvalid flag set to 0), CPU rises an internal interrupt flag set to 0), CPU rises an internal interrupt (exception) which starts system routine to find at last one free (exception) which starts system routine to find at last one free frame in RAM and reload the desired page from the swap area frame in RAM and reload the desired page from the swap area (usually in the mass storage).(usually in the mass storage).

If the free frame can’t be foundIf the free frame can’t be found,, system must choose one of the system must choose one of the used frames, write it’s contents (page) to the swap area (if the used frames, write it’s contents (page) to the swap area (if the frame was modified since last loading from swap – the dirty flag frame was modified since last loading from swap – the dirty flag is often applied in the Page Table record to mark this) and then is often applied in the Page Table record to mark this) and then replace it with the desired page.replace it with the desired page.

In the operation systems which use the paginated virtual memory In the operation systems which use the paginated virtual memory (practically all today’s multitasking systems) swap area is (practically all today’s multitasking systems) swap area is implemented as the special file (Windows) or the separated disk implemented as the special file (Windows) or the separated disk partition (Linux, UNIX etc.). The swap operation takes much time and partition (Linux, UNIX etc.). The swap operation takes much time and makes the access to memory much slower than normal (“real-makes the access to memory much slower than normal (“real-mode”) access cycle to physical memory. To avoid this problem (to mode”) access cycle to physical memory. To avoid this problem (to minimize the number of swapping operations) advanced algorithms minimize the number of swapping operations) advanced algorithms are implemented in operating systems for managing the pages.are implemented in operating systems for managing the pages.

Another problem is the Another problem is the length of the Page Tablelength of the Page Table. Normally the page . Normally the page is a segment of memory 4 kB (4096 bytes) long. The 1 GB memory is a segment of memory 4 kB (4096 bytes) long. The 1 GB memory (1 073 741 824 bytes) should then be divided into 262 144 pages (or (1 073 741 824 bytes) should then be divided into 262 144 pages (or frames). Such a number of records in the Page Table would also take frames). Such a number of records in the Page Table would also take the space in memory, of course. To overcome this problem Page the space in memory, of course. To overcome this problem Page Tables are implemented not as single, constant-length arrays but as Tables are implemented not as single, constant-length arrays but as the lists or multilevel tables rather (Intel processors 80386 and the lists or multilevel tables rather (Intel processors 80386 and newer, for example). newer, for example).