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HCAL FIT 2002
HCAL Data ConcentratorHCAL Data ConcentratorStatus ReportStatus Report
Gueorgui Antchev, Eric Hazen, Jim Rohlf, Shouxiang Wu
Boston University
7-9 Feb 2002 CMS HCAL -- E. Hazen 2
HCAL FIT 2002
DCC Engineering StatusDCC Engineering Status
• Two prototype boards working
• Successful transfer of simulatedHTR data to VME “spy” buffer at full PCI speeds
• Simple event builder working – FPGA coding for more advanced version underway
7-9 Feb 2002 CMS HCAL -- E. Hazen 3
HCAL FIT 2002
DCC DCC DemonstratorDemonstrator
Data Concentrator Logic PMC
PCI
PCI
PCI33/32
33/64
33/32
to CPU
DCCFPGA
UniversePCI-VMEBridge
S-Link (64) LSC
SDRAM
TTCRx
One 3-channel receiverOn PMC Adapter
PCI InterfacesNot workingDue to layoutError…
Working since Fall
Used for Source Test
Development Finished
7-9 Feb 2002 CMS HCAL -- E. Hazen 4
HCAL FIT 2002
DCC DCC DemonstratorDemonstrator
Spare PMC Sitefor Testing
DCC Logic Board
S-Link LSC(Transmitter)
TTCRxLVDS SerialLink Receiver
7-9 Feb 2002 CMS HCAL -- E. Hazen 5
HCAL FIT 2002
DCC DCC PrototypePrototypePC-MIP Mezzanine Cards3 Channel Link Receivers
Dat
a fr
om
HT
R M
od
ule
s
Data Concentrator Logic PMC
PCI
PCI
PCI33/32
33/64
33/32
to RUI
DCCFPGA
UniversePCI-VMEBridge
S-Link (64) LSC
SDRAM
TTCRx Overflow WarningFast Busy
To TTS
7-9 Feb 2002 CMS HCAL -- E. Hazen 6
HCAL FIT 2002
DCC – Final ConfigurationDCC – Final Configuration
TriggerS-LINK
DAQS-LINK
FPGA
DCC LogicMezzanine Card
Spare StandardPMC Site
(33MHz 64 bit)
3x LinkReceiver
TTCRx
FE
Dat
a fr
om H
TR
Car
ds
(LV
DS
Ser
ial) V
ME
9Ux400 VME Motherboard (Design ~Frozen)
Proposed TransitionModule
FastTiming/Control
235 pin 2mmConnector
7-9 Feb 2002 CMS HCAL -- E. Hazen 7
HCAL FIT 2002
DCC Logic BoardDCC Logic Board
DCC Logic Board
TTCrx
PCI 1
PCI 2
PCI 3
XC2V1000 S-Link
DDR SDRAM
Flash JTAG
7-9 Feb 2002 CMS HCAL -- E. Hazen 8
HCAL FIT 2002
DCC Xilinx ChipDCC Xilinx Chip
Port1 Port1 FIFO4KB
16bit/66MHz
Port2 Port2 FIFO4KB
TTCrx
Contr.
TTCrx FIFO4KB
DAQ FIFOWrite 4KB
Trig FIFO32KB
SPY FIFO8KB
Trig S-LINK
Port
Port 3
EVENTBUILDER
DDRSDRAMcontrol
Write PORT
Read PORT
32bit/128MHz
Arbiter
32
32DAQ FIFO Write
Port 3 Write
DAQ FIFORead 4KB
DAQ FIFO Write
XILINX -XC2V1000
LVDS Fast Monitoring
PCI1ACEX
32bit/33MHz
PCI2ACEX
32bit/33MHz
TTCrxboard
36bit/128MHz
TTCF out
32bit
PCI3ACEX
32bit/33MHz
Trig S-LINK
32bit/128MHz
Port 3 FIFO Read 16words
Port 3 FIFO Write 16words
8MBDDR
SDRAM
DAQ FIFO Read
Port 3 Read
DAQ FIFO Read
Port 3 Read
Port 3 Write
DAQS-LINK
MainS-LINK
Port
64bit/128MHz
32bit/128MHz
32bit/66MHz
16bit/66MHz
32bit/33MHz
Address/Contr.
64bit/128MHz
32bit/128MHz
1Mx8FLASH
JTAG
XILINXConfig.
Monitor FIFO4KB
Complete?
Preliminary ?
To be done
7-9 Feb 2002 CMS HCAL -- E. Hazen 9
HCAL FIT 2002
DCC Logic StatusDCC Logic Status
• Complete data path working
• PCI 1/2 masters working
• Event builder:– Preliminary version which just glues together HTR
data as-is to form events
• DDR SDRAM (1Gbyte/sec) interface– Dual-port logic for DAQ FIFO and VME Spy FIFO– Working; identical logic in use on D0 STT
• Simple VME interface for control/spy
7-9 Feb 2002 CMS HCAL -- E. Hazen 10
HCAL FIT 2002
DCC DCC Prototype Prototype PlansPlans
• Short-term goal: bandwidth test– Currently 9 clocks PCI overhead per event
For 100 byte events (typical) we get 240 Mbytes/s– Further testing/optimization underway
• Finish event builder– Need to settle HTRDCC and DCCFED formats
• Implement monitoring– What do we need to monitor? Lots of FPGA gates available
• Implement trigger S-Link output• Test TTCRx input• Integrate with HTR Prototype• Use for test beam
7-9 Feb 2002 CMS HCAL -- E. Hazen 11
HCAL FIT 2002
DCC DCC ProductionProduction Design Design
• One more logic board prototype:– Transition module for two S-Links– TTC Fanout input– Final “fast monitoring/status” outputs
• Overall Status:– Motherboard and Link Receiver design done
• Production purchase soon (this year!) ~ $50k each
– Logic board design could in principle be done by this summer, but would like to delay production as long as possible (from an engineering standpoint)
• Production cost also ~ $50k
– S-Link Transition module is NEW HARDWARE• No formal cost estimate, but should easily be funded by cost
savings in remainder of DCC
7-9 Feb 2002 CMS HCAL -- E. Hazen 12
HCAL FIT 2002
Lehman 2001 ScheduleLehman 2001 Schedule
CERN testbeam
CY2001 CY2002 CY2003 CY2004
Full scope
Priorities:
1. Full
channel
count
2. Fully
Operational
3. Testbeam
May ‘02
Final
Prototype
stage
Complete
Sept ‘02
– Begins:
Fall 2002
– Duration
4-6 months
– Completed:
Spring ‘03
Begins:
- ASAP after
Mar ’03
- No later than
Sep ‘03
Co
nti
ng
en
cy
Limited scope
Priorities:
1. Functional test of
requirements
- Integration now thru
summer ‘01
2. Ready for FNAL source calibration run
- August ‘01
CY2000
Demonstrator and Calibration TaskDemonstrator and Calibration Task
PrototypePrototype
Q2 Q3
FINALFINAL
Q1 Q2
ProductionProduction
Q3 Q4
FNAL source calibration
CERN SX5 and Alcove
InstallationInstallation
Are we in trouble? Maybe… = new estimate