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Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl...

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Hello, and welcome to this presentation of the ARM® Cortex® -M4 Core. 1
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Page 1: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

Hello, and welcome to this presentation of the ARM® Cortex® -M4 Core.

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Page 2: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

In addition to the main Cortex® -M7 CPU, the STM32H747/H757 and STM32H745/H755 microcontrollers integrate a Cortex® -M4 core in order to benefit from the powerful performance of the 32-bit processor architecture and particularly of the high level of deterministic processing.

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Page 3: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

Based on the ARM Cortex-M4 core, the STM32H7 series doubles the DSP capability of a single cycle DSP MAC for data processing and the single-precision FPU performance. In addition to the computation capability offered by the ARM® Cortex® -M7 core, the STM32H7 offers more control performance and enhanced execution determinism.

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Page 4: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

Many application domains can benefit from the dual-core architecture of the STM32H745/755/747/757 devices.

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Page 5: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

The Cortex®-M4 in the STM32H7 microcontroller offers support for 8 independent memory regions, with independent configurable attributes for:- Access permission: read/write allowed or not in privileged/unprivileged mode,- Execution permission: executable region or region prohibited for instruction fetch,- And cache policies that affect ART accelerator instruction cache behavior

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Page 6: Hello, and welcome to this presentation of the ARM® Cortex® … · 2021. 4. 15. · GOrtex-lVl compatiDlllty Forget traditional 8/16/32-bit classifications Seamless architecture

For more details, please visit the ARM website on which you can find all information about the Cortex-M4 core.

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