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1Chapter 13. SoC Design FlowChapter 13. SoC Design Flow
2OutlineOutline
Design flow for HF ICs
Examples of mm-wave ICs
3Top-down design flow for mm-wave SoCsTop-down design flow for mm-wave SoCs
System level specification, high-level modelSymbol, I/O, layout placeholder
Block level specificationhigh-level modelSymbol, I/O, layout placeholder
Transistor-level schematic design of basic cellshigh-level model
Transistor layout and extraction
System layout, extraction, Simulation, verification
Block level layout, extractionand simulation, verification
Basic cell inductor design, Inductor modelCell layout, simulation after extraction
SYSTEM level
Block (sub-block) level
Cell level
Design flow for HF ICs in nanoscale CMOS Design flow for HF ICs in nanoscale CMOS Check MOSFET model for sanity:
peak fT current density = 0.3mA/m ... 0.4 mA/m
Add RG and check fMAX, NFMIN and JOPT = 0.12-0.15 mA/m
Transistor/varactor cell optimization: Wf to balance RS, RG and
minimize Cgd and other parasitics. Fix Wf and vary just Nf.
Schematic level design with RG added to MOSFET digital model
Transistor(cascode,CMOS inverter) layout optimization: choice of metal stack on drain and source depending on: CS, CG, CD, cascode, CMOS inv
monitor fMAX, NFMIN, gain
Parasitic resistance seems to be the killer in 65nm and beyond
Design flow for HF ICs in nanoscale CMOS (ii)Design flow for HF ICs in nanoscale CMOS (ii)
Include RC-extracted transistor(cascode/CMOS inv) layout in schematic (expect significant > 20% performance degradation)
Design inductors and interconnect in EM simulator based on schematic-level design with extracted transistors and pad capacitance
Add metal ground and power mesh to cell and RC-extract cell (without inductors)
Add inductor and interconnect models to schematic of RC-extracted cell
Add interconnect modelled in ASITIC between cells
Example: Hierarchical breakout of cell Example: Hierarchical breakout of cell for parasitic extractionfor parasitic extraction
Minimize cell layout footprint to reduce capacitance
Extract cell RC
Model inductors and long interconnect in ASITIC
330
VDD
= 1 V
1 nH
Q1 Q2 Q3 Q4
1 nH
330
CLK
DATA
OUT
HVTHVT
LVT LVT
330
VDD
= 1 V
Q1
Q2
Q3 Q4
330
CLK
DATA
OUT
HVTHVT
LVT LVT
Layout IssuesLayout Issues
Specific to mm-waves:
For performance: gate finger width in LNA/VCO
For all applications using nano-scale CMOS:
For manufacturability (antenna rules, OPC)
For variability (strain, stress, and process variation)
Diff. pair layout in nano-CMOS technologiesDiff. pair layout in nano-CMOS technologies
Transistors share the same well and are interspersed
symmetrically to minimize impact of process variation
All fingers have the same orientation, Wf, L, to avoid
photolithography problems and strain variation
Dummy gates are placed on each side to ensure L uniformity, ease
photolithographical phase correction, and reduce impact of strain
variation
S D1 S D2 S D2 S D1 S
G1
Dum
my
Dum
my
G1
G2
G2
G2
G2
G1
G1
CMOS Latch, Selector, and Gilbert Cell LayoutCMOS Latch, Selector, and Gilbert Cell Layout
330
VDD
= 1 V
1 nH
Q1 Q2 Q3 Q4
1 nH
330
CLK
DATA
OUT
HVTHVT
LVT LVT
S D1 S D2 S D2 S D1 S
G1
Dum
my
Dum
my
G1
G2
G2
G2
G2
G1
G1
S D1 S D2 S D2 S D1 S
G1
Dum
my
Dum
my
G1
G2
G2
G2
G2
G1
G1
S D1 S D2 S D2 S D1 S
G1
Dum
my
Dum
my
G1
G2
G2
G2
G2
G1
G1
DUMMY DUMMY
HVT Pair
LVT QUAD
R1
R1
R1
R2
R2
R2R2R1
Colpitts VCO Layout Colpitts VCO Layout
Components are placed as
close as possible to each
other
Merged varactor pair with
shared n-well
Transistor fingers narrow
and contacted on both
sides (not shown)
Dummy gates on side to
minimize variability due to
STI-induced strain
C1 C2
C2C1
Cross-Coupled VCO LayoutCross-Coupled VCO Layout(K. Tang, et al CSICS-06)(K. Tang, et al CSICS-06)
Merged cross-coupled and buffer pair to minimize interconnect capacitance
Bias and ground distribution and decouplingBias and ground distribution and decoupling
Fine ground mesh with grounded substrate taps throughout the circuit
At least two metals shunted together on ground mesh
Distributed de-coupling of power supply mesh over ground mesh
Local MIM (0.5pF - 1pF) de-coupling to ground if available
Careful with MOM caps to ensure high Q
45 degree angles no longer allowed in 45nm
Bias Distribution Bias Distribution (E. Laskin, ISSCC-08)(E. Laskin, ISSCC-08)
Metal mesh distributes ground, VDD, bias to all cells Substrate contacts, distributed decoupling, low R, L Meets all density rules
Signal distribution : t-line groundplane lossSignal distribution : t-line groundplane loss
7.5 m
2 m
5 m
3 m
8.2 m
1 m
5 m
3 m
Local supply distribution and de-couplingLocal supply distribution and de-coupling
A
B
Bias de-coupling in 100-GHz transceiverBias de-coupling in 100-GHz transceiver
Signal and block-to-block isolation strategiesSignal and block-to-block isolation strategies
SILICON SUBSTRATE: p-
Shielded bias/controlline
p+ p+p+ p+p+ p+p+ p+p+ p+p+ p+p+ p+p+ p+p+ p+p+ p+ p+ p+p+ p+p+ p+p+ p+ p+
mm-wave GND GND
Mm-wave transceiver examplesMm-wave transceiver examples
60-GHz CMOS and SiGe BiCMOS wireless phased arrays
77-GHz SiGe BiCMOS automotive radar transceiver
70-80 GHz SiGe BiCMOS active imaging array with digital
beamforming
140 to 170-GHz SiGe BiCMOS sensor transceivers with on-
die BIST and antennas
60-GHz 1.5-5 Gb/s wireless links60-GHz 1.5-5 Gb/s wireless links
SiGe BiCMOS 60-GHz phased array receiverSiGe BiCMOS 60-GHz phased array receiver
SiGe BiCMOS 60-GHz phased array receiverSiGe BiCMOS 60-GHz phased array receiver
SiGe BiCMOS 60-GHz phased array transmitterSiGe BiCMOS 60-GHz phased array transmitter
65-nm CMOS 60-GHz receiver phased array65-nm CMOS 60-GHz receiver phased array
65-nm CMOS 60-GHz receiver phased array65-nm CMOS 60-GHz receiver phased array
77-GHz Automotive Radar77-GHz Automotive Radar[5]
W-Band active imaging array with digital W-Band active imaging array with digital beamformingbeamforming
[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]
[7]
Antenna array clustersAntenna array clusters
[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]
[7]
Digital beamforming array conceptDigital beamforming array concept
[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]
Blcok diagram of single arrayBlcok diagram of single array
[S.S. Ahmed et al, IEEE Microwave Magazine October 2012]
RX and TX array elementsRX and TX array elements
[7]
Differential LNA with ESD protectionDifferential LNA with ESD protection
Chip packagingChip packaging
Push-push 150-170GHz Doppler transceiverPush-push 150-170GHz Doppler transceiver
/128
IF2 OUT
IF1 OUT
PLLfREF
578-664MHz
AM-MOD
TXPD
148-170GHz
74-85GHz
LNA
LNA
TXAMP
LOAMP
LOAMP
LOAMP
TX ANT
RX1
RX2
[28]
Monostatic 120/150 GHz distance sensorsMonostatic 120/150 GHz distance sensors
890 mW with both prescalers on from1.8V and 1.2V supplies
[I. Sarkas et al.CSICS 2012]
Layout and performance summaryLayout and performance summary2.6mm2.3mm
130nm SiGe BiCMOS technology,
HBT fT/fMAX= 230/280 GHz
Tuning range 143-152 GHz
NF-6 dBm
PN < -83 dBc/Hz at 1MHz
PDC = 800 mW
Coupler with detectorsCoupler with detectors
Coupler with detectors: Linearity Coupler with detectors: Linearity
Digital Tuner StatesDigital Tuner States
0.2 0.5 1.0 2.0 5.0
-0.2j
0.2j
-0.5j
0.5j
-1.0j
1.0j
-2.0j
2.0j
-5.0j
5.0j
122 GHz 145 GHz
0.2 0.5 1.0 2.0 5.0
-0.2j
0.2j
-0.5j
0.5j
-1.0j
1.0j
-2.0j
2.0j
-5.0j
5.0j
145 GHz fundamental frequency VCO145 GHz fundamental frequency VCO
39
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4142
143
144
145
146
147
148
149
150
151
152
Coarse = 1.4V
Coarse = 0.8V
Coarse = 0VO
scill
atio
n Fr
eque
ncy
(GH
z)
Fine Control (V)
143-152 GHz tuning rangePN=-103 dBc/Hz @10MHz offset
PDC = 72 mW
Measured output powerMeasured output power
40
144 145 146 147 148 149 150 151 152 153-14-13-12-11-10
-9-8-7-6-5-4-3
Antenna port open
TX detector thru output- Antenna port terminated
Antenna port (after 6dB coupler)
TX P
ower
(dB
m)
Frequency (GHz)Power at antenna port measured with ELVA power sensorOn-chip and external measurements track very well
Receiver schematicsReceiver schematics
Receiver Gain and Noise FigureReceiver Gain and Noise Figure
42
142 143 144 145 146 147 148 149 150 151 152 1538
9
10
11
12
13
14
15
16
Gain
NF
Gai
n - D
SB
Noi
se F
igur
e (d
B)
LO Frequency (GHz)
13-15 dB gain, 23 dB of gain control in LNALow noise figure: 8.5-10.5dB
Antenna and die in package Antenna and die in package
43
QFN package with
bondwire transition to
antenna on alumina
Courtesy of Robert Bosch GmbH, Karlsruhe Institute of Technology and EU SUCCESS project partners
120-GHz Distance Sensor120-GHz Distance Sensor
[I. Sarkas et al. Trans. MTT, March 2012]
1.2/1.8V, PD=0.9W
NF = 10 dBRX Gain = 12 dBPN= -100 dBc/Hz
Psat > 3 dBm
Layout and PackagingLayout and Packaging
Chip: 2.2mm2.6mm Package: 7mmmm
130-nm BiCMOS9MW: SiGe HBT fT= 230 GHz, fMAX = 280 GHz
Dr. J. Hasch
SummarySummaryInductors and transformers are scalable to at least 200 GHz
Accurate modelling of passives is as critical as transistor models
Transistor layout is critical to nanoscale CMOS circuit
performance
Layout parasitics can degrade CMOS IC performance by as
much as one technology node
HF SoC performance critically dependent on
supply distribution and de-coupling strategies
Signal and block-to-block isolation strategies
Examples of mm-wave ICs above 60 GHz
TX/RX PackagingTX/RX Packaging
Slide 1OutlineSlide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Layout Issues Colpitts VCOLayout Issues cross-coupled VCOSlide 12Bias DistributionSlide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38145 GHz Fundamental Frequency VCOOutput PowerSlide 41Receiver Gain and Noise FigureLow Cost Packaging 145 GHz Solution Slide 44Slide 45Slide 46Slide 47