METAL OXIDE SEMICONDUCTOR

(MOS) DEVICES

Term Paper Topic:

Hafnium-based High-K Gate Dielectrics

AUTHOR

KYAWTHETLATT

2

Content

1. High-k Gate Dielectric introduction 3

2. Brief history of high-k dielectric development 4

3. Requirements of High-K Oxides 5

3.1. K Value, Band Gap and Band offset 5

3.2. Thermal Stability 6

3.3. Crystallization Temperature 7

3.4. Interface Quality 7

3.5. Defects 8

4. Latest Development in Hf-Based High-k Oxides 9

4.1. Doping of Hf-Based High-k Oxides 9

4.2. Silicon Doped Hf-Based High-k Oxides 10

4.3. Aluminum Doped Hf-Based High-k Oxides 10

4.4. Tantalum Doped Hf-Based High-k Oxides 13

4.5. Lanthanum Doped Hf-Based High-k Oxides 16

5. Conclusion 18

6. References 19

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Hafnium-based High-k Gate Dielectric

1. Introduction

Among the three main components of the transistor – gate stack, source/drain, and channel length;

gate stack has been the most sophisticated and sensitive part for it performance, yield and reliability.

From the performance perspective, scaling of silicon dioxide dielectric is an effective approach to

enhance transistor performance in MOSFET. Reduction thickness of silicon dioxide gate dielectric

has increased numbers of transistors per unit area and higher performance speed at lower cost. As

per today sub-45nm technology node, the effective oxide thickness (EOT) of the silicon dioxide

dielectric are required to be smaller than 1nm, which corresponding to about 3 monolayers

thickness. While it may be feasible to make silicon dioxide thinner but direct tunneling

compromises their ability to remain an insulator. To further downward scaling, dielectric with a

higher dielectric constant will be the solution to achieve the same transistor performance while

maintaining a relatively thick physical thickness [1]. Many alternate high-k gate dielectrics have

been studied and to replace SiO2. Among the candidates, Hf-based oxides have been recently

highlighted as the most suitable dielectric materials because of their comprehensive performance.

However, one of the key issues concerning new gate dielectrics is the low crystallization

temperature and difficult to integrate them into traditional CMOS processes.

In the assignment, brief history of high-k development, the requirements of high-k oxides, various

candidates of high-k, and the latest hafnium-based high-k materials will be discussed.

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2. Brief history of high-k dielectric development

To overcome gate leakage problems, incorporation of nitrogen into SiO2 has been adopted. There

are several ways to introduce nitrogen into SiO2, such as post deposition annealing in nitrogen

ambient and forming a nitride/oxide stack structure. By incorporating nitrogen into SiO2, it not only

increases the dielectric constant but also acts as a better barrier against boron penetration. In

addition, a nitride/oxide stack structure maintains the benefits of good interface quality between the

oxide and substrate [2], as shown in Fig.1.

Fig.1. Schematic showing incoming nitrogen radicals replace oxygen atoms to form Si–N bonds.

Despite the immense development with SiO2, these oxynitrides still have low k values and so a

relatively thick layer is required to prevent direct tunneling current. Therefore, alternative materials

with a higher k than SiO2 are needed to achieve the required capacitance without tunneling

currents. A lot of oxides have been proposed (Al2O3, Y2O3, La2O3, Sc2O3 and lanthanides such

as Pr2O3, Gd2O3 and Lu2O3), unfortunately due to limitations dictated by low power applications,

scalability, or serious reactions with the Si substrate. The choice of alternative gate dielectrics has

been narrowed to HfO2, ZrO2 and their silicates due to their excellent electrical properties and high

thermal stability in contact with Si.

However, another problem associated with Hf-based and Zr-based oxides is low crystallization

temperature. They can easily crystallize during standard CMOS processes. Hf-based oxides are

preferred over Zr-based oxides for its relative higher crystalline temperature. These crystalline

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structures can increase the gate leakage which providing pathways for diffusion of dopants and

dielectric breakdown. Many focused on the improvement of the crystallization temperature of these

oxides, such as N, Si, Al, Ta and La have been incorporated into these Hf-based high-k oxides.

3. Requirements of High-K Oxides

The most important requirements of gate dielectric materials are good insulating properties and

capacitance performance. Because the gate dielectric materials constitute the interlayer in the gate

stacks, they should also have the ability to prevent diffusion of dopants such as boron and

phosphorus and low defects. Meanwhile, they must have good thermal stability, high

recrystallization temperature and good interface qualities.

3.1. K Value, Band Gap and Band offset

The requirement of k value should be over 12 and the dielectric will have a reasonable physical

thickness which is enough to prevent gate leakage not too thick to hamper physical scaling when

achieving the target EOT and Fig. 2 shows that the k values of some oxides vary inversely with the

band gap [3].

Fig. 2. Dielectric constant (k), band gap and CB offset on Si of the candidate gate dielectric.

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To achieve the required insulating properties, the gate dielectric must exhibit at least the band offset

of 1eV while in contact with the Si substrate in order to avoid gate leakage and breakdown. The

band offset is required to be over 1eV in order to inhibit conduction by the Schottky emission of

electrons or holes into the oxide bands [3], as shown in Fig.3. This means that the materials must

have both the conduction band offset (CB) and valence band offset (VB) over 1 eV.

Fig. 3. Band offsets of CB and VB and dependence of carrier injection in oxide band states.

3.2. Thermal Stability

This requires that the gate oxides must be thermally and chemically stable especially with the

contacting materials, because the gate stacks need to undergo rapid thermal annealing (RTA)

process. Therefore, from the thermal stability point of view Al2O3, ZrO2, HfO2, Y2O3, La2O3,

Sc2O3 and some lanthanides such as Pr2O3, Gd2O3 and Lu2O3 are suitable. From the materials,

ZrO2 with higher heat of formation than SiO2 may also be slightly reactive with Si forming the

silicide, ZrSi2 which is not suitable for gate oxide. Among these high k dielectrics, HfO2 has both a

high k value as well as chemical stability with water and Si.

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3.3. Crystallization Temperature

Amorphous materials are preferred to crystalline because absence of grains and good diffusion

barrier properties. The grains which lie in the crystalline systems can often be the pathways for

dopants diffusion and breakdown. Unlike SiO2, high-k oxides usually have low crystalline

temperature and can easily crystallize when subjected to RTA. In particular, HfO2 and ZrO2

crystallize at much lower temperatures at ~4000 C and ~300

0 C, respectively. The approach to

improve the crystallization temperature of HfO2 and ZrO2 has been intensively studied. The

crystallized HfO2 has a much lower leakage current which has convinced many companies to adopt

binary oxides because of their relative higher k values.

3.4. Interface Quality

Interface quality is another key criterion for the high k dielectrics. The dielectric – silicon interface

must have the best electrical quality, flatness, absence of defects such as dangling bond and

impurities; to ensure the low interface state density. High fixed charge density will be introduced in

the interface, if the quality is not well controlled. This will induce a large shift in the flat band

voltage which is one of the most critical factors for the device performance and reliability.

Particularly there are two solutions to keep the interface with high quality; either amorphous oxide

grown on the silicon or epitaxial grown crystalline oxide on silicon. Comparing these two solutions,

amorphous oxide is more suitable than epitaxial oxide for current technology. First, amorphous

oxide stays lower cost than epi-oxide, and it is more compatible with the existing manufacturing

processes. Second, amorphous oxide could limit the interface defect concentration, and it is

achievable to gradually changing the composition without adding new phase. Third, its dielectric

constant is isotropic, thus the fluctuations in polarization from differently oriented oxide grains will

not lead to scattering of channel carriers. Last one, amorphous oxide does not have grain boundaries.

Considering all the above factors, the stack of gate dielectric will contain a few monolayers of Si-O

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materials as a buffer interlayer. This could maintain the critical, high quality nature of the SiO2

interface while providing a higher k value for that thin layer. A different high k material can also be

used on top of it.

3.5. Defects

Bulk defects introduced during the deposition of the high k material, is similar to interface defects,

will lead to the degradation of the dielectric performance as the rising number of defect-related

fixed charges and finally cause reliability issues. These defects act as the trap center for charges,

and might result in the time dependent shift for gate threshold voltage; associated with negative bias

temperature instability (NBTI); at the same time the trapped charges will scatter channel carriers

and reduce the carrier mobility. Normally, the bulk defects are sites of excessive or deficient oxygen

atom, or impurities; and this is the starting point for electrical failure and dielectric breakdown.

Unfortunately, most of the high k oxides inherently have more interface defects with silicon

substrate and bulk defects than SiO2 as their boning cannot relax easily. Currently, organization will

reduce the defect concentration by either process control or engineering of the materials.

Fig.4. Schematic diagram of two types of defects located (a) at the HfO2/SiO2 interface and

(b) in the bulk of HfO2 film.

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4. Latest Development in Hf-Based High-k Oxides

Crystallization of pure HfO2 occurs at only about 400–4500 C causing grain boundary leakage

current and non-uniformity of the film thickness. As a result, impurities such as O, B, and P can

penetrate the grain boundaries during high temperature post processing. It causes equivalent oxide

thickness (EOT) scaling and reliability concerns when Hf-based high-k ultrathin gate oxides are

integrated into high temperature CMOS processes.

4.1. Nitrogen Doped Hf-Based High-k Oxides

Nitrogen introduction into HfO2 films has significantly improved the electric properties as well as

crystallinity but nitrogen doping leads to decreased band gap. Despite the disadvantages, the

introduced nitrogen can suppress the growth of microstructure and interfacial layer. When N is

added to HfO2, it is expected to distort the equilibrium of the lattice and produce disordered states.

Researches have demonstrated that adding nitrogen results in the reduction of the mobility of Hf

and O atoms as well as increase in the nucleation temperature and consequently the crystalline

temperature. All these indicate that nitrogen acts as a crystallization inhibitor and causes an increase

in the crystallization temperature in Hf-based gate dielectrics [5] (Fig. 5).

Fig.5. XRD spectra for the HfO2 and HfOxNy films: (a) as-deposited and HfOxNy films annealed at

different temperatures and (b) as-deposited and HfO2 films annealed at different temperatures.

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4.2. Silicon Doped Hf-Based High-k Oxides

The interfacial layer between the high-k dielectrics and Si substrate is one of the key factors

determining the performance and reliability of a MOS transistor. Hence, it is extremely crucial to

fabricate a SiO2/Si like interface. A SiO2 interfacial layer is often grown between Hf-based oxide

and Si by thermal oxidation, HfO2/SiO2 gate dielectric stack usually introduces an additional EOT

increase due to the low k SiOx interfacial layer, whereas addition of Si into Hf-based oxide to form

Hf silicate will improve interface quality and foster the formation of amorphous structures. A

negative effect is the reduction in the k value, the k value decreases inversely with increasing Si

concentration in Hf-based oxides.

By using nitrogen incorporated HfSiO films, HfSiON is thermally stable compared to HfO2 due to

the Si-N bonds that are created by the nitridation step, and thus HfSiON has the potential for

implementation in a conventional gate-first process with high temperature activation annealing.

4.3. Aluminum Doped Hf-Based High-k Oxides

Al inclusion in HfO2 significantly increases the crystallization temperature. It can be seen that [10]

Fig.6. Crystallization temperature, dielectric constant of HfAlO as functions of Al percentage.

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the crystallization temperature increases monotonically from 375 oC for HfO2 to 1000

oC for HfAlO

with 45.5% Al. At an Al content of 31.7%, the crystallization temperature is about 400-500 oC

higher than that without Al. Figure 6 shows that the crystallization temperature increases as the

increment of Al contend in HfAlO, and the dielectric constant will decrease correspondingly. This

is due to the action of Al as a network modifier and stabilizes the amorphous phase of the metal

oxides.

It has been proved by Zhu et al [10], Moon et al [11], that the addition of Al also causes a

corresponding increase of the PDA (post deposition anneal) temperature at which the peak gate

leakage current occurs. Figure 7 shows the experimental results for where the leakage current for

MOS capacitors with about 1.1 nm equivalent oxide thickness (EOT) of HfO2, is plotted as a

function of PDA temperature from 300 oC to 800

oC. The temperature corresponding to the peak

leakage current is about 500 oC for HfO2, 700

oC for HfAlO with 6.8% of Al, and estimated to be

well above 800 oC for HfAlO with 31.7% of Al.

Fig.7. Gate leakage currents of HfO2, HfAlO with about 6.8% of Al and HfAlO with about 31.7% of

Al, as functions of PDA temperature.

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Most of high-K dielectric films are about to be crystallized during deposition or subsequent high

temperature process. Polycrystallization of thin films generates grain boundaries in thin dielectric

films which act as leakage current path, resulting in high leakage current. Thus, the onset of rising

leakage current is probably due to crystallization of the film, causing increased leakage through

grain boundaries. While with introducing in the Al component, it is clearly seen that HfAlO film

remained amorphous after PDA at 700 oC, while HfO2 was crystallized. Figure 8 shows the XTEM

images of HfO2 and HfAlO with TaN gate electrode. Both films undergo the same temperature of

400 oC deposition conditions and same PDA of 700

oC for 1 mins [11].

Fig.8. XTEM images of HfO2 and HfAlO after 700 oC in-situ PDA treatment. HfAlO layer remains

amorphous while HfO2 is crystallized. Both films were deposited at 400 oC without surface

nitridation.

Another advantage that Al incorporation brings to the dielectric is the increase of band gap; since

the tunneling current could be reduced dramatically as the band offset of the dielectric increases.

With Al, the band gap was increased from 5.8eV for pure HfO to 6.5eV for 45.5% Al content

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HfAlO. Despite the advantages of Al doped Hf-based High k oxide, there is one drawback for Al

incorporation. It introduces negative fixed oxide charges due to Al accumulation at the HfAlO – Si

interface, which resulting in channel carrier mobility degradation [12].

Considering the tradeoff among the crystallization temperature, band gap, and dielectric constant,

Zhu et al [10] has suggested that the optimum Al concentration is about 30% for conventional self –

aligned CMOS gate processing technology.

4.4) Tantalum Doped Hf-Based High-k Oxides

HfTaO gate dielectrics draw the researchers’ attention due to its good thermal stability and

electrical characteristics. With introducing Ta into HfO, it enhances the crystallization temperature

significantly while keeping a relatively high k value of about 17 [13]. Zhu et al [14] has confirmed

that with the incorporation of 43% Ta dramatically increases the crystallization temperature of HFO

up to 1000 oC. The degradation of dielectric constant is also avoided due to the high dielectric

constant of Ta2O5 ( k ~ 26). Since the HfTaO with 43% Ta film remains amorphous after activation

annealing at 950 oC for 30s, remarkable suppression of low – k interfacial layer growth and boron

penetration were achieved. Figure 9 shows the crystallization temperature vs Ta composition, which

indicate that about 43% Ta has the highest crystallization temperature about 1000 oC. This may be

attributed to the breaking of the periodic crystal arrangement or the inhibition of continuous crystal

growth in gate dielectric by incorporating Ta into HfO film. Figure 10 present the TEM images,

indicating the HfO film is fully crystallized whereas the HfTaO with 43% Ta film remains

amorphous after same condition of 700 oC PDA; meanwhile by comparing the thickness for

interlayers, it tells that the amorphous layer of HfTaO can effectively block oxygen diffusion

through the grain boundaries to form low – k interfacial layer during the high temperature annealing.

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Fig.9. XRD spectra of HfO2, HfTaO, and Ta2O5 for as-deposited and different temperature

annealing in N2. The crystallization temperature of HfO2 film is increased up to 1000 °C by

incorporating 43% Ta.[14]

Fig.10. TEM images of HfO2 and HfTaO with 43% Ta after PDA at 700 °C for 40 s and activation

annealing at 950 °C for 30 s. The HfO2 film is fully crystallized whereas the HfTaO with 43% Ta

film remains amorphous.[14]

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It is also indicated that the boron penetration induced flat band voltage shift in HfO film is

significantly suppressed by incorporating Ta. Figure 11 shows the negligible flat band voltage shift

of HfTaO with 43% Ta film is observed up to 950 °C annealing temperature. The excellent boron

penetration immunity is due to its amorphous structure which remains after high temperature

processes in the device fabrication. As Boron from the p+ ploy silicon gate electrode may easily

diffused not only through the gate dielectric layer, but also into the channel region during the dopant

activation annealing, it results in interface degradation and flat band voltage shift. Thus, the 43% Ta

doped Hf based high k dielectric could increase the reliability and performance of the device. Zhang

et al [15] also proved that compared to HfO gate dielectrics, HfTaO has advantages of much lower

charge trapping and at about 40% content of Ta, N-MOSFETs demonstrate the highest electron

mobility than other percentages.

Fig.11. Comparison of the flat-band voltage shift in HfO2 and HfTaO p-type MOS capacitors after

various temperature annealing. HfTaO films show a stronger immunity to boron penetration than

HfO2, due to its high crystallization temperature. [14]

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4.5. Lanthanum Doped Hf-Based High-k Oxides

In addition to Si, N, Al, Ta, rare earth element La can also be used to improve the characteristics of

Hf based high k dielectrics. With introduction of La2O3 into HfO, the crystallization temperature is

increased. As shown in figure 12, the crystallization temperature could be increased above 900 °C

respected to the increase of the La content. Moreover, unlike Al, N doped dielectric, the permittivity

of HfLaO still keep at high k value, normally above 20 [16].

Fig.12. XRD spectra of 30 nm films of _a_ HfO2, _b_ La2O3, _c_33%La–HfLaOx, and _d_

40%La–HfLaOx annealed at various temperatures. HfO2 and La2O3 films crystallize at under

600 °C. On the other hand, 40%La–HfLaOx film remains amorphous after 900 °C annealing.

Another advantage for HfLaO is that the small degradation in both the interface and bulk properties.

This is proved by Yamamoto et al [16]. In the capacitance – voltage (C–V) curve at different

frequencies, the curves show negligibly small hysteresis and no frequency dispersion. Even at 1

kHz, could not observe even a small hump, which is often detected in C-V curves of high – k MOS

capacitors. This result indicates a rather good quality of Si/HfLaO interface. The C-V curve of MOS

capacitors with even thicker HfLaO film has also shown the negligibly small hysteresis and no

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frequency dispersion that indicate the good bulk properties with a very low fixed charge density.

Figure 13 introduce the C-V curve for Au/40%La-HfLaO/p-Si metal insulator semiconductor.

Fig.13. C-V characteristics of Au/40%La–HfLaOx / p-Si MOS capacitor annealed at 600 °C. The

film thickness was 8.4 nm. It shows very small hysteresis and frequency dispersion. The inset in the

upper right shows the flatband voltages of Au/20%La–HfLaO/ p-Si or 40%La–HfLaO/ p-Si MOS.

It is also shown in figure 13 that La based dielectrics exhibit negative flat band shifts from the ideal

value; but the shift is not remarkable even in a thick film. Considering the high crystallization

temperature (>900) and high dielectric constant, good quality of bulk and interface properties with

few fixed charges, La doped Hf based high k dielectric is one of the potential materials for high k

gate insulator.

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5. Conclusion

This assignment reviews the motivation to replace traditional SiO2 gate dielectrics, brief history of

high-k materials development, requirements of high-k dielectrics and latest development in Hf-

based high-k dielectrics. In order to improve the performance of CMOS devices, Hf-based gate

layers are being integrated into MOSFETs to achieve low leakage current. Excellent gate transistors

with improved performance based on Hf-based gate dielectrics as the insulating layers are expected.

Although much progress has been made in fabricating novel gate dielectrics, investigation of these

Hf-based high-k gate dielectrics continues to be exciting and the final target has not yet been

reached.

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6. References

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Solid-State Electronics.

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HfOxNy and HfO2 gate dielectrics in TaN gated nMOSCAP and nMOSFET devices, vol. 22, pp.

1755-1758, J. Vac. Sci. Technol. B.

[iii] Zhu, W. J.; Tamagawa, T.; Gibson, M.; Furukawa, T. & Ma, T. P. (2002). Effect of Al

inclusion in HfO₂ on the physical and electrical properties of the dielectrics, vol. 23,

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[xiv] Yu, X.-F.; Zhu, C.-X.; Li, M. F.; Chin, A.; Du, A. Y.; Wang, W. D. & Kwong, D.-L. (2004).

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