High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

Analog Circuits and Signal Processing

Series Editors:Mohammed Ismail. The Ohio State University

Mohamad Sawan. Ecole Polytechnique de Montreal

For further volumes:http://www.springer.com/series/7381

Pui-In Mak � Rui Paulo Martins

High-/Mixed-VoltageAnalog and RF CircuitTechniques for NanoscaleCMOS

Pui-In MakUniversity of MacauTaipa, Macao, China

Rui Paulo MartinsUniversity of MacauTaipa, Macao, China

ISBN 978-1-4419-9538-4 ISBN 978-1-4419-9539-1 (eBook)DOI 10.1007/978-1-4419-9539-1Springer New York Heidelberg Dordrecht London

Library of Congress Control Number: 2012933993

# Springer Science+Business Media New York 2012This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part ofthe material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission orinformation storage and retrieval, electronic adaptation, computer software, or by similar or dissimilarmethodology now known or hereafter developed. Exempted from this legal reservation are brief excerptsin connection with reviews or scholarly analysis or material supplied specifically for the purpose of beingentered and executed on a computer system, for exclusive use by the purchaser of the work. Duplicationof this publication or parts thereof is permitted only under the provisions of the Copyright Law of thePublisher’s location, in its current version, and permission for use must always be obtained fromSpringer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center.Violations are liable to prosecution under the respective Copyright Law.The use of general descriptive names, registered names, trademarks, service marks, etc. in thispublication does not imply, even in the absence of a specific statement, that such names are exemptfrom the relevant protective laws and regulations and therefore free for general use.While the advice and information in this book are believed to be true and accurate at the date ofpublication, neither the authors nor the editors nor the publisher can accept any legal responsibility forany errors or omissions that may be made. The publisher makes no warranty, express or implied, withrespect to the material contained herein.

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Weng-Ieng & Long-ChengDita & Filipa, Diogo, Guilherme e Maria

Preface

The scope of more intelligent and higher data rate wireless connectivity in the

coming decades continuously push the performance envelope of wireless circuits

and systems. Higher integration level, more functionality, less cost and lower power

are the obvious goals. For the radio front-ends, inductorless broadband solutions

possess the highest potential to economically realize low-power multi-standard

solutions in nm-length CMOS technologies. The rapid downscaling of transistor

sizes and gate-oxide thickness, however, involves rapid reduction of supply voltage

for reliability. This fact, in addition to the changed device features such as lower

intrinsic gain and linearity, urges for more feasible techniques from different

dimensions, such that the performances can be aligned continuously with the

expectation from the global wireless chip industry.

In this book, high-/mixed-voltage analog and RF circuits are investigated as the

prospective solution for the next generation of wireless products in nm-length

CMOS technologies. The content starts by overviewing the design considerations,

pros and cons of high-/mixed-voltage circuits before describing three tailor-made

circuit designs targeting the mobile-TV applications. Mobile TV is recognized as

one of the key functions of handheld devices such as smart phones.

The first design is a 90-nmCMOS ultra-wideband low-noise amplifier withmixed-

voltageESDprotection for handling the full-bandofmobileTV.The second is a 90-nm

CMOShigh-voltage-enabledmobile-TVRF front-endwithTV-GSMinteroperability.

The third is a 65-nmCMOSmixed-voltage unified full-bandmobile-TV receiver front-

end averting any external balun,whilemeasuring favorably performanceswith respect

to the state-of-the-art.

Most techniques are generally extendable to different types of wireless systems

in ultra-scaled CMOS technologies.

Taipa, Macao, China Pui-In Mak

Rui Paulo Martins

vii

Acknowledgments

We are grateful to Macao Science and Technology Development Fund (FDCT)

and Research Committee of University of Macau (UM), for funding the project and

equipments of the State Key Laboratory of Analog and Mixed-Signal VLSI.We thank Mr. Ka-Fai Un andMiao Liu for their contribution to the design of the

multi-phase local oscillator generator and high-voltage amplifier, respectively.

We thank the staff at Springer, particularly Chuck Glaser, for guiding the

preparation of this book.

Finally, we send our heartfelt appreciation to our families, who endured our

dedication to this book.

ix

Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 The Global Development of Wireless Technologies . . . . . . . . . . . . . . . . . 1

1.2 Analog and RF Circuits in Nanoscale CMOS. . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Research Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4 Organization of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 General Considerations of High-/Mixed-VDD Analog

and RF Circuits and Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 System Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Device Reliability in Ultra-scaled Processes . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 AMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 HCI Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.3 TDDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.4 NBTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.5 Punchthrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Extend the Voltage Capability of Thin-

and Thick-Oxide Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 High-/Mixed-Voltage Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1 Power Amplifier and Wideband Balun-LNA

(High-VDD þ Mixed-Transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.2 Passive Mixers (High-VDD þ Thin-Oxide Transistor) . . . . . . . 15

2.5.3 Differential Pair (High-VDD þ Thin-Oxide Transistor) . . . . . . 17

2.5.4 Recycling Folded Cascode Operational Amplifier

(High-VDD þ Thin-Oxide Transistor) . . . . . . . . . . . . . . . . . . . . . . . . 18

2.5.5 OpAmp-Based Analog-Baseband Circuits

(Mixed-VDD þ Mixed-Transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.5.6 Low-Dropout-Regulator

(Mixed-VDD þ Mixed-Transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

xi

2.5.7 Sample-and-Hold Amplifier

(High-VDD þ Mixed-Transistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.8 Line Driver (High-VDD þ Thin-Oxide Transistor) . . . . . . . . . . . 32

2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3 A Full-Band Mobile-TV LNA with Mixed-Voltage

ESD Protection in 90-nm CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.1 Full-Band Mobile-TV Tuner Architecture . . . . . . . . . . . . . . . . . . . 36

3.2.2 PMOS-Based Open-Source Input Structure

and Mixed-Voltage ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.3 Double Current Reuse for gm-Enhancement. . . . . . . . . . . . . . . . . . 39

3.2.4 Single-Stage Thermal-Noise Cancellation. . . . . . . . . . . . . . . . . . . . 41

3.3 Key Practical Design Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3.1 Package Effect on Input Impedance Match . . . . . . . . . . . . . . . . . . 43

3.3.2 Self-Startup Constant-gm Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3.3 Power-Up/Down Control with Reliability Concern . . . . . . . . . . 45

3.3.4 Mixed-Voltage ESD Protection Scheme . . . . . . . . . . . . . . . . . . . . . 45

3.4 Simulation Results, Discussions and Benchmarks. . . . . . . . . . . . . . . . . . . . 46

3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 A High-Voltage-Enabled Mobile-TV RF Front-End

in 90-nm CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.2 Tuner Architecture for TV-GSM Interoperation. . . . . . . . . . . . . . . . . . . . . . 55

4.3 On/Off-Chip Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3.1 Basic-Cell of the LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3.2 ESD Protection Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.3 Programmable C-2C Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.4 I/Q Mixer Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.5 Customized External Preselect Filters . . . . . . . . . . . . . . . . . . . . . . . . 70

4.3.6 Feedforward Gain Roll-Off Compensation . . . . . . . . . . . . . . . . . . . 72

4.4 Experimental Results, Discussions and Benchmarks. . . . . . . . . . . . . . . . . 73

4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5 A Mixed-Voltage Unified Receiver Front-End for Full-Band

Mobile TV in 65-nm CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.2 RFE Architecture and Technology Features. . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3 Wideband Balun-LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

xii Contents

5.3.1 CG-CS Noise-Canceling Balun-LNA . . . . . . . . . . . . . . . . . . . . . . 84

5.3.2 Proposed Gain-Boosting Current-Balancing

Balun-LNA with VGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.4 Current-Reuse Mixer-LPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.4.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.4.2 Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.4.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.5 Multi-phase LOG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.5.1 Brief Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.5.2 Open Loop Multi-phase LO Generators

(Conventional and Proposed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.5.3 Circuit Implementation and Simulation Results. . . . . . . . . . . . 105

5.6 Measurement Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.6.1 The RFE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.6.2 The LOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.6.3 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.6.4 Architecture Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.1 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.2 Recommendations for Future Research. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Appendix: Open-Loop Multiphase LO Generators . . . . . . . . . . . . . . . . . . . . . . . 125

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Contents xiii

Abbreviations

1/f Flicker noise

AC Alternating current

ADC (A/D) Analog-to-digital converter

AMR Absolute maximum rating

ATT Attenuator

BB Baseband

BiCMOS Bipolar complementary metal oxide semiconductor

BPF Bandpass filter

BSF Band-selection filter

BTI Bias temperature instability

BUF Buffer

BW Bandwidth

CG Conversion gain

CG Common-gate

CLKGEN Clock generator

CM Common mode

CMFB Common mode feedback

CMOS Complementary metal oxide semiconductor

CMRR Common-mode rejection ratio

CQFP Ceramic quad flat-pack

CS Common-source

CSF Channel-selection filter

CT Continuous-time

DC Direct current

DMB-T Digital multimedia broadcasting-terrestrial

DRC Design rule check

DSB Double-side band

DSP Digital signal processor

DVB-T/H Digital video broadcasting-terrestrial/handheld

xv

ESD Electrostatic discharge

FET Field effect transistor

FF Fast-fast (corner)

FS Fast-slow (corner)

FS Frequency synthesizer

GBW Gain-bandwidth product

GSM Global system for mobile communications

HBM Human body model

HCI Hot carrier injection

HD2/HD3 Second-/third-order harmonic distortion

HPF Highpass filter

HR/HRR Harmonic rejection (ratio)

I In phase

I/P Input

IC Integrated circuit

IEEE Institute of electrical and electronics engineering

IIR Infinite-impulse response

IM3 Third-order intermodulation distortion

IP3 Third-order intercept point

IRR Image-rejection ratio

ISDB-T Integrated services digital broadcasting-terrestrial

ISM Industrial, scientific and medical

ISSCC IEEE international solid-state circuits conference

I-to-V Current-to-voltage

JSSC IEEE journal of solid-state circuits

LDO Low-dropout regulator

LIF Low IF

LNA Low-noise amplifier

LO Local oscillator

LOG Local oscillator generator

LPF Lowpass filter

LTCC Low-temperature co-fired ceramic

LV Low voltage

LVS Layout versus schematic

MOSFET Metal-oxide semiconductor field-effect transistor

NF Noise figure

O/P Output

OFDM Orthogonal frequency-division multiplexing

OpAmp Operational amplifier

OTA Operational transconductance amplifier

xvi Abbreviations

PCB Printed-circuit board

PLL Phase-locked loop

PM Phase margin

PVT Process, supply voltage and temperature

Q Quadrature phase/quality factor

QAM Quadrature amplitude modulation

RC Resistor-capacitor

RF Radio frequency

RFE Receiver front-end

RX Receiver

S2D Single-to-differential

SAW Surface acoustic wave

SF Slow-fast (corner)

SFDR Spurious-free dynamic range

SoC System-on-chip

SS Slow-slow (corner)

TDDB Time dependent dielectric breakdown

T-DMB Terrestrial-digital multimedia broadcasting

TX Transmitter

TXR Transceiver

UHF Ultra-high frequency

UWB Ultra wideband

VCO Voltage control oscillator

VGC Variable gain control

VHF Very-high frequency

V-to-I Voltage-to-current

WLAN Wireless local area network

ZIF Zero IF

Abbreviations xvii

Chapter 1

Introduction

1.1 The Global Development of Wireless Technologies

The convergence of wireless and semiconductor industries will turn into reality the

vision of fully autonomous and seamless wireless connectivity in the near future,

via combining advanced nanoscale CMOS technologies with innovative hybrid-

domain circuits and systems solutions [1, 2]. One aim inside this immense scope is

to develop a smart-mobile-companion device with high performance, adaptiveconnectivity and high power efficiency. High performance is the essential ingredient

to cope with the ever increasing add-on of functionalities in a small handheld

device. Adaptive connectivity is to automatically select the best wireless link,

maximizing the quality of service wherever and whenever possible. Power

efficiency is to extend the active-use days without entailing a big battery, or

worrying about the battery life after executing much of the device’s functionality.

To reach these three goals the system chips consisting of many analog and radio

frequency (RF) circuits play a key role. The aim of adaptive connectivity promotes

a full integration of many different radio technologies such as WiFi, Global

Positioning System (GPS), BluetoothTM, cellular and mmWave into one unit,

calling for an unprecedented high level of complexity among system planning,

architectures and circuits. The goal of maximizing hardware sharing without

compromising the performances challenges the designers throughout the front-to-

back-end development. Yet, advanced nanoscale CMOS technology constitutes,

still today, the most promising platform of wireless products for its tremendous

advance in speed, system-on-chip capability and maturity (to some extent).

In terms of power efficiency, 10-fold reduction of system power is the targeted

goal. This aggressive goal calls unavoidably for groundbreaking innovation in

silicon transceivers, sensors and mixed-signal interfaces. Investigation on new

architecture and circuit solutions benefiting the speed and area advantages of

nanoscale processes may eventually break the power wall. It is believed that,

the many new opportunities opened up by the wireless industry are bringing

P.-I. Mak and R.P. Martins, High-/Mixed-Voltage Analog and RF Circuit Techniquesfor Nanoscale CMOS, Analog Circuits and Signal Processing,

DOI 10.1007/978-1-4419-9539-1_1, # Springer Science+Business Media New York 2012

1

along another wave of synergy among the semiconductor industries including

the manufacturers, fabless IC design houses and CAD providers. As evidenced in

the last 20 years, the many challenges ahead continuously motivate large-scaleresearch and development in many aspects of integrated circuit design in the

coming decades.

1.2 Analog and RF Circuits in Nanoscale CMOS

Rapid downscaling of CMOS has led to faster analog and radio frequency (RF)

circuits, but with deteriorated linearity and accuracy due to lower device’s intrinsic

gain. Entered into the sub-1 V nanoscale regime, the downsizing of threshold

voltage (VT) is decelerated due to transistor variability, matching and leakage issues.

Along with the low supply voltage (VDD) constrained by the device reliability limits,

the trade-off between signal dynamic range and number of cascode transistors that

can be utilized become increasingly severe [3, 4]. While cascode structures are no

longer voltage efficient, cascade structuresmay not bewelcome also because of their

higher power consumption and lower operating speed. Thus, circuit techniques

that will continuously fit for sub-1 V processes must be investigated, in order to

keep driving up circuit performances in technology scaling.

1.3 Research Objectives

In this book, high-/mixed-voltage analog and RF circuits and systems are exten-

sively investigated. They have gained extensive attention in state-of-the-art

nanoscale-CMOS wireless systems such as mobile-TV, GPS and software-defined

radios [5–9]. As depicted in Fig. 1.1, for a wideband SAW-less receiver for multi-

standard compliance, maximizing the receiver dynamic range (DR) is essential to

detect weak signal in presence of high-power blockers.

0 dBm unwanted blocker (632 mVpp in 50W)

LO

RF BBLNA

High DR

-80 dBm desired signal(63.2 µVpp in 50W)

blockers

desiredFig. 1.1 Wideband multi-

band solution requires high

DR from all RF and baseband

circuits

2 1 Introduction

It is known that, for most analog and RF circuits, maintaining a constant

performance (i.e., signal to noise and distortion ratio) in a newer technology will

entail more power to compensate the loss of voltage headroom [10]. The basis can

be illustrated through the analysis of the relationship between VDD and the dynamic

range of a common-source (CS) amplifier with a resistive load, as shown in

Fig. 1.2a.

The channel-length modulation is neglected for simplicity. The input-referred

squared noise voltages imputable to M1 and RL are given by,

V2n;M1 ¼ 4kT

1

gmg; (1.1)

and

V2n;RL ¼ I2n;RL

1

g2m¼ 4kT

RL

1

g2m; (1.2)

respectively, where g is the noise factor and gm is the transconductance of M1, k isthe Boltzmann’s constant, T is the temperature (in Kelvin). The generic I-Vequation of a MOSFET considering the mobility degeneration parameter y is

given by,

ID ¼ 1

2

W

LmoCoxðVGS � VTÞ2 1

1þ yðVGS � VTÞ ; (1.3)

where W/L is the aspect ratio of the transistor and moCox is the transconductance

parameter. From (1.3), the input-referred third-order intercept point (IIP3) of a

MOSFET can be calculated [11],

V2IIP3 �

8

3

VGS � VT

y¼ 16

3

IDgmy

: (1.4)

RL

RL RL

VDD

VDD

VSS

Vout

Vin

ID

ID /2 ID /2

Vn,M1

In,RL

VCM.o+Vp

VCM,o-Vp

VCM,o

M1

M2

M1 M4

M3 M5 M6VLOp

VRFnVRFp

VLOp

Voutp Voutn

VLOn

2

2

a b

Fig. 1.2 (a) Typical CS amplifier and (b) typical active mixer with resistive load

1.3 Research Objectives 3

With (1.1), (1.2), and (1.4), the dynamic range DRCS of the CS amplifier can be

approximated,

DRCS � V2IIP3

V2n;M1 þ V2

n;RL

� 4

3

IDkTyg

; (1.5)

In practice, ID cannot be arbitrarily increased to boost DRCS when there is no

voltage headroom, i.e., the output common-mode voltage VCM,o must be withinVDD,

VCM;o ¼ xVDD ¼ VDD � IDRL; (1.6)

where x denotes a ratio value <1 and can be set as 0.5 for VCM,o ¼ VDD/2, which

roughly yields the highest 1-dB compression point (P1dB). Substituting (1.6) into

(1.5) lead,

DRCS � 2

3

VDD

RL

1

kTyg: (1.7)

When a high gain is desired, RL and VDD can be increased together by a factor

A such that the DR is maintained, while ID remains unchanged. The power is

increased by A times too. A similar situation holds for active mixer [12] as shown

in Fig. 1.2b. Its DR can be calculated following the same approach, i.e.,

DRMIXER � 2

3

VDD

RL

1

kTyg4

p2: (1.8)

Obviously, VDD cannot be arbitrarily increased to maximize the circuit’s DR due

to the reliability limitations. The major device reliability concerns of ultra-scaled

CMOS processes include the absolute maximum rating (AMR), hot carrier injection

(HCI), negative bias temperature instability (NBTI), time dependent dielectric

breakdown (TDDB) and punchthrough effect [13]. Boosting the device reliability

by transistor stacking can push upward the drain-source voltage limit. Differently,

the gate-drain/-source voltages should be controlled via proper bias in both active

and sleep modes. The device stacking can be simply based on thin-oxide devices,

or a hybrid of thin- and thick-oxide devices to balance the speed and voltage

withstand capability. Their implications to the circuit or system should be analyzed

according to the actual operation. For instance, when the maximum input and

output swings are defined, node-voltage trajectory checks can help to ensure there

is no device under overstressed at all time.

Inductorless wideband analog and RF techniques are considered as the key to

realize the next generation wireless multi-standard products in expensive nm-length

CMOS processes. As mentioned above, one of the keys to enhance the DR is

via elevating VDD, or in a wider extent, using mixed VDD as well as thin- and

thick-oxide transistors offered by advanced technologies [14]. Thin-oxide

transistors are normally for core design having a voltage limit which is the same

4 1 Introduction

as the nominal VDD. Thick-oxide transistors are for I/O design that can work at a

higher supply voltage. When design-for-reliability (i.e., prevents any device to be

under overstress) is included in the design flow, an elevated VDD outpacing the

technology roadmap can reliably enlarge the voltage headroom (VDD�VT) as

depicted in Fig. 1.3, where VT denotes the device threshold voltage.

As a way of demonstrating the techniques, the mobile-TV application is selected

as the common platform, which is recognized as one of the key functions for the next

generation smart-mobile-companion device [1]. The targeted mobile TV bands are

the VHF-III (174–248 MHz), UHF (470–862 MHz) and L (1.4–1.7 GHz)

bands as listed in Table 1.1. These three bands are where most mobile-TV standards,

2.5

3

3.5

4

Thr

esho

ld a

nd S

uppl

y V

olta

ges

(V)

0.13µm0.18µm

Technology Node

90nm 65nm0.25µm0

0.5

1

1.5

2

0.35µm

NominalVDD

An elevated VDD+

Design-for-Reliability

Elevated VDD

40nm

VT

Fig. 1.3 Benefiting thevoltageheadroomincrementviausinganelevatedVDDplusdesign-for-reliability

Table 1.1 Brief profiles of the most dominant mobile TV standards

Mobile TV standard

Frequency

(MHz) Data coding Air interface

T-DMB (Korea,

China, Europe)

174–245 Video: H.264 30 fps/QVGA OFDM (QPSK)

1,452–1,492 Audio: BSAC/AAC+

ISDB-T (Japan,

Brazil)

470–770 Video: H.264 15 fps/QVGA OFDM (QPSK/

16QAM)Audio: AAC+

DVB-H (Europe, US) 470–860 Video: H.264 30 fps/QVGA OFDM (QPSK/

16QAM/64QAM)1,670–1,675 Audio: AAC+

DMB-T (China) 470–860 Video: H.264 30 fps/QVGA OFDM (QPSK/

16QAM/64QAM)1,670–1,675 Audio: AAC+

MediaFLOTM (US) 712–722 Video: MPEG4 OFDM

1.3 Research Objectives 5

such as terrestrial–digital multimedia broadcasting (T-DMB), integrated services

digital broad-casting–terrestrial (ISDB-T), digital video broadcasting–handheld

(DVB-H) and digital multimedia broadcasting–terrestrial (DMB-T), reside.

Although the design examples in this book target mobile-TV applications, the

solutions are generally applicable to other wireless receivers in ultra-scaled

CMOS processes.

1.4 Organization of the Book

The materials are presented in six Chapters and one Appendix. Chapter 2 overviews

and studies, for the first time, state-of-the-art high-/mixed-voltage RF and analog

CMOS circuits and systems. Wherever appropriate their beneficial features

with respect to the conventional standard-voltage designs will be highlighted and

compared. From Chaps. 3 to 5, we present three circuit and system design examples

in nanoscale CMOS focusing on mobile-TV applications.

The first design is described in Chap. 3. It is a full-band mobile-TV low-noise

amplifier (LNA) with mixed-voltage ESD protection designed in 90-nm CMOS.

The details are outlined as follows:

• The LNA features a PMOS-based open-source input structure to optimize the

I/O swings under a mixed-voltage ESD protection while offering an inductorless

broadband input impedance match. The amplification core exploiting doublecurrent reuse and single-stage thermal-noise cancellation enhances the gain andnoise performances with high power efficiency. Optimized in a 90-nm 1.2/2.5-V

CMOS process with practical issues taken into account, the LNA using a

constant-gm bias circuit achieves competitive and robust performances over

process, voltage and temperature (PVT) variation. The simulated voltage gain

is 20.6 dB, noise figure is 2.4–2.7 dB and IIP3 is +10.8 dBm. The power

consumption is 9.6 mW at 1.2 V. |S11| < � 10 dB is achieved up to 1.9 GHz

without needing any external resonant network. Human Body Model ESD

zapping tests of �4 kV at the input pins cause no failure of any device.

Chapter 4 describes the second design, which is a high-voltage-enabled mobile-

TV RF front-end with TV-GSM interoperability fabricated in 90-nm CMOS.

The details are outlined as follows:

• It is an on/off-chip co-design employing externally three customized UHF/VHF

preselect filters, a RF switch and a balun. The integrated part includes:

(1) a cascode-cascade inverter-based low-noise amplifier that features a high

gain-to-power efficiency; (2) a linearized C-2C attenuator using reliable-

overdriven MOS switches; (3) an inductive-peaking feedforward path that

evens out the passband variation; and (4) two cascode I/Q mixer drivers

capable to drive passive mixers with small gain and bandwidth reduction.

Gate-drain-source engineering and self-biased structures are the keys enabling

6 1 Introduction

http://dx.doi.org/10.1007/978-1-4419-9539-1_2

http://dx.doi.org/10.1007/978-1-4419-9539-1_3

http://dx.doi.org/10.1007/978-1-4419-9539-1_5

http://dx.doi.org/10.1007/978-1-4419-9539-1_3

http://dx.doi.org/10.1007/978-1-4419-9539-1_4

performance optimization with low power and no reliability risk. Fabricated in a

90-nm CMOS process with 1-V thin-oxide devices, the RF front-end measures

68-dB rejection at GSM-900 uplink, 0.7-dB passband roll-off, 3.9-dB noise figure

and �5.5-dBm IIP3 at a maximum voltage gain of 26.2 dB. The core occupies

0.28 mm2 and draws 15 mW. The achieved power-performance metrics

compares favorably with the prior arts.

The third design example is presented in Chap. 5. It is a mixed-voltage, unified

receiver front-end for full-band mobile TV fabricated in 65-nm CMOS. The details

are outlined as follows:

• The receiver front-end features three advances: (1) a gain-boosting current-balancing wideband balun-LNA shows low noise figure (NF), high IIP2 and

wideband output balancing concurrently; (2) a current-reuse mixer-lowpass filter(LPF) merges quadrature/harmonic-rejection mixing and third-order current-

mode post filtering in one block, enhancing linearity and noise just where both

are demanding, while saving power and area; (3) a direct injection-locked4-/8-phase local oscillator (LO) generator involving frequency division relaxes

themaster LO frequency. Fabricated in a 65-nmCMOS process, the RFE exhibits

4-dB NF, 35-dB maximum voltage gain and +32/�3.4-dBm out-of-channel

IIP2/IIP3 while dissipating 43–55 mW. The active die area is just 0.46 mm2.

The concluding remarks and recommendations for future work are summarized

in Chap. 6. The Appendix describes the theoretical analysis and design of open-loop

multi-phase local oscillator generators. It is a complementary part of the 65-nm

CMOS receiver front-end described in Chap. 5. Although this part is not the major

interest of this book, this self-contained Appendix allows the readers to digest such

a set of materials when concerning the design details in Chap. 5. Finally, it should

be noted that this book covers a wide range of topics. For in-depth investigation and

further study, some area requires additional reading of the references, such as [15]

about the mobile-TV standards and specifications. The key originalities of this

research have led to these publications [16–20].

References

1. G. Delagi, “Harnessing Technology to Advance to Next-Generation Mobile User-Experience,”

IEEE ISSCC, Digest of Technical Papers, pp. 18–14, Feb. 2010.2. L. Perre, J. Craninckx, A. Dejonghe, Green Software Defined Radios: Enabling Seamless

Connectivity While Saving on Hardware and Energy, Springer, 2009.3. P.-I. Mak, S.-P. U and R. P. Martins, Analog-Baseband Architectures and Circuits – for

Multistandard and Low-Voltage Wireless Transceivers, Springer, Sept. 2007.4. P.-I. Mak, S.-P. U and R. P. Martins, “On the Design of a Programmable-Gain Amplifier with

Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems,” IEEETransactions on Circuits and Systems – I: Regular Papers, vol. 55, no. 3, pp. 496–509,Mar., 2008.

References 7

http://dx.doi.org/10.1007/978-1-4419-9539-1_5

http://dx.doi.org/10.1007/978-1-4419-9539-1_6

http://dx.doi.org/10.1007/978-1-4419-9539-1_5

http://dx.doi.org/10.1007/978-1-4419-9539-1_5

5. R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and

A. A. Abidi, “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,”

IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2860–2876, Dec. 2006.6. Vassilios, K. Vavelidis and N. Haralabidis et al, “A 65-nm CMOS Multistandard, Multiband

TV Tuner for Mobile and Multi-Media Applications,” IEEE J. Solid-State Circuits, vol. 43,pp. 1522–1533, Jul. 2008.

7. C. Andrews, A. Molnar, “A Passive-Mixer-First Receiver with Baseband-Controlled RF

Impedance Matching, <6 dB NF, and >27dBm Wideband IIP3,” ISSCC Dig. Tech. Papers,pp. 46–47, Feb. 2010.

8. H. Moon, S. Lee, S-C. Heo, H. Yu, J. Yu, J-S. Chang, S-I. Choi, B-H. Park, “A 23 mW Fully

Integrated GPS Receiver with Robust Interferer Rejection in 65 nm CMOS,” ISSCC Dig. Tech.Papers, pp. 68–69, Feb. 2010.

9. J. Borremans, G. Mandal, V. Giannini, T. Sano, M Ingels, B. Verbruggenn and J. Craninckx

“A 40 nm CMOS Highly Linear 0.4-to-6 GHz Receiver Resilient to 0dBm Out-of-Band

Blockers,” ISSCC Dig. Tech. Papers, pp. 62–63, Feb. 2011.10. A. Annema, B. Nauta, R. Langevelde and H. Tuinhout, “Analog Circuits in Ultra-Deep-

Submicron CMOS,” IEEE Journal of Solid-State Circuits (JSSC), pp.132–143, Jan. 2005.11. W. Sheng, A. Emira and E. Sanchez-Sinencio, “CMOS RF Receiver System Design:

A Systematic Approach,” IEEE Trans. on Circuits and Systems – I: Regular Papers, vol. 53,no. 5, pp. 1023–1034, May. 2006.

12. M. El-Nozahi, E. Sanchez-Sinencio and K. Entesari, “Power-Aware Multiband–Multistandard

CMOS Receiver System-Level Budgeting,” IEEE Trans. on Circuits and Systems – II: ExpressBriefs, vol. 56, no. 7, pp. 570–574, Jul. 2009.

13. B. Serneels and M. Steyaert, Design of High voltage xDSL Line Drivers in Standard CMOS,Springer, 2008.

14. STMicroelectronics technology profile in Circuits Multi-Projet (R) [Online]: http://cmp.imag.

fr/products/ic/

15. A. Youssef and J. Haslett, Nanometer CMOS RFICs for Mobile TV Applications, Springer,2010.

16. P.-I. Mak and R. P. Martins, “Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale

CMOS for Full-Band Mobile TV Tuners,” IEEE Transactions on Circuits and Systems – I:Regular Papers, vol. 56, no. 5, pp. 933–942, May 2009.

17. P.-I. Mak and R. P. Martins, “A 2 � VDD-Enabled Mobile-TV RF Front-End with TV-GSM

Interoperability in 1-V 90-nm CMOS,” IEEE Transactions on Microwave Theory andTechniques, vol. 58, pp.1664–1676, Jul. 2010.

18. P.-I. Mak and R. P. Martins, “High-/Mixed-Voltage RF and Analog CMOS Circuits Come

of Age,” IEEE Circuits and Systems Magazine, Issue 4, pp. 27–39, Dec. 2010.19. P.-I. Mak and R. P. Martins, “A 0.46 mm2 4-dB NF Unified Receiver Front-End for Full-Band

Mobile TV in 65 nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC),pp. 172–173, Feb. 2011.

20. P.-I. Mak and R. P. Martins, “A 0.46-mm2 4-dB NF Unified Receiver Front-End for Full-Band

Mobile TV in 65-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), pp. 1970–1984,Sept. 2011.

8 1 Introduction

http://cmp.imag.fr/products/ic/


Chapter 2

General Considerations of High-/Mixed-VDD

Analog and RF Circuits and Systems

2.1 Introduction

Instead of just following the rapid downsizing of VDD in technology scaling,

high-/mixed-voltage RF and analog CMOS circuits and systems have emerged as

a prospective alternative [1], to deal with the wireless technology trends such

as software-defined radio and cognitive radio; both are hungry for bandwidth and

dynamic range. An elevated VDD, or a hybrid use of I/O and core VDD’s,

in conjunction with optimum selection of thin- and thick-oxide MOSFETS open

upmuch new design possibilities in re-defining circuit topologies, whilemaintaining

most speed and area benefits of advanced fine linewidth processes [2]. Voltage-

conscious bias techniques and overdrive protection circuits are simple and low

overhead techniques to ensure the reliability of all devices. This chapter studies

the basic design concept, system design considerations and some state-of-the-art

circuit examples. A wide variety of analog and RF CMOS circuits featuring high-/

mixed-VDD is discussed. Those circuits comprise power amplifier, low-noise ampli-

fier, mixer, operational-amplifier-based analog circuits, sample-and-hold amplifier

and line driver. Reliability metrics such as oxide breakdown voltage, hot carrier

injection (HCI), time dependent dielectric breakdown (TDDB), and bias tempera-

ture instability (BTI) will be briefly addressed. The involved concepts and

techniques are generally extendable to different wireless and non-wireless

applications.

2.2 System Considerations

A general system architecture of mixed-voltage wireless system-on-chip (SoC) for

portable applications is depicted in Fig. 2.1. Thin-oxide transistors powered byVDD,c

(core VDD) exhibit the simplest structure to maximize the speed-to-power efficiency



9

of digital functions such as the digital signal processor. However, RF and analog

circuits such as theRFpower amplifier and the baseband operational amplifier are not

that efficient to work under the same VDD,c, which in the latest technologies, such as

the 65 and 40-nmCMOS, has values in the order of 1 to 0.9V [3], respectively. Such a

reduced VDD,c limits: (1) the overdrive voltages on transistors, and (2) the linear

output swing. Both of them can directly burden the performance optimization,

especially in multistandard wireless systems that demand high-linearity low-noise

wideband RF circuits [4]. Consequently, the exploration of a voltage islandingconcept in a power management unit would become essential for distribution of

the supply voltages to different RF and analog functions appropriately.

On the other hand, since many peripherals do not scale synchronously with the

silicon technologies, thick-oxide transistors are still kept available in advanced

processes to facilitate I/O communications. Thus, bringing thick-oxide transistors,

and their associated VDD,IO, into the RF and analog circuit design portfolio appears

to be a handy option to increase the design flexibility. Thick-oxide transistors can

be considered as devices from previous technology nodes: 0.25 and 0.18 mm.

Their reliable operating voltages are 2.5 and 1.8 V, respectively. Both are much

more comfortable values for RF and analog circuit design and can be easily

generated by a 3.6/3.7-V Li-ion battery. Obviously, circuits built with purely

thick-oxide transistors are not preferred as they cannot profit the speed and area

benefits of advanced processes. A hybrid use of thin- and thick-oxide transistors,

VDD,c and VDD,IO, emerges then as a new art in electronics that should be

adopted with a sensible balance. In the next sections, before the high-/mixed-

voltage-enabled circuits for wide types of RF and analog functions are described,

we will discuss the key device reliability concerns.

PowerManager

VDD,c

VDD,IO

Li-ion Battery2.7~ 4.2 V

1.2 V

2.5 V

RF & Analog

2.5 V I/O

Digital & 1.2 V I/O

Core Device(Thin-Oxide)

IO Device(Thick-Oxide)

LV Peripherals

HV PeripheralsPeripherals: SRAM, Flash, LCD

Display, LED, Key Pad, SIM Card….

SoC

Fig. 2.1 Increase the design flexibility of analog and RF circuits with more options on voltage

supplies and devices

10 2 General Considerations of High-/Mixed-VDD Analog. . .

2.3 Device Reliability in Ultra-scaled Processes

The technology Design Rule Manual provides the key device reliability concerns

including the absolute maximum rating (AMR), hot carrier injection (HCI),

electrostatic discharge (ESD), time dependent dielectric breakdown (TDDB), bias

temperature instability (BTI) and punchthrough effect. Complying with them in the

design indeed translates the term “design for reliability” into “voltage-conscious

design”, highly simplifying the design and verification methodologies [5]. Further-

more, in the topology formation phase, their implications to the circuits can be

easily identified. Other reliability issues related to interconnects and materials

like electromigration, stress-induced voiding and mechanical weakness are beyond

the scope of this work.

2.3.1 AMR

The AMR corresponds to the maximum voltage applied to a minimum-gate-length

device with no unrecoverable hard failure. AMR is concerned mainly with the gate-

oxide breakdown voltage as it is 3–4 times smaller than the junction breakdown

voltage [5]. A device biased close to the AMR limit may also lead to a deviation in

device parameters, degrading the long-term reliability. The tolerable AMR is

continuously reducing with the technologies (e.g., 1.6 V in 90-nm CMOS),

complicating the design of ESD protection in high-frequency pins.

2.3.2 HCI Lifetime

Degradation of MOS device characteristics occurs as a result of exposure to a high

VDS with a large drain current. Examples of degradation are a shift of VT and a

shorter gate-oxide breakdown lifetime. HCI normally happens in high-power

circuits such as the power amplifier, where the worst HCI bias conditions:

VDS≧VGS≧VT and VDS≧VDD/2 are concurrently satisfied. HCI degradation can be

reduced by lowering the drain current or increasing the device channel length (L).

2.3.3 TDDB

TDDB is the wear-out of insulating properties of silicon dioxide in the CMOS gate,

leading to the formation of a conducting path through the oxide to the substrate.

In order to protect the circuit against TDDB the catastrophic destruction of gate

oxides induced by the maximum DC gate oxide voltage at different temperatures

2.3 Device Reliability in Ultra-scaled Processes 11

must be considered. According to the maximum DC gate oxide voltages of 90 and

65-nm CMOS given in Table 2.1, NMOS has a higher voltage standing capability

than PMOS for all cases to prevent TDDB. Thus, NMOS is preferable when

considering TDDB in circuit design.

2.3.4 NBTI

BTI degradation happens under steady-state conditions. It is design dependent in

analog and RF circuits and primarily only PMOS devices are subjected to BTI

stress, namely negative BTI (NBTI). In a VDD-upscaled design, analyzing NBTI

involves detecting, in all modes of operation (DC and small signal), which PMOS

device is exposed to a peak or rms voltage value exceeding the standard VDD, which

is around 1 V in 90 and 65-nm CMOS. Thus, NMOS is also preferred when

implementing analog switches.

2.3.5 Punchthrough

Transistor gate length should be increased wherever possible to prevent the drain-

source depletion regions from punchthrough. In 90-nm CMOS, for a transistor

having an aspect ratio (W/L) of 10/0.1, a strong increment of drain current due to

punchthrough effect starts at a value of |VDS| around 2.3 V. Although the punch-

through effect is not intrinsically destructive it can accelerate, in the long term, the

gate oxide breakdown because of the induction of hot carriers. Punchthrough is a

critical concern in high-power circuits such as the power amplifier (PA), but it can be

avoided for low-power RF circuits such as the low-noise amplifier (LNA).

2.4 Extend the Voltage Capability of Thin-

and Thick-Oxide Transistors

With respect to the above-mentioned reliability concerns, individual thin (thick)-

oxide transistors can withstand maximally just one VDD,c (VDD,IO) voltage differ-

ence for any of the two terminals. In order to extend their voltage capability,

Table 2.1 Maximum DC gate oxide voltage to prevent TDDB

90 nm CMOS 65 nm CMOS

45�C 150�C 45�C 150�CGP NMOS 1.43 V 1.28 V GP NMOS 1.35 V 1.23 V

GP PMOS 1.29 V 1.17 V GP PMOS 1.23 V 1.11 V


stacking of devices can be applied. The concept is illustrated in Fig. 2.2. In steady

state, the possible structures can be a stack of two (or more) thin-oxide transistors,

thick-oxide transistors, or a hybrid use of both. Generally, the voltage capability

across the drain and source terminals can be multiplied by the number of stacked

transistors. One basic request of this technique is that the bulk should be tied to the

source terminal to avoid overstress between them, implying the need of a triple-well

process for NMOS to have an isolated bulk.

Among the three structures shown in Fig. 2.2 only pure stack of thin-oxide

transistors and a hybrid stack of thin- and thick-oxide transistors are relevant to

balance the speed and voltage capability. A pure stack of thick-oxide transistors

cannot take advantage of the area and speed features of advanced technologies.

In the hybrid case the thin-oxide transistor can serve as the amplification device

for minimization of the loading effect to the previous stage. The thick-oxide

transistor serves as the cascode device thus increasing the voltage capability.

High-/mixed-voltage RF and analog circuits are generally based on these two

stacking structures.

In addition to steady-state overstress, transient-state overstress should not be

allowed too. Depending on the nature of the signal processing, large-signal circuits

(e.g., line driver) requires checking the trajectory of all nodes. Alternative solutions

are to employ voltage-biased and self-biased circuit topologies; both of them

have the benefit that the internal node voltages can be easily controlled during

power up/-down transients. Examples of the techniques will be discussed in the

next section.

VDD,c

VDD,c

VDD,c

VDD,IO

VDD,IO

VDD,IO

VDD,IO

VDD,c

VDD,c

VDD,c

VDD,c

VDD,c

VDD,c

VDD,c

VDD,c

VDD,c

VDD,IO

VDD,IO+VDD,c

VDD,IO

VDD,IO

VDD,IO

VDD,IO

VDD,IO

2VDD,IO2VDD,c

VDD,IO

VDD,IO

Thin-Oxide MOS Thick-Oxide MOS

Fig. 2.2 Extending the voltage capability of thin-and thick-oxide transistors through stacking

2.4 Extend the Voltage Capability of Thin- and Thick-Oxide Transistors 13

2.5 High-/Mixed-Voltage Building Blocks

2.5.1 Power Amplifier and Wideband Balun-LNA(High-VDD þ Mixed-Transistor)

VDD-upscaling circuits have appeared in the literature for many years. The most

common application is on the PA. As shown in Fig. 2.3a a hybrid use of thin- (M1)

and thick-oxide device (M2) in cascode permits using of a higher VDD beyond the

standard value to maximize the possible output power in 0.13-mm CMOS [6].

The reliability test should be under the maximum output power level with the

entailed modulation (e.g., 64QAM OFDM), to ensure the steady-state overstress

conditions are met (i.e., │VGD,rms│, │VGS,rms│ and │VDS,rms│ have to be less than VDD

of each device type). M2 entails a triple well for independent bulk-source

connection.

On the other hand, in order to protect M1 from overstressing automatically

during the power-up/down transients, we propose to add a thick-oxide device

Mpt1 can be added to the Vx node. Its size is not critical as its aim is to ensure Vx

< VDD,c when VDD,elevated is activated first and can be turned off when VDD,c has

caught up automatically.

Mixed-transistor circuit topologies also find applications in recent small-signal

linearity-demanding wireless circuits and systems [7–9]. A 90-nm CMOS ultra-

wideband balun low-noise amplifier (LNA) [7] based on an elevated VDD (2.5 V)

VDD,elevatedVDD,elevated

VDD,elevated

VDD,elevated

Vb5VDD,c

VDD,c

VDD,elevated

VDD,C

Vb1

Vin

Vb

Vb4Vin

Mb1

Rb Vx

Vx

Vb2

LLLL

LL1

RLRL

M3

R2

R1

M2

M1

M1

M2

M4

C1

Voutn

Vout Voutp

Ib

C1

IMpt1

IMpt1

Automatic Overdrive Protection for M1

0t

V/I When VDD,elevated ramps upbefore VDD,c, M1 is cutoff

Mpt1,2 ensures Vx<VDD,c

Mpt1 is cutoff when innormal operation

Mpt1

a b

Fig. 2.3 RF circuits using an elevated VDD. (a) Power amplifier with automatic protection of M1

from being overstressed. (b) Wideband balun LNA


increases the output dynamic range while allowing more voltage drop at the

resistive load RL (Fig. 2.3b), achieving both high gain and high linearity but a

smaller output bandwidth due to an increased RL. A gain-peaking inductor LL can

be exploited to extend the output bandwidth.Mpt1 in Fig. 2.3a can also be applied to

this topology to protect M1 and M3.

2.5.2 Passive Mixers (High-VDD þ Thin-Oxide Transistor)

A passive current-mode downconversion mixer can be implemented with a resistor

Rff in-series with a MOS switch, and terminated with a virtual ground through the

use of an operational amplifier (OpAmp). The OpAmp provides linear I-V conver-

sion and first-order lowpass filtering at the output. In order to achieve a rail-to-rail

output swing the output dc-level should be at half of the supply. For a generic

1 � VDD design as shown in Fig. 2.4a, the clocked MOS switch can only have

1xVDD

1xVDD

2 xVDD

1xVDD

2xVDD

0

Vout

Vout

Vin

Vin

VSS

VSS

Rff

Rff

Rfb

Cfb

Rfb

Cfb

VCM(0.5xVDD)

VCM(1xVDD)

0.5xVDD-0.5xVDD

VGS =

1xVDDVGS =

(VDC = 0.5xVDD) (VDC = 0.5xVDD)

(VDC = 0.5xVDD)

(VDC = 1xVDD)

(VDC = 1xVDD)(VDC = 1xVDD)

0

a

b

Fig. 2.4 Downconversion passive mixers: (a) 1 � VDD design. (b) 2 � VDD design

2.5 High-/Mixed-Voltage Building Blocks 15

a maximum overdrive voltage of 0.5 VDD. However, by doubling the supply to

2 � VDD as shown in Fig. 2.4b, the overdrive voltage of the MOS switches is

maximized to the technology allowable limit, i.e., 1 � VDD. This act significantly

reduces the size of the MOS switch and its induced nonlinearity. The design of

2 � VDD OpAmp will be presented later in this chapter.

Another type of 2� VDD passive mixer with a mixer driver is shown in Fig. 2.5a.

A 2 � VDD 90-nm CMOS cascode amplifier serves as the mixer driver improving

the linearity and reverse isolation but the output dc-level is up-shifted to 1.5� VDD.

Under a 1.5 � VDD dc-level PMOS is preferred as the mixing MOS to maximize

the overdrive voltage. The unmatched input and output dc-levels of the OpAmp

require an extra bias current Ib to sink out the excess dc-current in the feedback

loop. Since Ib depends on the absolutely value of Rfb, a resistance-tracking

0

=

3R

R

Vout

lb

Vin

a

b

2xVDD

2xVDD

2xVDD

Rfb

Rfb

3Rfb

ID

Ib

R2

M2

M1

R1

Cfb

VSSVSS

VSS

VSSVSS

VSS

VCM(1.5xVDD)

(VDC ª 1xVDD)

(VDC ª 1.5xVDD)

(VDC ª 0.5xVDD)

(VDC ª 0.5xVDD)

(VDC ª 0.5xVDD)

1.5xVDD

1.5xVDD

0.5xVDD

1xVDDVGS =

2xVDD

0.5xVDD

Fig. 2.5 (a) 2 � VDD passive mixer with mixer driver and its (b) Ib generation circuit


bias circuit can be utilized for this purpose. As shown in Fig. 2.5b, an error

amplifier together with a 3Rfb and a current mirror generates the required value of

Ib ¼ 0.5 � VDD/Rfb. It should be noted that no device is under overstress.

2.5.3 Differential Pair (High-VDD þ Thin-Oxide Transistor)

A 3.3-V 0.18-mmCMOS two-stage operational amplifier (OpAmp) was demonstrated

in [10]. The concept of extending the voltage is related with the addition of

extra cascode transistors, boosting the voltage-withstand capability from 1.8 to

3.3 V. The input stage is of particular interest as it is based on a high-voltage-

enabled differential pair using a current mirror load. In order to understand the

performance difference in an advanced process, we re-designed and compared

only the input stage of the OpAmp (output stage is more customized) in 65-nm

CMOS, as shown in Fig. 2.6a and b. Table 2.2 summarizes the simulation

VinnVinp Vinp

a b

1xVDD

2xVDD

Vbp1

Vbp1

Vbp2

VinnM2

M2

M4

M4

M5 M5 M6

M7 M8

M3M3

M1

M1

CLCL

(VDC ª 0.3xVDD)

(VDC ª 1xVDD)

(VDC ª 0.55xVDD)

(VDC ª 0.7xVDD)

(VDC ª 1.5xVDD)

Fig. 2.6 Typical OpAmp’s input stage: (a) 1 V (typical) (b) 2 V-enabled

Table 2.2 Comparison between 65-nm1-V and 2-VOpAmp’s input stagewith a current-mirror load

Parameters 1 V OpAmp’s input stage 2 V OpAmp’s input stage

Technology 65 nm CMOS

Transistor type 1 V GP NMOS and PMOS

Power consumption 0.4 mW

Load CL 1 pF

DC gain 10 dB 18.4 dB

Unity-gain frequency 318.5 MHz 191 MHz

Phase margin 107� 95�

HD3 (@ 1 MHz input) 45.6 dB at 125 mVpp Output 44.3 dB at 330 mVpp Output

Output noise voltage

(@ 100 MHz)

14.6 nV/sqrtHz 14.7 nV/sqrtHz


results showing that the dc gain and linear output swing of the 2-V design are

8.4 dB and 2.6 times better than its 1-V counterpart, respectively. On the other

hand, the unity-gain frequency is reduced by 40% due to the additional parasitic

poles in the 2-V design. Thus, when the speed is not that demanding, a 2-V-

enabled OpAmp is better since OpAmp-based circuits such as the active filter

are normally for baseband operation.

2.5.4 Recycling Folded Cascode Operational Amplifier(High-VDD þ Thin-Oxide Transistor)

Based on the above observation, a 2 � VDD-enabled recycling folded cascode

(RFC) OpAmp [10] is proposed and compared with its 1 � VDD RFC counterpart

[11] and its original 1 � VDD folded cascode (FC) counterpart. Without resorting

from a two-stage or multi-stage OpAmp, this 2 � VDD-enabled RFC OpAmp can

offer sufficient open-loop gain and linear output swing to realize high-precision

analog functions in a single stage. The reliability of the circuit is ensured via

voltage-conscious biasing and gate-drain-source engineering.

The single-stage FC OpAmp is shown in Fig. 2.7. Its performance can be

enhanced with the RFC technique [11] as shown in Fig. 2.8. It employs M1b, M2b,

M11, M12, M3b andM4b to improve concurrently the gain and speed. By controlling

the current mirror gain K, the small signal transconductance can be boosted,

M4M3

M5 M6

M8

M9M10

M7M1

Vbp1

Vbn2

Vbp2

Vcmfb

Vbn1

M0

M2

GND

Vinp Vinn

VOn

VDD

VOp

lblb2lb

2lb2lb

Fig. 2.7 Typical RFC OpAmp (1 � VDD design)


i.e., gmRFC ¼ gm1a (1 + K). Thus, under a fixed power budget, the RFC shows

a higher gain-bandwidth product (GBW) than the conventional FC structure.

Furthermore, the RFC OpAmp also exhibits larger output resistance than its FC

counterpart, leading to further gain enhancement.

The proposed 2 � VDD RFC OpAmp is depicted in Fig. 2.9. The aim of

doubling the supply is to enhance certain performance metrics that cannot be

simply obtained by doubling the bias current at 1 � VDD under the same power

budget. By appropriately doing transistor stacking and biasing, the output resis-

tance of the devices can be boosted while the voltage stress on them can also be

shared to meet the reliability limits. For instance, under a 2 � VDD, M00 can be

added to share the voltage stress on the current source M0 and improve its output

resistance, thereby the OpAmp’s common-mode rejection ratio (CMRR). On the

other hand, the current mirrors (M3a, M3b, M4a, M4b) are cascoded with (M3a0,

M3b0, M4a0, M4b0), whereas the current sources of the output stage (M11, M12) are

cascoded with (M9,M10). Thus, the overall DC gain should be enhanced due to the

boosted output resistance RO,RFC-2V by comparing it with the RO,RFC-1V as

summarized in Table 2.3.

The bias and common-mode feedback circuits (CMFB) are tailored to include

extra cascode devices to ensure all node voltages are within the reliability limits as

shown in Fig. 2.10.

M7

K:1

(K-1)Ib /2(K-1)Ib /2

1:K

GND

1xVDD

M4aM3a M3b M4b

M2b M2aM1a M1b

M0

M12

M5 M6

M11Vbn2

Vbn2

M8

M9 M10Vcmfb

VOpVOn

Vinn

2lbVbp1

Vbp2

Vinp

Fig. 2.8 Typical RFC OpAmp (1 � VDD design)


In order to ensure the reliability and performance of the 2� VDD RFC OpAmp, it

should be tested in a closed-loop way based on the intended applications. Here, a

first-order active-RC circuit with unity gain is assumed, as shown in Fig. 2.11.

To check the reliability of all devices inside the OpAmp, a large square-wave

input at a common-mode voltage of 1 V is applied. Figure 2.12 shows the VGS–VGD

relationship at an input swing of 1.2 Vpp. Since the circuit is differential, only

half-circuit results are shown. It can be observed that both VGS and VGD vary within

the ±1-V boundary and the variation is indeed small. Next, the VDS trajectory is

checked. Figure 2.13a–c show that the VDS, in a period of square-wave input under

an input swing of 1.2, 1.6 and 2 Vpp, respectively. When the input swing is 1.2 V, all

VDS are within the ±1-V boundary. When the input swing is enlarged, some of the

VDS exceed 1 V, reached 1.13 and 1.25 V for 1.6 and 2-Vpp inputs, respectively.

According to the lifetime targets discussed in [12], VDS > 1 V may still be

acceptable for some applications.

In order to compare the performances between 1 � VDD FC, 1 � VDD RFC and

2� VDD RFC OpAmps fairly, they are designed under the same power budget. The

simulated open loop DC gain (Fig. 2.14) of the FC, 1-V RFC and 2-V RFC is

45.3 dB, 54.0 dB and 72.8 dB respectively, which indeed demonstrates the

enhanced output impedance of the 2-V RFC and the enhanced gain of the 1-V

RFC over the FC is apparent and within the expected range of 8–10 dB.

K:1 1:K

GND

M4aM4bM3a M3b

M3a’ M3b’ M4b’ M4a’Vbn0 Vbn0

Vinp

M2b M2aM1a M1b

Vinn

M0

M0’

lb

Vbp1′

Vbp1(K-1)Ib /4(K-1)Ib /4

M9 M10Vcmfb

M7’ M8’

Vbp3

M7 M8Vbp2

M5 M6Vbn2

VOpVOn

2xVDD

Fig. 2.9 Proposed 2 � VDD-enabled RFC OpAmp


Table

2.3

Designequationsof1�

VDDFC,RFCand2�

VDDRFCOpAmps

FC

1-V

RFC

2-V

RFC

Current

I D¼

1 2mC

oxW LðV

GS�VTÞ2

Transconductance

Gm;FC¼

gm1

Gm;1V�R

FC¼

gm1að1

þKÞ

Gm;2V�R

FC¼

gm1að1

þKÞ

Outputim

pedance

RO;FC�

½ðgm5þgmb5Þr o

5

ðr o1jjr

o3Þ�jjðg

m7r o

7r o

9Þ

RO;1V�R

FC�

½ðgm5þgmb5Þr o

5ðr o

1ajjr

o3aÞ�

jjðg m

7r o

7r o

9Þ

RO;2V�R

FC�

fðg m

5þgmb5Þr o

5½ðr

o1ajjðg m

3a0

þgmb3

a0Þr o

3a0 ro3aÞ�g

jjðg m

7r o

7g m

70 ro7

0 ro9Þ

Gain

Av;FC¼

Gm;FC�R

O;FC

Av;1V�R

FC¼

Gm;1V�R

FC�R

O;1V�R

FC

Av;2V�R

FC¼

Gm;2V�R

FC�R

O;2V�R

FC

GBW

GBW

FC�

Gm;FC

CL

GBW

1V�R

FC�

Gm;1V�R

FC

CL

GBW

2V�R

FC�

Gm;2V�R

FC

CL

Outputsw

ing

VO

Swing;FC¼

2�½1�ðV

ov3þ

Vov5þjV

ov7jþ

jVov9jÞ�

VO

Swing;1V�R

FC¼

2�½1�ðV

ov3aþ

Vov5þjV

ov7jþ

jVov9jÞ�

VO

Swing;2V�R

FC¼

2�½2�ðV

ov3a0þVov3aþVov5

þjV

ov7jþ

jVov70 jþ

jVov9jÞ�

Slew

rate

SRFC¼

I b CL

SR1V�R

FC¼

KI b

CL

SR2V�R

FC¼

KI b

2CL

Thermal

noise

v2 iT;FC¼

8k BTg

g m1�½1

þgm

3

gm1þ

g m9

g m1��Df

v2 iT;1V�R

FC¼

8k BTg

g m1að1þK

Þ�½ð1

þK2Þ

1þK

þgm3a

gm1aþ

1ð1þK

Þg m

9

gm1a��Df

v2 iT;2V�R

FC¼

8k BTg

gm1að1þK

Þ�½ð1

þK2Þ

1þK

þg m

3a

g m1aþ

11þK

g m9

gm1a��Df

Flicker

noise

v2 if;FC¼

KFP

m PC2 oxW

1L1f½1þ2KFN

KFPðL 1 L

3Þ2

þðL 1 L

9Þ2 �

�Df

v2 if;1V�R

FC¼

KFP

m PC2 oxW

1aL1að1þK

Þf½ð1

þK2Þ

ð1þK

Þþ

KKFN

KFPðL 1

a

L3aÞ2

þðK

�1Þ

ð1þK

ÞðL1a

L9Þ2 �

�Df

v2 if;2V�R

FC¼

KFP

m PC2 oxW

1aL1að1þK

Þf½ð1

þK2Þ

ð1þK

ÞþK

KFN

KFPðL 1

a

L3aÞ2

þðK

�1Þ

ð1þK

ÞðL1a

L9Þ2 �

�Df

Power

P¼

I Total;FC�1

P¼

I Total;1V�R

FC�1

P¼

I Total;2V�R

FC�2


As for the GBW, the FC, 1-V RFC and 2-V RFC is 68.2 MHz, 157.8 MHz and

97.5 MHz, The GBW of the 2 � VDD design, as expected, is less than to that in

the 1 � VDD design under the same power budget, but is fairly adequate for most

analog functions with signal bandwidth of less than 10 MHz. The phase margin

simulated for FC, 1-V RFC and 2-V RFC is 86.6�, 60.9� and 70.7� at their

respective GBWs. The phase margin of 1-V RFC is smallest since it has the largest

GBW, and has more poles compared to FC. The 2-V RFC shows less phase

margin compared to FC, since the larger GBW and the multiple poles added by

2xVDD

GND

Vref=1V

Ib

CMFBBias circuit

Vbn1

Vbn2

Vbp3

Vbp1

Vbp2

VBp1’

Vcmfb

VOutn

VOutp

Fig. 2.10 Bias and CMFB circuits for the 2 � VDD-enabled RFC OpAmp

R

R

R

R

Vinp

Vinn

C1 C1

C2

C2

C1 C1

Voutp

Voutn

Fig. 2.11 A unity-gain amplifier is used to assess the performance and reliability of a 2 � VDD-

enabled RFC OpAmp. R ¼ 600 kO, C1 ¼ 2 pF and C2 ¼ 4 pF. The input and output dc-levels are

1 � VDD to maximize the signal swing and allow ease of cascading


-0.75

0.0

0.75

1.5

-1.50.0 1.0u0.5u 1.5u 2.0u

Time [S]

0.95

: M0 : M0' : M2b : M2a : M4b’ : M4a’: M4b : M4a : M6 : M8 : M8’ : M10



1.2Vpp Input Swing 1.6Vpp Input Swing

2VppInput Swing

-1.50.0 2.0u1.0u0.5u 1.5u

Time [S]

0.0

1.5

1.13

-0.75

0.0

0.75

1.5

-1.50.0 1.0u0.5u 1.5u 2.0u

Time [S]

1.25

VD

S[V

]

VD

S[V

]

VD

S[V

]

a b

c

Fig. 2.13 VDS variation versus time at an input swing of (a) 1.2 V, (b) 1.6 V and (c) 2 V. The

notations correspond to Fig. 2.9. The maximum Vds is within 0.95/1.13/1.25 V, respectively

-0.5

0

0.5

1

M0 M0' M2b M2a M4b'

M8'

M4a'

M4b M4a M6 M8

-1 -0.5 0 0.5 11

M10

VGS[V]

VG

D[V

]

Fig. 2.12 2 � VDD-enabled RFC OpAmp’s VGS–VGD trajectories when a square-wave input is

applied with a signal swing of 1.2 Vpp


cascode and current mirror. Nevertheless, neither amplifier shows any ringing in the

transient performance.

The linearity of the OpAmps is assessed as follows: a two-tone test centered

around 500 kHz (250 mVpp at 450 kHz and 250 mVpp at 550 kHz) was applied to

the three OpAmps, and their results are shown in Fig. 2.15a–c. The third intermod-

ulation distortion, IM3, is �49.7 dB (1-V FC), �57.2 dB (1-V RFC) and �76.5 dB

(2-V RFC), as shown in Fig. 2.16. For an analog-to-digital converter, the achieved

gain of the 2-V RFC OpAmp corresponds to>11-bit resolution for an output swing

as large as 0.8 Vpp. When they are in a unity-gain configuration, Fig. 2.17 confirms

the high gain accuracy of the 2-V RFC OpAmp over such a wide output swing.

The input-referred noises of the three OpAmps are shown in Fig. 2.18. When

integrated over a bandwidth of 1 Hz to 100 MHz, the noises are 74.4 mVrms (FC),

64.3 mVrms (1-V RFC) and 83.2 mVrms (2-V RFC). The latter is actually inferior

103 104 105 106 107 108 109

103 104 105 106 107 108 109

-40

-20

0

20

40

60

80

Frequency (Hz)

Mag

nitu

de (

dB)

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Pha

se (

deg)

FC1-V RFC2-V RFC

FC1-V RFC2-V RFC

a

b

Fig. 2.14 (a) Gain and (b) phase responses of 1-V and 2-V RFC OpAmps


2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5x 105

x 105

x 105

-100

-80

-60

-40

-20

0

Frequency (Hz)

FC

- A

mpl

itude

(dB

) -12.239

-61.9072

2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5-100

-80

-60

-40

-20

0

Frequency (Hz)

1-V

RF

C -

Am

plitu

de (

dB)

-12.1225

-69.3184

2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

2-V

RF

C -

Am

plitu

de (

dB)

-12.0629

-88.595

a

b

c

Fig. 2.15 Two tone FFT spectrums of (a) the FC, (b) the 1-V RFC and (c) the 2-V RFC for a

0.5 Vpp signal centered at 500 kHZ and separated by 100 kHz


comparing with the 1-V ones. Table 2.4 summarizes their simulation results.

It concludes that the 2 � VDD RFC OpAmp is more efficient in improving the

gain precision and linearity of analog circuits. However, when GBW and noise are

the priorities, the 1-V RFC OpAmp becomes more superior. Voltage-oriented

OpAmp design, therefore, improves the performance metrics very different from

the current-oriented ones in nm-length CMOS processes.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 210

20

30

40

50

60

70

80

Output Voltage (V)

Gai

n (d

B)

FC1V-RFC2V-RFC

Fig. 2.16 Open-loop gain versus output voltage. The common-voltage voltages are Vcm, FC ¼0.5 V, Vcm,1-V RFC ¼ 0.5 V and Vcm,2-V RFC ¼ 1 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

0.2

0.4

0.6

0.8

1

Output Voltage (V)

Gai

n (V

/V)

FC1V-RFC2-V RFC

Fig. 2.17 OpAmps in a unity gain configuration. The common-voltage voltages are Vcm,1-V FC ¼0.5 V, Vcm,1-V RFC ¼ 0.5 V and Vcm,2-V RFC ¼ 1 V


2.5.5 OpAmp-Based Analog-Baseband Circuits(Mixed-VDD þ Mixed-Transistor)

As shown above, a 2 � VDD recycling folded-cascode (RFC) OpAmp can achieve

better performances than its 1 � VDD counterpart such as DC gain and close-loop

linearity under a similar power budget. The applications of such an OpAmp are

extensive, as shown in Fig. 2.19. Depending on the selected impedances of Zfb and Zffseveral types of continuous-time and discrete-time circuits can be synthesized. Of

course, in some cases, it will need to interface between standard-VDD and high-VDD

building blocks.As shown inFig. 2.20a, in a transmitter the use of 1�VDD and2�VDD

OpAmp allows a progressively increase of linear output swing. The level shifter is a

current source Ib. Another case is shown in Fig. 2.20b for receiver, a 2� VDD OpAmp

(at the front) offerswider linear output swing to handle the out-of-channel interferer 1�VDD OpAmp (at the back) easily interfaces with 1 � VDD ADC. Again, Ib allows

seamless cascade of blocks having different common-mode voltages.

100 102 104 106 108

10-10

10-12

10-16

10-18

10-14

Frequency (Hz)

Spe

ctra

l Den

sity

(V

2/H

z)FC1-V RFC2-V RFC

Fig. 2.18 Input referred noise spectral power density

Table 2.4 Performance summary for 1-V and 2-V RFC OpAmps

Parameter FC 1-V RFC 2-V RFC

Power (bias current) [mA] 600 600 300

DC gain [dB] 45.3 54.0 72.8

GBW [MHz] 68.2 157.8 97.5

Open loop PM [deg] 86.6 60.9 70.7

Capacitive load [pF] 5.0 5.0 5.0

Slew rate (average) [V/ms] 53.3 96.6 65.4

1% settling time [ns] 24.8 9.8 18.0

Gain precision (closed loop, ideal case is 1) 98.6% 99.4% 99.8%

IM3, 0.5 Vpp at 0.5 MHz [dB] �49.7 �57.2 �76.5

Input referred noise (1 Hz–100 MHz) [mVrms] 74.4 64.3 83.2


The Weighted Summer

Lowpass Filter

Current-Mode Mixer-+

-+

-+

Amplifier (or Buffer)

-+

Highpass Filter

-+

2xVDD

VSSVCM

Vin Vout(VDC = 1xVDD)

(VDC = 1xVDD)

Zfb

Zff

(1xVDD)

-

+

Fig. 2.19 Analog-baseband circuits based on a 2 � VDD OpAmp

Ib

Ib

Ri /2

Ri /2

Ri /2

Ri /2

Vx

Ri /2 Vx

0.5V1V

DAC

1xVDD

1xVDD

1xVDD-Vx

VSS

VSS VSS

VSS

VSS

VCM(0.5xVDD)

VCM(0.5xVDD)

VSSVCM(1xVDD)

VCM(1xVDD)

Signal

InterfererFullSwing

FullSwing

LNTAPassiveMixer

ADC

Signal

Interferer

(VDC ª 0.5xVDD)

(VDC ª 0.5xVDD) (VDC ª 0.5xVDD)

(VDC ª 0.5xVDD)

(VDC ª 0.5xVDD)

(VDC ª 1xVDD)

(VDC ª 1xVDD)

2xVDD

Rfb

Cfb

2xVDD

Rfb

Cfb

1xVDD

Rfb

Cfb

1xVDD

Rfb

Cfb

Vout

ID =

Ri /2

1xVDD-VxID =

a

b

Fig. 2.20 Level shifting: (a) 1 � VDD to 2 � VDD. (b) 2 � VDD to 1 � VDD


After lowpass filtering, the baseband signal can be driven off-chip or to the

analog-to-digital converter (ADC). In either case, a high-VDD source follower with

a thick-oxide MOS can be used as the buffer, as compared in Fig. 2.21a and b for

mixed-VDD and standard-VDD design. The mixed-VDD design inherently offers

level-shifting, avoiding any AC-coupling circuit that is area hungry at baseband,

i.e., the highpass cutoff frequency should be sufficiently low to prevent notching the

signal spectrum.

2.5.6 Low-Dropout-Regulator (Mixed-VDD þ Mixed-Transistor)

Low-dropout regulators (LDOs) are widely employed in SoC for improving the

power-supply rejection ratio (PSRR) of the internal circuit. PMOS-based LDO

(Fig. 2.22a) is more popular than its NMOS counterpart (Fig. 2.22b) for its lower

dropout voltage property. The main issue of PMOS-based LDO is the necessity of

an external big capacitor to ensure the stability. Such a requirement significantly

increases the manufacturing cost and pin counts because many LDOs are entailed

for a SoC. The NMOS-based LDO, on the other hand, is free from such a request

(i.e., cap-less) and features better stability and PSRR+. The key appeal is that VG

will need to be greater VDD12, which is not normally possible in a single-VDD

design. In a mixed-VDD design, VG > VDD12 can be solved as shown in

Fig. 2.22c. The abovementioned benefits of NMOS-based LDO are retained,

while an add-on benefit is that the maximum Vout,max can now be VDD12 (i.e., no

dropout voltage!). The drawback is that every 1-mA current to ZL yields 1.3-mW

power loss in the pass transistor. Thus, the technique befits better low-power high-

sensitivity circuits.

In addition to VDD-LDO, ground-LDO is becoming more crucial to desensitize

low-noise high-DR circuits, e.g., voltage-controlled oscillator (VCO), from sub-

strate noise coupling in a noisy SoC environment as shown in Fig. 2.23. Due to the

Vout,bufVout,buf

Thick-OxideSource Follower

Thick-OxideSource Follower

1xVDD 1xVDD1xVDD 2xVDD

R1 R1VDCª0.5xVDD VDCª0.5xVDD

VDCª0.5xVDDVDCª1xVDDM2

M2

M1 M1M3 M3

VoutVout

CDC

RDC

a b

Fig. 2.21 (a) Standard-VDD and (b) mixed-VDD source follower serves as a buffer


presence of VDD25, VDD-LDO and ground-LDO can be jointly employed. The VCO

may employ a thick-oxide varactor or MOSFET capacitor as the frequency tuning

element, covering potentially a wider tuning range. Proper biases can ensure the

internal rail sufficiently large for the core circuit, surpassing the voltage-headroom

NMOSVG

Cap-less

Stability & PSRR +

PMOS

ZLCext

ZL

OTA OTAVref Vref

VG <VDD12

VG>VDD12 is solved

VG>VDD12

VG

VG

VG

External Cap

NMOS

Cap-lessStability & PSRR+

OutputStage

Vout,max=VDD12-VDSVout,max =VDD12-VDS

Vout,max =VDD12

Vout Vout

ZL

Vout

VDD25VDD25

VDD12 VDD12

VDD12OTA

a b

c

Fig. 2.22 LDO with (a) a PMOS pass transistor. (b) a NMOS pass transistor, and (c) mixed-

voltage design on a NMOS pass transistor

NMOS

Core Circuit

VDD,i

VDD,i

Mp1

Mn1 Mn2

Mp2OTA

PMOS

VGND,i

VGND,i

Vctrl

1.2V

0.65V

0.65V

~0.25V

~2.25V

0.65V

1.85VL

CC

Sufficient Internal Rail

Cap-lessStability & PSRR+/-

Thick-Oxide Varactor/MOS capacitor

VDD25VDD25

VDD25

Vref1

Vref2

VG1

VG2OTA

Fig. 2.23 Mixed-voltage mixed-transistor LDO for both positive and negative rails


tradeoff when employing LDO for PSRR improvements. Again, the drawback is

that every 1-mA current to ZL yields 1.3-mW power loss in the two pass transistors.

2.5.7 Sample-and-Hold Amplifier (High-VDD þ Mixed-Transistor)

Discrete-time analog-baseband circuits not only can benefit from the area and

power savings of a VDD-elevated OpAmp, but also the extra voltage headroom to

improve the linearity of sampling. Shown in Fig. 2.24a and b are two sample-and-

hold circuits with 1-V and 2.5-V supplies, respectively. At a 100-MHz sampling

rate, to sample-and-hold a 10-MHz 0.6-Vpp sinusoidal input at a dc level that is

midway to VDD/2, the former, based on thin-oxide MOS with a minimum channel

length of 60 nm can achieve 1.18-GHz tracking bandwidth (BW) but the HD3 is

limited to 31.5 dB. Alternatively, the latter based on thick-oxide MOS with a

minimum channel length of 280 nm can achieve 50-dB HD3, but the tracking

BW is almost halved. Then, this speed-linearity tradeoff is subject to applications

and can be flexibly selected in advanced processes, as both thin- and thick-oxide

devices are available. Since the clock is normally synthesized with the thin-oxide

circuit for power and area reduction, a clock level shifter, as shown in Fig. 2.25,

would be required for the 2.5-V design. Thus, power and speed overheads must be

considered.

1V

0V

0.8V0.5V

10/0.06

0.2V

1pF

10MHz

100MHz2.5V

0V

1.55V1.25V

10/0.28

0.95V

1pF

10MHz

100MHz

Output HD331.5 dB

Output HD350 dB

1.18 GHzTracking BW

0.57 GHzTracking BW

a b

Fig. 2.24 Sample-and-hold circuits: (a) 1-V design. (b) 2.5-V design

2.5V 2.5V

0V 0V

1V0

2.5V0

1V

0V

1V PLL

Fig. 2.25 Clock level shifter for 1–2.5 V


2.5.8 Line Driver (High-VDD þ Thin-Oxide Transistor)

Reference [13] has demonstrated that a 5.5-V line driver realized in a standard 1.2-V

0.13-mmprocess is capable to attain state-of-the-art performances with no reliability

degradation. Figure 2.26 depicts the block schematic of such a central office (CO)

line driver topology (the output stage), where a 2 � VDD,c supply is adopted for

simplicity. The input signal is delayed (to synchronize with the upper path) and

buffered to drive the NMOS device M1, besides being also level-shifted up to drive

the PMOS device M4. The cascode transistors M2 and M3 serve to increase the

voltage-withstand capability. With a 2� VDD,c supply, the gate-bias voltages ofM2

andM3 are very simple, i.e., 1� VDD,c to ensure no overstress in both high- and low-

state outputs (Fig. 2.27). For a higher VDD multiplying design (i.e., greater than 2),

M1

M2

M3

M4

1xVDD,c1xVDD,c

1xVDD,c

2xVDD,c

2xVDD,c

2xVDD,c2xVDD,c2xVDD,c

1xVDD,c1xVDD,c

1xVDD,c

1xVDD,c

1xVDD,c

0

LevelShifter

0 0

Vin

Vout

0

0

Delay

Fig. 2.26 CO line driver with a 2 � VDD,c

0V

0V(Low)

0V

2xVDD,c 2xVDD,c

1xVDD,c

2xVDD,c

2xVDD,c

1xVDD,c

2xVDD,c(High)

1xVDD,c

1xVDD,c

1xVDD,c

1xVDD,c

1xVDD,c

1xVDD,c

M1

M2

M3

M4

M1

M2

M3

M4

Fig. 2.27 The internal node voltages when the output stage is delivering high and low-state

outputs showing all voltage differences are within 1 � VDD,c


a dedicated bias circuit for each cascode transistor is necessary to guarantee no

device is under overstress in both steady-state and transient operations. The circuit

needs two supplies 1 � VDD,c and 2 � VDD,c. The application-related performance

metrics are available elsewhere [13].

This 2 � VDD line driver has been recently modified to work on a 90-nm CMOS

switched-capacitor power amplifier [14] and 32-nm CMOS class-D power amplifier

[15]; both demonstrate state-of-the-art performances, further proving the impor-

tance of high-/mixed-VDD designs in nanoscale CMOS.

2.6 Summary

High-/mixed-voltage techniques feature high potential to boost up the

performances of RF and analog circuits without degrading the reliability. Bringing

the VDD,IO and thick-oxide transistors into the RF and analog circuit design portfo-

lio does not by itself require any add-on resource or technology option (at least up to

now), but it effectively increases the design flexibility. Circuit techniques play a

key role in this development, and are therefore long-term reusable when the

technology continues to advance.

This chapter only serves as a glimpse of this research trend and guiding direc-

tion, while highlighting the necessary gate-drain-source engineering skills to take a

broader advantage of available techniques. One of the critical points would be to

guarantee the circuit reliability compliance with the foundry guidelines when

considering device size and the potential adopted bias in transient and steady states.

Advantages of high-/mixed-voltage analog and RF CMOS circuits have been

demonstrated by several recent works, and are easily extendable to other

applications.

References

1. A.-J. Annema, B. Nauta, R. V. Langevelde and H. Tuinhout, “Analog Circuits in Ultra-

Deep-Submicron CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 40, pp. 132–143, Jan.,2005.


“A 40nm CMOS Highly Linear 0.4-to-6GHz Receiver Resilient to 0dBm Out-of-Band

Blockers,” ISSCC Dig. Tech. Papers, pp. 62–63, Feb. 2011.3. STMicroelectronics technology profile in Circuits Multi-Projet (R) [Online]: http://cmp.imag.

fr/products/ic/

4. P.-I. Mak, S.-P. U and R. P. Martins, “Transceiver Architecture Selection – Review, State-

of-the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, Issue 2, pp. 6–25,Jun. 2007.

5. B. Serneels and M. Steyaert, Design of High voltage xDSL Line Drivers in Standard CMOS,Springer, 2008.

References 33



6. M. Zargari, L. Nathawad, H. Samavati, et al., “A Dual-Band CMOS MIMO Radio SoC for

IEEE 802.11n Wireless LAN,” IEEE J. Solid-State Circuits (JSSC), vol. 43, pp. 2882–2895,Dec., 2008.

7. R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and

A. A. Abidi, “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,”

IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2860–2876, Dec. 2006.8. C. Andrews, A. Molnar, “A Passive-Mixer-First Receiver with Baseband-Controlled RF

Impedance Matching, <6dB NF, and > 27dBm Wideband IIP3,” ISSCC Dig. Tech. Papers,pp. 46–47, Feb. 2010.

9. H. Moon, S. Lee, S-C. Heo, H. Yu, J. Yu, J-S. Chang, S-I. Choi, B-H. Park, “A 23mW Fully

Integrated GPS Receiver with Robust Interferer Rejection in 65nm CMOS,” ISSCC Dig. Tech.Papers, pp. 68–69, Feb. 2010.

10. L. Miao, P.-I. Mak, Z. Yan and R. P. Martins, “A High-Voltage-Enabled Recycling Folded

Cascode OpAmp for Nanoscale CMOS Technologies,” IEEE International Symposium onCircuits and Systems (ISCAS), pp. 33–36, May 2011.

11. R. S. Assaad, J. S. Martinez, “The Recycling Folded Cascode: A General Enhancement of the

Folded Cascode Amplifier,” IEEE J. Solid-State Circuits, vol. 44, no. 9, Sep. 2009.12. K. Ishida, A. Tamtrakarn and T. Sakurai, “An Outside-Rail Opamp Design Targeting for

Future Scaled Transistors,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.73–76,Nov. 2005.

13. B. Serneels, M. Steyaert and W. Dehaene, “A 237 mW aDSL2+ CO Line Driver in a Standard

1.2V 130nm CMOS Technology,” ISSCC Dig. Tech. Papers, pp. 524–525, Feb. 2007.14. S.-M. Yoo. J.S. Walling, E. C. Woo and D.J. Allstot, “A Switched-Capacitor Power Amplifier

for EER/Polar Transmitters,” ISSCC Dig. Tech. Papers, pp.428–430, Feb. 2011.15. H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. A. El-Tanani and K. Soumyanath, “A Flip-

Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN

Application,” IEEE J. Solid-State Circuits (JSSC), vol. 46, no. 7, pp. 1596–1605, Jul. 2011.


Chapter 3

A Full-Band Mobile-TV LNA

with Mixed-Voltage ESD Protection

in 90-nm CMOS

3.1 Introduction

This chapter presents a number of circuit techniques enforced in the design of an

electrostatic discharge (ESD)-protected ultra-wideband (UWB) low-noise amplifier

(LNA) for mobile-TV applications. Unlike the design of narrowband LNAs, con-

current reception over a wide range of spectrum necessitates the LNA to feature

high linearity, preventing desensitization by the high-power blockers. This require-

ment, in conjunction with the obvious design goals of ESD protected input, low

noise figure (NF), low power, impedance match and high gain, constitute hard

tradeoffs to obtain a sensible balance and good compromise among all. The

proposed LNA is to cover the full band of mobile-TV services from 170 to

1,700 MHz such that only one LNA is necessary to support multiple standards.

It features a PMOS-based open-source input structure to optimize the I/O swings

under a mixed-voltage ESD protection while offering an inductorless broadband

input impedance match. The amplification core exploiting double current reuse andsingle-stage thermal-noise cancellation enhances the gain and noise performances

with high power efficiency. Optimized in a 90-nm 1.2/2.5-V CMOS process with

practical issues taken into account, the LNA using a constant-gm bias circuit

achieves competitive and robust performances over process, voltage and tempera-

ture (PVT) variation. The simulated voltage gain is 20.6 dB, noise figure is

2.4–2.7 dB and IIP3 is +10.8 dBm. The power consumption is 9.6 mW at 1.2 V.

│S11│ < –10 dB is achieved up to 1.9 GHz without needing any external resonant

network. Human Body Model ESD zapping tests of �4 kV at the input pins cause

no failure of any device.



35

3.2 Circuit Description

3.2.1 Full-Band Mobile-TV Tuner Architecture

Figure 3.1 shows the block diagram of the full-band mobile-TV tuner where the

proposed LNA is inserted. The architecture is based on a direct-conversion receiver

that is differential to avoid common-mode pickups and even-order distortion [1]. As

addressed in many existing TV tuners (e.g., [2–5]), the baluns required for

generating the differential inputs in this frequency range are bulky in size, and

should be placed off chip. Wideband baluns having a center-tapped secondary can

be employed. The typical insertion losses of a 4.5–2,000-MHz 1:1 SMD balun are

0.32 and 2 dB in 4.5–1,000 MHz and 1–2 GHz, respectively [6].

Wideband reception suffers from the problem of harmonic mixings, i.e., in-band

blockers located at the harmonics of the local oscillator will become the co-channel

interferers. A 60-dB harmonic rejection ratio is expected. To achieve this, separated

RF filters in conjunction with a polyphase I/Q-mixer scheme are employed to doubly

reject the harmonic-mixing products. The polyphase I/Q-mixer scheme includes

three transconductance amplifiers having a gain ratio of 1:√2:1 to drive the passive

current-mode mixers [7]. A voltage-to-voltage LNA is therefore chosen to drive

those transconductance amplifiers that feature purely capacitive input impedance.

3.2.2 PMOS-Based Open-Source Input Structureand Mixed-Voltage ESD Protection

Figure 3.2 depicts the schematic of the proposed LNA. In order to save voltage

headroom and reduce the number of active devices, the cascode structure was not

applied. The main consequence of not using a cascode structure is a limited

470-860MHz

174-245MHz

1450-1700MHz

Balun

Iout+

Iout -

1

-45°

0°

45°

To Q-channel

LNA

This Work

1

Switches

Polyphase I/Q-Mixer SchemeOff-Chip

√2

Fig. 3.1 Full band mobile-TV tuner using a single wideband balun and LNA

36 3 A Full-Band Mobile-TV LNA with Mixed-Voltage ESD Protection. . .

reverse isolation. The results, however, show that with proper sizing the reverse

isolation is acceptable in the targeted frequency range. No matching network is

required as the source node of a nanoscale transistor offers a simple broadband

input impedance match.

The 1:1 balun equally splits the RF signal Vrf toM1 andM2 with opposite phases,

where reverse-biased P+-diffusion diode DP, and N+-diffusion diode DN, are

adopted for pin-to-rail ESD clamp. ESD-protection rail-clamp circuits incorporated

with DP and DN offer low-ohmic discharge paths among the I/O supply voltage –

VDD,I/O, the core supply voltage – VDD, and the common ground – GND. The aim of

choosing a PMOS-based input structure instead of NMOS is illustrated by

VDD

VDD,I/O

1:1Balun

Vrf

IbiasIbias

ESDProtectionRail-Clamp

Circuit

GND

On-Chip

Off-Chip

Package

RS

DP

DN

C2

C4

C1

C3

R1 R2

R5 R6

M1 M2

M3

R3M4

R4

Vout−Vout+

Vb1 Vb1

Vb2Vb2

0.5:

1

0.5:

1

Fig. 3.2 Schematic of the proposed LNA

3.2 Circuit Description 37

comparing the different bias conditions of the LNA and its pin-to-rail ESD clamp,

as follows:

In case NMOS is selected as the input device together with an input common-

mode voltage VCM,IN set to 0.6 V (Fig. 3.3a), the input swing is optimum as it is

midway the rail-clamp supply that is the VDD. Regrettably, VCM,IN ¼ 0.6 V will

offset the output common-mode level by the same amount, resulting in a limited

output swing. Though VCM,IN ¼ 0 V can resolve such an output swing limitation

(Fig. 3.3b), DN at such a VCM,IN is at a higher risk of forward bias, unavoidably

sacrificing part of the input swing.

Conventionally, the above tradeoff cannot be resolved by using PMOS

devices as shown in Fig. 3.4a. In this work, we propose to use VDD,I/O as the driving

voltage for the pin-to-rail ESD clamp. VDD,I/O is commonly available in modern

dual-oxide CMOS processes necessary for input–output (I/O) interfaces. Given that

VDD,I/O ¼ 2.5 V in the employed technology, the I/O swings can be concurrently

maximized, as shown in Fig. 3.4b. Besides that, considering the ESD robustness,

VCM,IN ¼ VDD balances the discharge capability of � zapping events.

The improvement of the proposed input structure in the employed 90-nm CMOS

technology is illustrated by plotting the diode-clamp I/O transfer curves and their

1.2 V

1.2 V

0.6 V+Vsat,n

Load

1.2 V

1.2 V

VCM,IN = 0VVCM,IN = 0.6 V

VinVin

DN

DP

DN

DP Vsat,n

VoutVout

Load

a b

Fig. 3.3 Diode clamps with a NMOS-input structure: (a) VCM,IN ¼ 0.6 V and (b) VCM,IN ¼ 0 V

1.2 V

Load

2.5 V (I/O Supply)

1.2 V- Vsat,p

0.6 V- Vsat,p

Load

VCM,IN = 1.2 VVCM,IN = 0.6 V

Vin

Vout

DN

DP

Vin

Vout

DN

DP

a b

Fig. 3.4 Diode clamps with a PMOS-input structure: (a) VCM,IN ¼ 0.6 V and (b) VCM,IN ¼ 1.2 V

but the clamping voltage is the VDD,I/O ¼ 2.5 V


first derivatives at typical and extreme temperatures (Fig. 3.5). With VCM,IN ¼ VDD

¼ 1.2 V, the linear input [vsig(t)], even at the highest temperature, has a swing of

roughly 3 Vpp in the PMOS case, while it is just roughly 0.8 Vpp in NMOS case with

VCM,IN ¼ GND (0 V).

3.2.3 Double Current Reuse for gm-Enhancement

Current reuse is power-efficient in gain enhancement. In this work, current is

doubly reused to boost the transconductance (gm). A simplified small-signal half-

circuit equivalent of Fig. 3.2 is shown in Fig. 3.6. Firstly, M1 gate-source terminals

are coupled with a gain of �1 (i.e., capacitive cross-coupling [8]) such that the

transconductance of M1, gm1, is enhanced to g0m1 as given by,

g 0m1 ¼ ð1þ AxÞgm1; (3.1)

where Ax stands for the voltage transfer of the highpass network: C3 and R1. The

capacitance division between M10s CGS and C3 gives Ax < 1.

The capacitive cross-coupling reuse in the NMOS device, M3, to further

enhances the overall transconductance Gm as given by,

Gm ¼ g 0m1 þ Aygm3; (3.2)

-2

-1

0

1

2

3

4

-2 -1 0 1 2 3 4 5Input Voltage, Vin (V)

Out

put V

olta

ge, V

out (

V)

1st derivativeof I/O curves

I/O curves

125°C

−55°C27°C

2.5 V

Vin = 0 V + Vsig

Vin = 1.2 V + Vsig

DN

DP

Vin Vout

VCM,IN = 1.2 V

VCM,IN = 0 V

Fig. 3.5 Diode-clamp I/O transfer curves and their first derivatives at different temperatures,

showing the linear input swing versus the selected VCM,IN


where Ay is the voltage transfer of the highpass network:C1 and R3. R5 is a grounded

resistor. R5 and COUT in parallel with the output resistance of M3 (i.e., ro3), andthe resistance looking into the drain node of M1 [i.e., Rout,M1 ¼ ro1 + RS +

gm1ro1(Ax + 1)RS,] will lead to the total output impedance ZOUT,

ZOUT ¼ R5== ro1 þ RS þ gm1ro1ðAx þ 1ÞRS½ �==ro3== 1

joCOUT

: (3.3)

Grounded R5 implemented with a high-resistive polysilicon is to linearize ZOUTand optimize the output common-mode voltage. Since nanoscale transistors suffer

from strong channel-length modulation, the conventional 1/gm approximation of the

LNA’s source-node input impedance leads to poor matching between the calculated

and simulated results. An accurate expression of the resistive input impedance RIN

has to take into account all finite output impedances, i.e., ro1 of M1 and ro3 of M3,

yielding,

RIN ¼R5==ro3==

1joCOUT

þ ro1

1þ g 0m1ro1

: (3.4)

-1

-1

1:1Balun

Vrf

RS

0.5:

1

0.5:

1

RIN

ZIN

ZOUT

COUT

CIN

Ay

Ax

Vout+

VDD

R1Vb1

C3

C1

R3Vb2

M3 R5

M1

Fig. 3.6 Single-ended

small-signal equivalent

circuit of the proposed LNA


RIN in parallel with the input parasitic capacitance CIN leads to the input

impedance ZIN of the LNA given by,

ZIN ¼ RIN==1

joCIN

: (3.5)

After all, the differential voltage gain of the LNA, Av,diff, can be obtained as,

Av;diff ¼ Voutþ � Vout�Vrf

¼ 2ZINRS þ 2ZIN

GmZOUT: (3.6)

3.2.4 Single-Stage Thermal-Noise Cancellation

Noise-cancelling LNAs using a cascading configuration have been reported, e.g.,

[9, 10]. However, additional amplification stages lead to higher NF and poor

linearity. In this work, thermal-noise cancellation can be achieved in a single

stage by taking advantages from the bi-directional coupling behavior of the

balun, and the structure of the LNA after double-current reuse. Re-examining

Fig. 3.2 we can observe that the thermal noise of M1 (which can be modeled as a

noise current source connecting its drain and source) is partly injected to Vout+, and

partly negatively couples to the source of M2 through the balun, and to the gate of

M2 (M4) through the cross-coupling network R2-C4 (R4-C2). An identical noise

coupling operation occurs around M2. Differentially, certain noise transfer paths

will be out phased from the others, yielding a way to cancel out the noise ofM1 with

virtually no cost. Based on RIN (but not ZIN to simplify the noise analysis), it can be

shown that the noise factor F of the LNA is given by,

F ¼ 1þRSRIN

RS þ 2RINGm � 1

� �2gm1

g1a1

þ gm3g3a3

þ 1

R5

2RIN

RS þ 2RIN

� �24RIN

RS þ 2RIN

� �2Gm

2 RS

2;

(3.7)

where a1(a3) and g1(g3) are the process- and bias-dependent parameters ofM1 (M3),

respectively. Principally, the noise generated by M1 (M2) can be minimized by

designing,

RSRIN

RS þ 2RINGm ¼ RSRIN

RS þ 2RINg 0m1 þ Aygm3

� � ! 1: (3.8)

Regrettably, since (3.6) and (3.7) are inter-dependent by most parameters, there

is no straight way to minimize the overall system NF (NF ¼ 10·log F) since Av,diff

also affects the input- referred noise contribution of the succeeding circuits.


In order to co-optimize the key performance metrics, a constraint-based

semi-computed design flow is applied. Given a power budget of 10 mW and a

�3-dB output bandwidth of >1.7 GHz when driving a 0.3-pF load (the input

capacitance of the polyphase I/Q-mixer scheme), the size of M1 and R5 are picked

to fulfill the required RIN, which must be close to RS/2 for an acceptable S11(<�10 dB). R5 is relatively low (250 O) to desensitize ro3 in Eq. 3.5 such that,

without affecting the input match, tuning the size ofM3 can trade the Av,diff, NF and

linearity. Simulation results are plotted in Fig. 3.7a and b, where the size multiplier

(N) of M3 is swept from 1 to 9. Selecting N ¼ 5 yields the highest input-referred

third-order intercept point (IIP3) since the third-order derivative of the DC charac-

teristic is close to zero at this N. The corresponding Av,diff is over 20 dB and NF is

2.5 dB. The �3-dB output bandwidth (1.84 GHz), │S11│ (�16.3 dB) and power

budget (9.6 mW) are satisfied.

-25

-20

-15

-10

-5

0

5

10

15

20

25

1 3 5 7 92

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

Av,diff

Av,

diff

(dB

)

Performance @ 1GHz

NF

(dB

)

NF

|S11|

|S11

| (dB

)

-17

-16.9

-16.8

-16.7

-16.6

-16.5

-16.4

-16.3

-16.2

-16.1

-16

1 3 5 7 97

7.4

7.8

8.2

8.6

9

9.4

9.8

10.2

10.6

11

IIP3

Power

N, size mutiplier of M3 (M4)

N, size mutiplier of M3 (M4)

Size of M3 (M4) = 10µm/0.16µm x N

Size of M3 (M4) = 10µm/0.16µm x N

Performance @ 1GHz

IIP3

(dB

m)

2

1.96

1.92

1.88

1.84

1.80

1.76

1.72

1.68

1.64

1.6O

utpu

t -3d

B B

andw

idth

(G

Hz)

Output -3dBBandwidth

8

8.5

9

9.5

10

10.5

11

11.5

12

Pow

er (

mW

)

a

b

Fig. 3.7 Size of M3(M4) versus RF performances: (a) │S11│, Av,diff and NF. (b) power consump-

tion, IIP3 and output �3-dB bandwidth


3.3 Key Practical Design Issues

3.3.1 Package Effect on Input Impedance Match

Taking into account the package effect (Fig. 3.8), the single-ended (left-half) input

impedance Z’IN of the LNA is given by,

Z 0IN ¼ 1

joCOC

== joLBW þ RBW þ RIN==1

joCIN

� �� : (3.9)

where COC denotes the parasitic capacitance of the lead-frame and soldering pad on

the testing board. LBW and RBW stand for the inductance and resistance of the

bondwire, respectively. CIN is the total input capacitance resulting fromM1, DN and

DP, the parasitic capacitance of C1 and C3, and the bondpad (CPAD).

Similar to the analysis addressed in [11], targeting an in-band │S11│ < �10 dB

requires an input reflection coefficient magnitude │GIN│ to satisfy,

GINj j ¼ Z 0IN � RS=2

Z 0IN þ RS=2

�� 0:32: (3.10)

With RS ¼ 50 O and a balun ratio of 1:1, RIN ¼ 25 O achieves a superior │S11│.However, the matched bandwidth is insufficient since CIN will lower ZIN when

frequency is increasing. Thus, as shown in Fig. 3.8 as well, the optimal RIN that can

result in a broaden bandwidth should be a higher value in practice. Here, with a

-35

-30

-25

-20

-15

-10

-5

0

0.1 101Frequency (GHz)

Equivalent Circuit

Vrf/2

RS/2 RBW

COC

COC = 2.7 pF

CIN = 2 pF

LBW

Z’IN

CINRINRIN = 25 Ω

RBW = 1 ΩLBW = 3 nH

RIN = 30 Ω

RIN = 35 Ω

RIN = 40 Ω

ZN

|S11

| (dB

)

Fig. 3.8 Input matching design including package effects

3.3 Key Practical Design Issues 43

value of RIN between 35 and 40 O it will lead to an adequate │S11│ over the desiredbandwidth, avoiding any external resonant network.

Since the exact value of LBW is uncertain in practice, the pickedRINmust guarantee

a │S11│ < �10 dB over an acceptable range of inductance variation [12]. As shown in

Fig. 3.9, the tolerable LBW variation range is from 1.5 to 3.5 nH for RIN ¼ 40 O.

3.3.2 Self-Startup Constant-gm Bias Circuit

To tackle the PVT variation, a self-startup constant-gm bias circuit is adopted. As

depicted in Fig. 3.10, an off-chip resistor RREF serves as the reference, such that gm,Mb2 can be fixed to the inverse of RREF by equalizing the dc bias current ofMb1 and

Mb2 (they exhibit a ratio of 4:1 and are both long-channel devices) [13]. The

generated Vb1 is the bias voltage of the LNA’s M1 and M2. RREF is scaled up by

10� to reduce the power consumption. Thus, the size ratio of Mb2 to M1 is set to

1:10 for a correct transconductance ratio.

The self-bias structure requires a start-up circuit. Diode-connected Mb7

guarantees that the bias circuit can be started up at power-on by satisfying,

VT;Mb5 þ VT;Mb3 þ VT;Mb7 þ jVT;Mb2j<VDD; (3.11)

and shut down afterwards by satisfying,

VGS;Mb5 þ VGS;Mb3 þ VT;Mb7 þ jVGS;Mb2j>VDD; (3.12)

where VT is the threshold voltage of the transistor.

-35

-30

-25

-20

-15

-10

-5

0

0.1 1 10Frequency (GHz)

1.5nH

2nH

2.5nH

3nH

3.5nH

In-band

|S11

| (dB

)

Fig. 3.9 Input matching versus the inductance (LBW) variation of the bondwire


3.3.3 Power-Up/Down Control with Reliability Concern

Nanoscale circuits for mobile TV require particular attention of reliability in power-

down condition since DVB-H uses time-slicing operation. In the employed 90-nm

CMOS process, the proposed LNA operating at 1.2 V is free from hot carrier

injection (HCI), time-dependent dielectric breakdown (TDDB) and absolute maxi-

mum rating (AMR). The primary concern is the negative bias temperature instabil-

ity (NBTI) of all PMOS devices. To prevent large VGS or VGD in power-down mode,

Mb1 and Mb2 in the self-startup constant-gm bias circuit (Fig. 3.10) are pulled up to

VDD. In this way, the NBTI stress is transferred to the pull-up switches, Mpu1 and

Mpu2, which show no impact to the LNA in active mode. This technique simulta-

neously pulls up Vb1 to VDD, guaranteeing M1 and M2 of the LNA are also shut

down in the same manner.

3.3.4 Mixed-Voltage ESD Protection Scheme

Protecting the nanoscale thin-oxide devices from ESD events requires well-

designed discharge paths to the supply rails. Figure 3.11 shows the designed

mixed-voltage ESD clamps. Power clamps based on P+/N-well diode chains

efficiently realize a sufficient high trigger voltage that is greater than the supply,

such that the leakage current and the chance of accidental latching due to normal

supply fluctuation are minimized. For instance, with a silicon diode threshold

Mb1

Vb1

VDD

Mb4

Mb2

Mb3

Mb7

Mb6Mb5

Mpu1 Mpu2

RREF(off-chip)

IbIb

4 : 1

Start Up PowerUp/Down

gm,Mb2 =1/RREF

Fig. 3.10 Self-startup constant-gm bias circuit (with power up/down control)

3.3 Key Practical Design Issues 45

voltage of ~0.65 V, the VDD,I/O-GND power clamp needs five diodes in series,

whereas for VDD-GND only three are necessary. The selected number of diodes in

the VDD,I/O-VDD power clamp have had the precaution of different supply start-up

sequences. For instance, VDD,I/O may start before VDD. The proposed scheme is

optimized to avoid the happening of any forward-bias current in all supply start-up

sequences.

The dimension of DP (DN) is 1 mm/50 mm � 10. Since the technology

determines that the parasitic capacitances resulting from DP and DN per unit area

are CDP ¼ 0.9 fF/mm2 and CDN ¼ 0.74 fF/mm2, respectively, the imposed total

parasitic capacitance at the input is ~870 fF, which occupies 44% of the total CIN

budget. The rest of the CIN budget can be reserved for the CPAD (~300 fF), the input

parasitic capacitance of M1 and the parasitic capacitances of C2, C4 and C5, which

are all metal-over-metal (MoM) capacitors.

3.4 Simulation Results, Discussions and Benchmarks

The LNA has been extensively characterized in a CadenceTM environment with

SPECTRE as the simulator. The devices dimensions are listed in Table 3.1. The

package effects and parasitic capacitances at the input and output nodes have been

modeled in all simulations. An extra load capacitor of 0.3 pF is added to account for

the input capacitance of the succeeding polyphase I/Q-mixer scheme. The ESD

robustness of the RF-input pins to rail is tested using the Human Body Model

(HBM) reference circuit [14]. A�HBM voltage pulse is applied to the LNA’s input

GND

I/P

VDD,I/O-GNDPower Clamp

VDD,I/O-VDDPower Clamp

VDD,I/O-GNDPower Clamp

LNA

+ zaps

− zaps

N+ diff. in P-wellDiode

P+ diff. in N-wellDiode

CDNxArea

CDPxArea

VDD,I/O (2.5 V) VDD (1.2 V)

VDC=1.2 V

DP

DN

Fig. 3.11 Mixed-voltage ESD-protection scheme


to induce a large +/– zapping discharge current that has a rising/falling time

of ~8 ns. Verified in all combinations, the LNA can withstand minimally �4 kV

of ESD zapping without causing internal or protection devices failure. This result

fulfills the standard of “safe level” (i.e., �4 kV) in the chip-level ESD

specifications.

It would be interesting to compare the effectiveness of the double-current reuse

technique to the simple capacitive cross-coupling. As shown in Fig. 3.12, with M3

serving as an amplification device, there are roughly 1-dB or 3-dB improvements in

terms of NF or Av,diff, respectively.

Multi-band reception of mobile-TV standards does not pose rigid group-delay

variation specification as the BW usage of each standard is relatively small when

comparing it with that of the LNA. The simulated inband gain delay is 233 � 21 ps.

The in-band linearity is verified by two-tone tests as shown in Fig. 3.13. Due to the

cascode-free structure of the LNA and optimal gate-source voltage biasing, high IIP3

of +10.8 dBm and �1-dB input-referred compression point (ICP) of �7.6 dBm are

Table 3.1 Devices dimensions

Device Size Device Size

M1, M2 (10 mm/0.08 mm) � 10 RREF 400 OM3, M4 (10 mm/0.08 mm) � 5 Mb1 (10 mm/0.08 mm) � 4

R1–R4 1 mm � 40 mm ¼ 40 kO Mb2 (10 mm/0.08 mm) � 1

C1–C4 1 mm � 40 mm ¼ 2.7 pF Mb3–Mb7 (1 mm/0.32 mm) � 8

R5, R6 10 mm � 3 mm ¼ 250 O DP, DN (1 mm/50 mm) � 10

-50

-40

-30

-20

-10

0

10

20

30

0

5

10

15

20

25

30

35

40Av,diff

0.01 0.1 1 10

Frequency (GHz)

NF

M3 as a current source

M3 as an amplifier

Av,

diff

and

|S11

| (dB

)

NF

(dB

)

|S11|

Fig. 3.12 RF performance comparison: M3 used as a current source (i.e., only capacitive cross-

coupling of M1) or M3 used as an amplifier (double-current reuse)

3.4 Simulation Results, Discussions and Benchmarks 47

concurrently achieved. Other IIP3’s among the desired signal band varies between

+10.5 and +13.7 dBm. Out-of-band two-tone test at 2.0 and 2.1 GHz is also conducted

(not shown), obtaining an out-of-band IIP3 of +9.9 dBm and a �1-dB ICP of

�3.5 dBm. Both are superior linearity performance metrics in this 1.2-V 9.6-mW

LNA design. The power-down leakage is 47 mW.

The effects of differential imbalance to the performances of the LNA are

simulated. Ten percent size mismatch between M1 and M2 still maintain the

in-band common-mode and supply rejection ratios >50 dB. Since the LNA is

intended to drive an integrated mixer, testing the reverse isolation S12, which

needs a 50-O test buffer, will not allow the determination of the stability infor-

mation of the LNA in its true operating condition. Thus, only the reverse voltage

gain (i.e., the differential outputs coupled back to the input node) and transient

simulation results can help to estimate the stability of the LNA. The simulated in-

band reverse voltage gain is < �28 dB. The tolerable CL is up to 1 pF without

affecting the targeted │S11│ of �10 dB. These tests inspire confidence about the

stability of the LNA while in practice.

As the impact of transistor variability in a nanoscale process is continuously

increasing, process corner and Monte-Carlo (MC) simulations are essential to

investigate the robustness of the RF performances over PVT. A set of simulations

counting the process (Fig. 3.14) supply voltage (Fig. 3.15) and temperature

(Fig. 3.16) variations have been conducted. In addition, a set of 100-time MC

simulation of the RF performances was also performed (Fig. 3.17).

-80

-60

-40

-20

0

-20 -10 0 10 20

Out

put S

igna

l Pow

er (

dBm

)

Input Signal Power (dBm)

20

40

60

IIP3 = +10.8 dBm

9

10

11

12

13

14

0.2 0.7 1.2 1.7Frequency (GHz)

IIIP

3(dB

m)

15

ICP = -7.6 dBm

Fig. 3.13 Two-tone tests at 695 and 700 MHz


16

16.5

17

17.5

18

18.5

19

19.5

20

20.5

21

0.1 0.5 0.9 1.3 1.7 2.1

Frequency (GHz)

SS

FFSNFP

FNSP

-40

-35

-30

-25

-20

-15

-10

-5

0

0.1 0.5 0.9 1.3 1.7 2.1

Frequency (GHz)

SS

FF

SNFP

FNSP

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

0.1 0.5 0.9 1.3 1.7 2.1

SS FFSNFPFNSP

Frequency (GHz)

|S11

| (dB

)N

F (

dB)

Av,

diff

(dB

)

a

b

c

Fig. 3.14 RF performance in process corners: FAST-FAST (FF), SLOW-SLOW (SS), FAST-

NMOS-SLOW-PMOS (FNSP) and SLOW-NMOS-FAST-PMOS (SNFP). (a) Av,diff (b) |S11|

and (c) NF

3.4 Simulation Results, Discussions and Benchmarks 49

These pre-silicon results rigidly verify the effectiveness of the proposed circuit

techniques and the completeness of the design consideration. The LNA will be

experimentally verified with the entire TV tuner.

Table 3.2 gives a comparison of the proposed LNA with respect to the recently

published wideband CMOS LNAs [15–32] (design with both simulation and

0

5

10

15

20

25

0.01 0.1 1 100

2

4

6

8

10

-40

-32

-24

-16

-8

0 1.4V1.2V1.0V

Power Consumption6.3mW @1.0V9.6mW @1.2V

[email protected]

Frequency ( GHz)

NF

1.4V1.2V1.0V

1.4V1.2V1.0V

Av,diff

Av,

diff

(dB

)

|S11|

|S11

| (dB

)

NF

(dB

)

Fig. 3.15 RF performances versus supply voltage variation

NF

Power Consumption8.5mW @-55°C9.6mW @ 27°C

11.5mW @125°C

0

5

10

15

20

25

0.01 0.1 1 100

2

4

6

8

10

-40

-32

-24

-16

-8

0

Frequency ( GHz)

Av,

diff

(dB

)

|S11

| (dB

)

NF

(dB

)

-55°C27°C

125°C

-55°C27°C

125°C

-55°C27°C

125°C

|S11|

Av,diff

Fig. 3.16 RF performances versus temperature variation


measurement results are considered). It can be observed that most performance

metrics of the current design are superior, in particular the voltage gain, power and

linearity, even under high ESD protection.

3.5 Summary

This chapter has described the design of an ESD-protected UWB LNA covering

170–1,700 MHz for full-band mobile TV tuners in a 90-nm CMOS process. �4-kV

ESD robustness at the RF input pins and +10.8-dBm IIP3 have been concurrently

achieved by exploiting a 1.2/2.5-V-mixed ESD protection scheme and a PMOS-based

20.2 20.3 20.4 20.5 20.6

5101520253035

-16.5 -16 -13.5 -120

4

8

12

16

20

2.37 2.38 2.39 2.4 2.41 2.42 2.43 2.44 2.45 2.460

5

10

15

20

25

0

-14.5 -12.5-15.5 -15 -14 -13

20.25 20.35 20.45 20.55

Av,diff @1GHz (dB)

NF @ 1GHz (dB)

Hits

Hits

Hits

Mean = 20.38SD = 0.058

N = 100

Mean = -14.54SD = 0.928

N = 100

Mean = 2.416SD = 0.014

N = 100

|S11| @ 1GHz (dB)

Fig. 3.17 Hundred-time MC simulation results of the RF performances

3.5 Summary 51

Table

3.2

Brief

perform

ance

benchmarkofrecentlypublished

widebandLNAs

Ref

–Year

Technology

Bandwidth

(GHz)

Gain(dB)

NF(dB)

IIP3(dBm)

Supply

(V)

Power

(mW)

No.ofinductors

ESD

protection

[15]TCAS-I’09

S90nm

CMOS

0.1

~1.89

20.6

VG

<2.7

+10.8

@0.7

GHz

1.2

*9.6

0�

4kV

[16]JSSC’08

M65nm

CMOS

0.2

~5.2

13–15.6

VG

<3.5

>0

1.2

21

0No

[17]JSSC’08

M130nm

CMOS

0.8

~2.1

14.5

VG

2.6

+16

1.5

17.4

0No

[18]ASSCC’07

M180nm

CMOS

0.05–0.86

15

VG

2.5

+8.3

1.8

7.2

0No

[19]RFIC’07

m90nm

CMOS

0.4

~1

16

PG

<5.3

�17@

1GHz

1.2

16.8

0No

[20]TCAS-II’07

S130nm

CMOS

0.2

~3.8

11.2

VG

<2.85

�2.7

@3GHz

1.2

1.9

0No

[20]TCAS-II’07

S130nm

CMOS

0.2

~6.2

10.5

VG

<2.85

�2.7

@3GHz

1.2

1.9

2No

[21]TCAS-I’07

M180nm

CMOS

2.8

~7.2

19.1

PG

<3.8

�1@

6GHz

1.8

32

7No

[22]PRIM

E’06

S130nm

CMOS

0.9

~2.5

17

PG

2�5

1.2

15.6

4No

[23]RFIC’05

M130nm

CMOS

0.1

~0.93

13

PG

4�1

0.2

1.2

0.72

0No

[24]CICC’05

M130nm

CMOS

0.1

~6.5

19

PG

<4.2

+1

1.8

11.7

4No

[25]ESSCIRC’05

M130nm

CMOS

3~5

26

VG

4�1

31.5

45

4�

1.5

kV

[26]ISCAS’05

S130nm

CMOS

3~10.7

11

PG

3�8

.21.2

4.8

5No

[27]ASSCC’05

M180nm

CMOS

0.04~0.9

20.3

PG

4�1

0.8

~�1

2.7

1.8

43.2

0No

[28]ISCAS’05

S180nm

CMOS

1.5

~2.6

15.4

PG

0.9

�2.5

1.5

11

4No

[28]ISCAS’05

S180nm

CMOS

3.2

~4.8

17.9

PG

1.6

�4.5

1.5

13.2

4No

[29]JSSC’05

M180nm

CMOS

2~4.6

9.8

PG

<5.2

�71.8

12.6

3No

[30]TCAS-I’05

M250nm

CMOS

3.2

~4.8

7PG

<3.7

4@

4GHz

2.5

20

2No

[31]ISSCC’04

M180nm

CMOS

2.3

~9.2

9.3

PG

5.2

�6.7

1.8

95

No

[31]ISSCC’04

M180nm

CMOS

2.4

~9.5

10.4

PG

5.3

�8.8

1.8

95

No

[32]MWSCAS’03

S180nm

CMOS

3~7

15.3

PG

<1.9

N/A

1.8

15

4No

Ssimulationresults,M

measurementresults*:2.5

VforESDprotectiondiode,PGpower

gain,VGvoltagegain


open-source input structure. Reliability- and PVT-conscious bias techniques lead to

competitive and robust RF performances. The LNA core employed double current-

reuse and single-stage thermal-noise cancellation achieves 20.6-dB voltage gain and

<2.7-dB NF with 9.6-mW power consumption.

References

1. P.-I. Mak, S.-P. U and R. P. Martins, “Transceiver Architecture Selection – Review, State-of-

the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, Vol. 7, Issue 2,

pp. 6–25, June 2007.

2. Vassiliou et al., “A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and

Multimedia Applications,” IEEE J. of Solid- State Circuits, vol. 43, no. 7, pp. 1522–1533,Jul. 2008.

3. P. Antoine, et al., “A Direct-Conversion Receiver for DVB-H,” in IEEE ISSCC, Digest ofTechnical Papers, pp. 426–427, Feb. 2005.

4. D. Saias, et al., “A 0.12mm CMOS DVB-T Tuner,” in IEEE ISSCC, Digest of TechnicalPapers, pp. 430–431, Feb. 2005.

5. I. Vassiliou et al., “A 0.18mm CMOS, Dual-Band, Direct-Conversion DVB-H Receiver,” in

IEEE ISSCC, Digest of Technical Papers, pp. 606–607, Feb. 2006.6. Falco Electronics SMD RF Balun, Available [online]: http://www.falcomex.com/products/3/

04-00.asp

7. I. V R. Bagheri, A. Mirzaei, S. Chehrazi, M. Heidari, M. Lee, M. Mikhemar, W. Tang and A.

Abidi, “An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS,” IEEE Int.Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 480–481, Feb. 2006.

8. W. Zhuo, S. Shekhar, S. Embabi, J. Gyvez, D. Allstot and E. Sanchez-Sinencio, “A Capacitor

Cross-Coupled Common-Gate Low-Noise Amplifier,” in IEEE Trans. On CAS-II: ExpressBriefs, vol. 52, no. 12, pp. 875–879, Dec. 2005.

9. C.-F. Liao and S.-I Liu, “A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB

Receivers,” IEEE J. of Solid-State Circuits, vol. 42, no. 2, pp. 329–339, Feb. 2007.10. E. A. Klumperink, F. Bruccoleri, P. Stroet and B. Nauta, “Amplifiers Exploiting Thermal

Noise Canceling: A Review” in Proc. of Gallium Arsenide and other compound semiconductorApplication Symp. (GAAS), pp. 371–374, Oct. 2004.

11. K. Bhatia, S. Hyvonen and E. Rosenbaum, “A Compact, ESD- Protected, SiGe BiCMOS LNA

for Ultra-Wideband Applications,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1121–1130,May 2007.

12. G. Banerjee, K. Soumyanath and D. J. Allstot, “Desensitized CMOS Low-Noise Amplifiers,”

IEEE Trans. On CAS-I: Regular Papers, vol. 55, no. 3, pp. 752–765, Apr. 2008.13. R. Zele and D. Allstot, “Low Power CMOS Continuous-Time Filters,” IEEE J. of Solid-State

Circuits, vol. 31, no. 2, pp. 157–168, Feb. 1996.14. ESD Sensitivity Testing: Human Body Model (HBM) – Component Level, ESD Association

Standards, 1993.


CMOS for Full-Band Mobile TV Tuners,” IEEE Transactions on Circuits and Systems – I:Regular Papers, vol. 56, no. 5, pp. 933–942, May 2009.

16. S. Blaakmeer, E. Klumperink, D. Leenaerts and B. Nauta, “Wideband Balun-LNA With

Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling,” IEEE J. ofSolid-State Circuits, vol. 43, no. 6, pp. 1341–1350, Jun. 2008.

17. W.-H. Chen, G. Liu, B. Zdravko and A. M. Niknejad, “A Highly Linear Broadband CMOS

LNA Employing Noise and Distortion Cancellation,” IEEE J. of Solid-State Circuits, vol. 43,no. 5, pp. 1164–1176, May 2008.

References 53

http://www.falcomex.com/products/3/04-00.asp

http://www.falcomex.com/products/3/04-00.asp

18. Y. Liao, Z. Tang and H. Min, “A CMOS Wide-Band Low-Noise Amplifier with Balun-Based

Noise-Canceling Technique,” in Proc. IEEE A-SSCC, pp. 91–94, Nov. 2007.19. M. Vidojkovic, M. Sanduleanu, J. Tang, P.Baltus and A. Roermund, “A 1.2 V, Inductorless,

Broad-band LNA in 90 nm CMOS LP,” in Proc. IEEE RFIC symp., pp. 53–56, Jun. 2007.20. A. Amer, E. Hegazi and H. Ragai, “A Low-Power Wideband CMOS LNA for WiMax,” IEEE

Trans. On CAS-II: Express Briefs, vol. 54, no. 1, pp. 4–8, Jan. 2007.21. Y.-J. Emery Chen and Y.-I. Huang, “Development of Integrated Broad-Band CMOS

Low-Noise Amplifiers,” IEEE Trans. On CAS-I: Regular Papers, vol. 54, no. 10,

pp. 2120–2127, Oct. 2007.

22. B. Martineau, et al., “A Wideband LNA for Wireless Multi-standard Receiver in 130 nm SOI

Process”, in Proc. IEEE PRIME, pp. 449–452, Jun. 2006.23. S. Wang, A. Niknejad and R. Brodersen, “A Sub-mW 960-MHz Ultra-Wideband CMOS

LNA,” in Proc. IEEE RFIC symp., pp. 35–38, Jun. 2005.24. S. Chehrazi, A. Mirzaei, R. Bagheri, and A. Abidi, “A 6.5 GHz Wideband CMOS Low Noise

Amplifier for Multi-Band Use,” in Proc. IEEE CICC, pp. 801–804, Sept. 2005.25. R. Salerno, M. Tiebout, H. Paule, M. Streibl, C. Sandner and K. Kropf, “ESD-Protected CMOS

3–5GHz Wideband LNA+PGA Design for UWB,” in Proc. ESSCIRC, pp.219–222, Sept.2005.

26. R. Molavi, S. Mirabbasi, and M. Hashemi, “A Wideband CMOS LNA Design Approach,” in

Proc. IEEE ISCAS, pp. 5107–5110, May 2005.

27. D. R. Huang, et al., “A 40–900 MHz Broadband CMOS Differential LNA with Gain-Control

for DTV RF Tuner”, in Proc. IEEE A-SSCC, pp. 465–468, Nov. 2005.28. Y. Wang, J. S. Duster, and K. T. Kornegay, “Design of an Ultra- Wideband Low Noise

Amplifier in 0.13mm CMOS,” in Proc. IEEE ISCAS, pp. 5067–5070, May 2005.

29. C.-W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, and S. G. Lee, “An Ultra-Wideband CMOS

Low Noise Amplifier for 3–5-GHz UWB System,” IEEE J. Solid-State Circuits, vol. 40, no. 2,pp. 544–547, Feb. 2005.

30. J. Lerdworatawee and W. Namgoong, “Wide-Band CMOS Cascode Low-Noise Amplifier

Design Based on Source Degeneration Topology,” IEEE Trans. On CAS-I: Regular Papers,vol. 52, no. 11, pp. 2327–2334, Nov. 2005.

31. A. Bevilacqua and A. Niknejad, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz

Wireless Receivers,” in IEEE ISSCC Digest of Technical Papers, pp. 382–383, Feb. 2004.32. H. Doh, Y. Jeong, S. Jung, and Y. Joo, “Design of CMOS UWB Low Noise Amplifier with

Cascade Feedback,” in Proc. IEEE MWSCAS, pp. II-641–II-644, Jul. 2004.


Chapter 4

A High-Voltage-Enabled Mobile-TV RF

Front-End in 90-nm CMOS

4.1 Introduction

High-voltage (HV)-enabled circuits offer a feasible alternative to cope with the

sub-1 V technologies at low cost. This chapter describes the first 2 � VDD-enabled

mobile-TV RF front-end with TV-GSM interoperability. It is an on/off-chip co-

design employing externally three customized UHF/VHF preselect filters, a RF

switch and a balun. The integrated part includes: (1) a cascode-cascade inverter-

based low-noise amplifier that features a high gain-to-power efficiency; (2) a

linearized C-2C attenuator using reliable-overdriven MOS switches; (3) an

inductive-peaking feedforward path that evens out the passband variation; and (4)

two cascode I/Q mixer drivers capable to drive passive mixers with small gain and

bandwidth reduction. Gate-drain-source engineering and self-biased structures are

the keys enabling performance optimization with low power and no reliability risk.

Fabricated in a 90-nm CMOS process with 1-V thin-oxide devices, the RF front-end

measures 68-dB rejection at GSM-900 uplink, 0.7-dB passband roll-off, 3.9-dB

noise figure and �5.5-dBm IIP3 at a maximum voltage gain of 26.2 dB. The core

occupies 0.28 mm2 and draws 15 mW. The achieved power-performance metrics is

favorably comparable with the prior arts.

4.2 Tuner Architecture for TV-GSM Interoperation

Figure 4.1 shows the proposed 2 � VDD-enabled mobile-TV tuner RF front-end. It

supports VHF-III (170–240 MHz) and UHF (470–860 MHz) bands in typical recep-

tionmode, and narrowerUHF band (470–750MHz) in TV-GSM interoperationmode.

A direct-conversion architecture [1] facilitates the frequency plan and hardware reuse

for multiband multistandard mobile-TV applications [2]. The external passives

include an off-the-shelf balun, an off-the-shelf SP3T RF switch and three customized



55

preselect filters built with surface-mount devices (SMDs). A wideband LNA covering

the VHF-III and UHF bands is employed as it can cover both VHF III to UHF bands

without demanding reconfigurability [3]. The LNA has to exhibit low noise, high gain

and gain control such that the noise contribution of the latter circuitry is minimized.

However, due to the high gain of the LNA, the linearity of the front-end is limited

by the C-2C attenuator and I/Q mixer drivers. Since a 2 � VDD helps improving

linearity with low overhead, techniques for improving the linearity of the C-2Cattenuator and I/Q mixer driver are developed. All circuit blocks are differential

to desensitize them from bondwire variation, while minimizing common-mode

pickups and even-order nonlinearity. An inductive-peaking feedforward path is

added to even out the passband variation. The reason for the LNA to have three

sets of differential outputs will be addressed later. The gain control is implemented

digitally in three steps: (1) the LNA provides a one-step high-/low-gain control,

(2) the C-2C attenuator offers a coarse gain control with a 6-dB step size, and (3)

the I/Q mixer driver renders a fine gain control with a 0.75-dB step size.

The rationale for employing three preselect filters is related with the fact that

in the frequency range of interest the VHF-III band suffers from harmonic mixing

if only one preselect filter is adopted, since the UHF band is located at the

third harmonic of the local oscillator (LO) when downconverting the VHF-III

band by hard-switching mixers. This drawback is overcome by separation of the

Balun

LNA

C-2CAttenuator

I/Q MixerDrivers

I

Q

LOQ

LOI

880-915 MHz

PolyphasePassiveMixers

170-240 MHz

470-860 MHz

470-750 MHz

On-Chip

Preselect Filters

(for TV-GSMinteroperation)

GSM-900Transceiver

HPF:H(f)

900f (MHz)[log]

|H(f)| (dB)

750

Gain Ctrl

~10 dBIsolation

SP3T RFSwitch

Feedforward Gain-Roll-Off compensation

Off-Chip

Fig. 4.1 Proposed on/off-chip co-designed mobile-TV tuner RF front-end supporting VHF III

(170–240 MHz) and UHF (470–860 MHz) bands in typical reception mode, and narrower UHF

(470–750 MHz) band in TV-GSM interoperation mode

56 4 A High-Voltage-Enabled Mobile-TV RF Front-End in 90-nm CMOS

VHF-III and the UHF prefilters with transference of the mixers to a polyphase

harmonic-rejection mixer scheme [4, 5]. The VHF-III prefilter serves to reject the

interferers located at the harmonics of the LO, whereas the mixer scheme

interpolates a pseudo sinewave to suppress the third and fifth harmonics of the LO.

The preselect filter for the narrower-UHFband supports theTV-GSMco-integrated

terminals. The presence of the GSM-900 service poses a strict challenge to the tuner

operating in the UHF band [6]. Figure 4.2 outlines the spectrum of TV-GSM

interoperation, where the upper cutoff frequency is reduced from 860 to 750 MHz,

as allowed by theDVB-H specifications [7]. Since the isolation between the tuner and

GSM transceiver is limited to roughly 10 dB, external filtering is required for

seamless TV-GSM interoperation. For the GSM transceiver, a forefront off-chip

highpass filter (HPF) minimizes its leakage power from increasing the tuner’s input

noise floor. For the tuner, a preselect filter having a notch at 900MHz is required. An

attenuation level of not less than 58 dB is necessary to guarantee theGSM-900 uplink

signal, with a maximum power level of +33 dBm, still aligned with the maximum

input power outlined by theDVB-H standard. Such a rejection requirement cannot be

simply fulfilled by an off-the-shelf TV-tuner filter [8]. Typically, with no intent of

TV-GSM interoperation, only 30-dB attenuation at GSM-900 uplink is provided.

Moreover, due to a limited Q factor, a sloped passband is induced.

Here a customized preselect filter and a feedforward gain roll-off compensation

path are applied concurrently in the TV-GSM interoperation mode to meet the

GSM-rejection profile, while maintaining the flatness of the passband prior to

down-conversion. Likewise, the input-referred noise around the transition fre-

quency will not be pronouncedly degraded.

Other design specifications are concisely summarized here as they have been

extensively reported in the literature [2, 9]. The representative linearity specifica-

tion is given by the L1 pattern test of DVB-H, i.e., the TV tuner has to demodulate a

f (MHz)[log]

Power (dBm)

0

-35

WantedSignal

In-band blocker

≥58dB is required to suppress it as an in-band blocker

GSMSignal

23

-75

Slopedpassband

3rd OrderInter-modulation

distortion

2f1-f2 2f2-f1(900)

f1 f2

Fig. 4.2 170-to-750-MHz preselect filter’s profile for receiving the TV band in the presence of

GSM-900 uplink

4.2 Tuner Architecture for TV-GSM Interoperation 57

16-QAM signal when there are two interferers, one digital (40-dB stronger) and one

analog (45-dB stronger), two and four channels away from the desired, respec-

tively. This test sets the IIP3 to �5 dBm together with a noise figure (NF) of 8 dB.

The sensitivity specification is also given by the DVB-H standard. At the maximum

gain a NF of 5 dB is required. This value includes the insertion loss (IL) of the

external components.

4.3 On/Off-Chip Circuit Design

All the integrated circuits are of differential architecture though several schematics

are shown in their single-ended equivalents for simplicity.

4.3.1 Basic-Cell of the LNA

This sub-section describes the basic cell of the LNA that can be easily upscaled to

2 � VDD operation. As shown in Fig. 4.3, a 1 � VDD inverter-type amplifier with

the NMOS’s source terminal as the input enables a wideband input impedance

match. The capacitive cross-coupling technique [10] reuses the gate-source

transconductance (gm) of both NMOS and PMOS devices, resulting in an improved

gain-to-power efficiency. In this sub-circuit level, the input DC voltage is set at

Vinp

Rfb Rfb

VDD

Vp,bulk

Voutp Voutn

Vinn

RIN,diff

VRF

Vn,bulk Vn,bulk

Vp,bulk

VDD

C1C1

M1

M2M2

M1

(VDC = 0.5xVDD)

(VDC = VSS)Balun

Fig. 4.3 1 � VDD inverter LNA. Input DC level is assumed to be at Vss (0 V)


0 V (VDC ¼ VSS) through the off-chip balun. The gate voltage is self-biased by the

feedback resistor Rfb, resulting in an output DC voltage halfway of the supply (i.e.,

0.5 � VDD) that can maximize the linear output swing. The differential voltage gain

AV,diff is given by,

AV;diff ¼ Voutp � Voutn

Vinp � Vinn

¼ gm1 þ 2gm2 þ 1

ro2� 1

Rfb

� �ro1==ro2==Rfbð Þ: (4.1)

where gm1,2 and ro1,2 are the transconductance and output resistance of M1,2,

respectively. The overall transconductance (Gm) corresponds to the term gm1 +2gm2 + 1/ro2�1/Rfb which can be approximated to gm1 + 2gm2 for sufficiently

large ro2 and Rfb, implying roughly a tripled increment of transconductance when

comparing to that achieved by a single transistor. With VDD ¼ 1 V, proper sizings

lead to │VGS│ ¼ │VGD│ ¼ │VDS│ ¼ 0.5 V for bothM1 andM2. Given that |VT| of the

thin-oxide NMOS and PMOS transistors is roughly 0.3 V, each transistor is biased in

strong inversion with │VGS�VT│ ¼ 0.2 V. The Gm-to-Ib ratio is ~30 V�1 and the

output dynamic range is 0.6 Vpp.

The use of M2’s source node as the input terminal realizes a wideband input

impedance match. It can be shown that the differential input resistance (RIN,diff) of

the LNA is given by,

RIN;diff ¼ 2

2gm2 þ 1Rfb

þ 1Rfb

� 1ro2

� �AV; diff

: (4.2)

which can be simplified to a handy and observable form,

R0IN;diff �

2

gm1 þ 4gm2; (4.3)

when ro1 and ro2 are assumed to be infinite. However, in nanoscale technologies

Eq. 4.2 is essential for an accurate calculation of RIN,diff. RIN,diff and the total input

parasitic capacitance CIN determine the value and BW of the input reflection

coefficient magnitude │GIN│, as given by,

GINj j ¼1

joCIN==RIN;diff � RS

1joCIN

==RIN;diff þ RS

��; (4.4)

where RS denotes the output resistance of the test source. The finite output imped-

ance ofM1 andM2 complicates the optimization between voltage gain, BW and NF

under an impedance-match condition. For the sizing of each component, a

constraint-based semi-computed design flow [11] is applied to optimize those

parameters concurrently. It is noteworthy that the capacitive cross-coupling

4.3 On/Off-Chip Circuit Design 59

technique and the use of an off- chip balun for signal injection allows effective

noise and distortion cancellation of M2.

Self-biased inverter-based circuits are sensitive to process, voltage and temper-

ature (PVT) variation. The back-gate control scheme highlighted in [12] is an

effective solution for this problem. It keeps the supply current constant and reduces

the sensitivity to supply ripple by returning the correcting signals to Vp,bulk and

Vn,bulk. A triple-well process is required to isolate the bulk of NMOS from substrate.

Because this work is the very first proof-of-concept prototype, this back-gate

control scheme has not been embedded.

Since the linearity of the receiver is mainly limited by the I/Q mixer drivers, the

main design consideration of the LNA is to operate it under a 2 � VDD with

guaranteed reliability. The associated biasing is simplified by introducing a VDD

partitioning concept. Based on it, a 2 � VDD cascode-inverter LNA, and a 2 � VDD

cascode-cascade-inverter LNA that befits the proposed RF front-end, are developed.

1. VDD Partitioning Concept: In order to reliably bias the thin-oxide transistors

under an elevated supply, it is convenient to equally divide the supply into four

regions, as shown in Fig. 4.4. From left to right, under a 2 � VDD, a 1 � VDD

inverter-type amplifier (IA1 to IA3) can be connected in three different ways

without affecting the performance and reliability. Such an amplifier is self-

biased by a feedback resistor. It can be observed that the inter-rail voltage levels

(0.5 � VDD, 1 � VDD and 1.5 � VDD) call for additional circuitry for generating

the inter supply rails. This overhead, however, can be avoided by exploiting a

cascode of two identical inverter amplifiers (IA4 and IA5). The intermediate

point is still the RF input node, self-biased to a value close to 1 � VDD because

of voltage division. Due to a matched I/O DC level, the voltage gain can be

enhanced further by cascading the cascoded inverter amplifiers (IA6 to IA9),

without needing any ac-coupling.

2xVDD

1.5xVDD

1xVDD

0.5xVDD

VSS

Single Stage Cascode Cascode-Cascade

IA1

IA2

IA4

IA5 IA7

IA6

IA9

IA8IA3

InverterAmplifier

self-biasedto1xVDD

Fig. 4.4 Three 2 � VDD partitioning schemes for the LNA


2. 2 � VDD Cascode-Inverter LNA: Figure 4.5 describes the transformation of a

1 � VDD inverter LNA into a 2 � VDD cascode-inverter LNA. It is noteworthy

that the main objective is to keep the RF performance, power consumption and

output resistance remain unchanged, but the voltage capability is doubled. The

LNA is structured by, first, splitting the 1 � VDD inverter LNA into two, relying

on the principle of device parallelism. The second is stacking them together. The

reliability of all devices is maintained at static and power-up/down transient as

the dc-levels of all internal nodes follow linearly with the 2 � VDD when it

ramps up (see Fig. 4.5, right). Due to the separation of circuits from 1 to 2, the

output impedance of each output (Vout1 and Vout2) is doubled from its original

1 � VDD design. This issue can be solved by ac-shorting the dual outputs

passively by a capacitor, or actively by another gain stage as shown in

Fig. 4.6. The latter can further boost the RF gain, at the expense of the BW

(since Vout is of even higher output impedance). The reliability is guaranteed

simply by adding two cascode devicesMcp andMcn with resistor Rb for the drain-

gate bias.

Here the passive combination has been selected for its excellent linearity, and

also the fact that the required summing capacitor can be merged into the

subsequent programmable C-2C attenuator, and the gain of the supply and

Ib x 0.5

Ib x 0.5

Rfb

Rfbx 2

Rfbx 2

Rfbx 2

VDD

VSS

VSS

2xVDD

VDD

Vout

M2

M2

M2M1

M1

M1

M4

M3

C1

C1x 0.5

C1 x 0.5

C1 x 0.5

Splitting bases onparallelism of each device

Cascoding (upper)

Cascoding (lower)

1xVDD

1xVDD

1xVDD

Vinn

Vinn Vout

Vout1

Vout2

Vinp

Vinp

Vinn

Vp,bulk

Vn,bulk

Vinn

Vinp

(VDC = Vss) (VDC = 0.5xVDD)

(VDC = 0.5xVDD)

(VDC = 1.5xVDD)

(VDC = 1xVDD)

(VDC = 1xVDD)

(VDC = 1xVDD)

(VDC = Vss)

0

0.5

1

1.5

2

0 0.5 1 1.5 2Supply Voltage (V)

DC

Lev

el (

V)

LNA

2xVDD2xVDD

0

ramp upA

B

C

D

A

B

C

D

W1/L1

W1/L1 x 0.5

W1/L1 x 0.5

W2/L2 x 0.5

W2/L2 x 0.5

W2/L2 x 0.5 x k

W1/L1 x 0.5 x k

W2/L2

Ib

Fig. 4.5 Constant-power constant-performance transformation of a 1 � VDD inverter LNA into a

2 � VDD cascode-inverter LNA (simplified half circuit)


ground noises to the single-ended output can be remarkably reduced. The gain

enhancement is modified as a double capacitive cross-coupling technique. Thus,

the bias point, and the net voltage stressed on each transistor, are unaltered when

compared with a generic 1 � VDD design. This feature contrasts with the

outside-rail HV circuits [13] which operates with large signals, the trajectories

of the device terminal voltages in transients must be controlled to be within the

reliability limits such as HCI, TDDB and punchthrough. The factor k is

introduced as a correction constant since the roles of NMOS and PMOS in the

lower inverter are switched comparing with the upper one. It is possible to

design without k, but it helps to ensure that the upper and lower inverters can

achieve the same RF performances. The bulk of M2 (M3) should be tied to its

source to avoid voltage overdrive between the bulk and source terminals. The

bulks of M1 and M4 can be used to desensitize the circuit from PVT variation as

mentioned before. The DC level of the input node is self-biased to a value close

to 1 � VDD (halfway of the elevated supply).

3. 2 � VDD Cascode-Cascade-Inverter LNA: Its schematic is shown in Fig. 4.7.

Adding one more gain stage boosts gain and permits gain switching without

affecting the input impedance match. The second stage is realized by A3 and A4

that are inverter-like common-source amplifiers offering a simple gain-bypass

mode by using a switch (SW) in parallel with Rfb2. Considering the upper path

involving A1 and A3, the voltage gain AV,A3 of A3 in the high-gain mode can be

expressed by,

AV;A3 ¼ Vout;2nd

Vin;2nd¼ gm5 þ gm6 � 1

Rfb2

1ro5==ro6

þ 1Rfb2

: (4.5)

From

From

(VDC = 1.5xVDD)

(VDC = 1.5xVDD)

(VDC = 0.5xVDD)

(VDC = 0.5xVDD)

(VDC = 1xVDD) (VDC ª 1xVDD)

2xVDD

Mcp

VSS

Mcn

Mn

Mp

Rb

Vout1

Vout,sum

Vout2

Fig. 4.6 A 2 � VDD cascode-inverter LNA with its dual outputs combined actively by a dual-

input cascode amplifier


where gm5,6 and ro5,6 are the transconductance and output resistance of M5,6,

respectively. In the low-gain mode, Rfb2 is reduced (in parallel with the ON-

resistance of the SW). The input resistance of A3 RIN,2nd is given by,

RIN;2nd ¼ Rfb2 þ ro5==ro61þ gm5 þ gm6ð Þ ro5==ro6ð Þ : (4.6)

Since RIN,2nd loads to A1, the gains of A1 and A3 are simultaneously reduced in

the low-gain mode when Rfb2 is decreased, effectively increasing the linearity.

Besides, no reliability issue is induced as the gain control involves no change of

bias point. The consideration applies for the lower path involving A2 and A4. One

particular feature of this LNA is that in addition to the two high-impedance

output terminals (Vout1p and Vout2p), a low-impedance output terminal (Vout3p) is

available, which will be re-used for gain roll-off compensation.

The simulated performances of the standalone LNA are shown in Fig. 4.8. At noload condition the high-gain mode shows 31.4-dB voltage gain, 2.8-dB NF and

S11 < �10-dB BW of 0.1–1.5 GHz. At the low-gain mode, the performances are

21.1-dB voltage gain, 3.6-dB NF and S11 < �10-dB BW of 0.1–1.56 GHz. An

in-band 2-tone test at 400 and 500MHz shows an IIP3 of -3.3/5.4 dBm at high-/low-

gain mode. The LNA draws 9.8 mW at 2 V. It is noteworthy that those performance

metrics exclude the loading effect of the C-2C attenuator and I/Q mixer drivers.

Co-simulations between blocks are necessary to justify the overall RF performances.

Ib1 Ib2

A4

A1

A2

High/LowGain Mode

A3

NX

A3 & A4

SW

ESD Protection

2xVDD

2xVDD 2xVDD

VSS

VSS VSS

C1

C1

Vinp

Vinn(VDC = 1xVDD)

(VDC = 1xVDD)

Vout,2nd

Vout1p

Vout3p

Vout2p

Vin,2nd

RIN,2ndVp,bulk

M5

M6

Rfb2

(VDC = 1.5xVDD)

(VDC = 1xVDD)

(VDC = 0.5xVDD)

Fig. 4.7 A 2 � VDD cascode-cascade-inverter LNA with triple output terminals and high/low-

gain mode (simplified half circuit)


4.3.2 ESD Protection Scheme

Since NX (see Fig. 4.7) is self-biased internally by the LNA at a DC level halfway of

the supply, it is convenient to apply forward-connected diode chains to boost the

ESD protection level. As shown in Fig. 4.9, D3’s and D4’s are three substrate PNP

diodes, which, together with the reverse-biased diodes (D1 and D2) and power

clamp construct the ESD protection scheme. In the ESD-robustness simulation, a

Human Body Model (HBM) voltage pulse is applied to the LNA’s input to induce a

large +/� zapping discharge current that has a rising/falling time of ~8 ns [14]. As

verified in all combinations the RF input pins can withstand minimally �4 kV of

ESD zapping without causing internal or protection devices failure. This result

fulfills the standard of “safe level” in the chip-level ESD specifications. The main

concern is the induced nonlinear parasitic capacitance, which is roughly 0.2 pF in

this design. With a rail-to-rail sinewave applied at the input, the total harmonic

distortion is 0.1%.

4.3.3 Programmable C-2C Attenuator

The linearity of the I/Q mixer driver limits that of the entire TV tuner because of the

voltage gain of the LNA. Instead of utilizing the current-steering gain-control

method [15] that can affect the operating points, a passive C-2C attenuator

(Fig. 4.10) is inserted between the LNA and the I/Q mixer drivers to control

coarsely the dynamicity of the RF signal. Conveniently, the input capacitor can

be divided into two equally-sized capacitors (Cx’s) for passively combining the

LNA’s upper (Vout1p) and lower (Vout2p) outputs. The five-stage attenuator offers an


In-Band

-15-10-505

101520253035

S11

High-Gain ModeLow-Gain Mode

NF

Voltage GainV

olta

ge G

ain,

NF

, S11

(dB

)

no load

Fig. 4.8 Simulated performances of the standalone LNA with no load


attenuation range Av ¼ 0 to �30-dB with a �6-dB step size, i.e., Av ¼ Gn(2)�n for

n ¼ 0, 1, . . ., 5, where Gn ¼ (0, 1) is the gate control logic for switching the

attenuation levels. Sizing Cx has a tradeoff between the accuracy and BW. An

increase of Cx value can desensitize the gain step from parasitic capacitances,

whereas a decrease of Cx value can maximize the BW. Here the optimized Cx is

0.5 pF for the targeted BW. The simulated magnitude response of the C-2Cattenuator is shown in Fig. 4.11. The ON-resistance of the switches and capacitor

size determine the BW of the attenuator, which is well over 1 GHz among all

D1

D2

D3's

D4's

Powerclamp

RF Pin ESDProtection

LNA

(VDC ª 1xVDD)Vinp

2xVDD

VSS

Fig. 4.9 ESD protection scheme of the RF input pin

1.5xVDD

0.5xVDD

ON

OFF

Driving VoltageG0 ... G5

(to NY, biasedat 0.5xVDD)

0 to - 30 dB (-6dB/step)

Vin1 Vout

Vin2

CX

CX

CX = 0.5 pFAll NMOS: (5/0.1) x 4

CX CX 2CX

2CX2CX

VSS

G0

G0

G1 G2 G5

VSS VSS

Fig. 4.10 Programmable C-2C attenuator for coarse-gain control. The input capacitor 2Cx is

divided into 2 Cx’s to interface with the LNA


attenuation levels. The output is not buffered before driving the mixer driver,

inducing 0.1-dB passband gain loss under a 0.1-pF load, which models the input

capacitance of the mixer driver.

An elevated VDD helps minimizing the size and nonlinearity of MOS switches.

In the proposed VDD partitioning scheme there are four gain switching methods

using digital inverters, as shown in Fig. 4.12. NMOS and PMOS switches using

the corresponding inverter ensure VGS ¼ 1 V in ON-state, VGS ¼ 0 V in OFF-

state. The main reliability concern of the C-2C attenuator is the BTI because

all switches conduct no static current, and to overcome it, triple-well NMOS

switches allowing bulk-source connection are employed as they are far less

affected by BTI than the PMOS devices. The associated tradeoff is that NMOS

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0


Mag

nitu

de R

espo

nse

(dB

)

In-Band

-1dB ~ - 31dB

@ 0.1pF load

Fig. 4.11 Simulated magnitude response of the C-2C attenuator

Vo2

Vo3Vo3

Vo1

Vo1

Vo2

Vo2

NMOS

NMOS

PMOS

PMOS

DigitalInverter

VSS

0.5xVDD

1xVDD

1.5xVDD

2xVDD

1(2xVDD)0(1xVDD)

1(1xVDD)0(GND)

1(1.5xVDD)0(0.5xVDD)

Fig. 4.12 Appropriate digital inverters for switches operating at different supply rails. They drive

NMOS and PMOS switches correspondingly, such that VGS of 1 � VDD in ON-state can be

achieved in the four cases shown


requires a deep n-well to permit bulk-source connection, which is a cheap option

widely available in advanced processes. The parasitic capacitances associated

with the deep-n-well diodes have to be accounted to minimize gain-step error.

The terminal voltage NY is purposely set to 0.5 � VDD (0.5 V) to interface with

the I/Q mixer drivers. As such, the gain-control logics [G0 to G8] can be reliably

up-shifted to 1.5 � VDD (1.5 V) in ON-state. Considering AMR and TDDB, the

RF input signals (Vin1 and Vin2) can be as large as 0.4 Vpp. In the linear region, a

0.5-V increment of overdrive (VGS�VT) leads to a better linearity and a smaller

transistor size for a given ON-resistance (RON). The RON of a CMOS transistor

based on a first-order model is given by,

RON ¼ 1

moCoxWL VGS � VTð Þ : (4.7)

The simulated IIP3 of the C-2C attenuator under a 50-Ω source impedance with

1.5 and 1-V gate-control voltages are shown in Fig. 4.13. The former achieves +9.8

to +16.1 dBm IIP3 among an attenuation range of 0 to �30 dB, showing minimally

7.3-dB improvement of IIP3 when comparing it with the latter.

The 0.5 � VDD-up level shifter is shown in Fig. 4.14. It features a simple

structure to realize low-to-high transition from 0/1-V input to 0.5/1.5-V output.

When the input is logic 1 (1 V), Vx level is close to ground, MOS switch Ma is

turned ON (with a resistance much smaller than R1), yielding Vy � 0.5 V [i.e., 2 V ·

(2R1//R1)/(2R1//R1 + 2R1)] and making [G0 to G5] equal to logic 1 (1.5 V). On the

other hand, when the input is logic 0 (0 V), Ma is OFF, yielding Vy � 1.5 V

0

2

4

6

8

10

12

14

16

18

-30 -24 -18 -12 -6 0

Gain (dB)

IIP3(

dBm

)

[G0 to G5]: 1V

[G0 to G5]: 1.5V

VDC=0.5V VDC=0.5V

VDC=0.5V VDC=0.5V

7.3 dB

Fig. 4.13 IIP3’s of the C-2C attenuator with 1-V and 1.5-V gate voltages. The triple-well NMOS

switches are biased at a DC level of 0.5 V


[i.e., (2 V�1 V) · (2R1)/(2R1 + 2R1) + 1 V] and making [G0 to G5] equal to logic

0 (0.5 V). It can be verified that all terminal voltages of MOS devices satisfy the

reliable limits. The required reference voltages are generated by an on-chip high-

ohmic polysilicon resistor ladder.

4.3.4 I/Q Mixer Drivers

The proposed I/Q mixer drivers (Fig. 4.15) are based on a cascode structure with a

resistive load to drive a passive mixer. It benefits the most from an elevated VDD in

terms of linear output swing and reverse isolation. The fine-gain control [G6 to G8]

is set at the AC-switching part ofM3 (i.e.,M03), covering a 0–6-dB gain range with a

0.75-dB step size. The gain-control logics [G6 to G8] are up-boosted to 0.5 � VDD

in OFF-state and 1.5 � VDD in ON-state to improve the linearity, similar to the gain

control in the C-2C attenuator. The entire coarse-fine gain control involves no

change of bias points, ensuring the reliability in all operating modes. M4 and M5

are NMOS transistors with VGS ¼ VDS ¼ 1 � VDD and are of long channel length

(i.e., 1.2 mm) to avoid BTI and punchthrough.

M3 and M03 are linearized and self-biased by R3 at a VGS of 0.5 � VDD. They

deliver the signal current to the two cascode devices M4 and M5 while maintaining

adequate reverse and I/Q isolations of 76.3 and 38.4 dB in simulations, respectively.

The linear output swing is boosted to 0.6 Vpp without jeopardizing the reliability

limits in terms of RF stress [16], which is confirmed by checking the trajectories of

the terminal voltages in power-up/-down transients.

The mixer driver is supposed to deliver high swing output to a resistive load while

ensuring a sufficient voltage gain. When driving a passive mixer realized with

MOSFET, a small device size is preferred as the switching power of the local oscillator

(LO) path can be minimized. The mixer switchMMIX shown in Fig. 4.15 is of PMOS

type to take advantage of the 1.5 � VDD output dc-level, increasing the gate-source

2 V

1 V

2R1

2R1 R1

0 V

1 V

1.5 V

0.5 V

MaVGS, VGD, VDS, ≤ 1v

for all transistors

Gain Ctrl Logic

(1V, 0V)

G0 ...G5(1.5V, 0.5 V)

Vx

Vy

Fig. 4.14 0.5 � VDD-up level shifter


overdrive in ON-state as 1 � VDD. Since the I/Q mixer driver has resistive input

impedance, the loading effect between it and the LNA and C-2C attenuator must

be taken into account to check the overall gain and output BW under different loads.

As shown in Fig. 4.16, with RL1 ¼ 700O the voltage gain can be maintained>20 dB

0 to -30 dB(-6dB/step)

ProgrammableC-2C Attenuator

NZ (VDC ª 0.5xVDD)NY

(VDC ª 0.5xVDD)

ONOFF

GateVoltageG6 ...G8

Feedforward Gain roll-offCompensation Path

C

A A

B B

0 to 6 dB(0.75dB/step)

(VDC ª1.5xVDD) (VDC ª1.5xVDD)RL1

MMIX

loutp Qoutp

MMIX

M5

M3

M3'

R3

M4

LO90LO0

RL1

1.5xVDD1.5xVDD

1.5xVDD

0.5xVDD0.5xVDD

2xVDD 2xVDD

VSS

VSS

G6

G6G6 -G8

Vout1p

Vout2p

Vout3p

Fig. 4.15 The proposed cascode I/Q mixer driver. M3 is partially switchable for fine-step gain

control. The low impedance nodeNz interfaces the feedforward path to compensate the gain roll-off


-20

-10

0

10

20

30

Mag

nitu

de R

espo

nse

(dB

) RL1 = 700Ω

In-Band

MMIX

3.6/0.1 x 4

3.6/0.1 x 33.6/0.1 x 2

3.6/0.1

Fig. 4.16 Magnitude response of the RF front-end at different sizes of the MMIX


with around 1-GHz overall output BW with sizes ofMMIX ranging from 3.6/0.1 � n,where n ¼ 1, 2, 3, 4. With a 50-O RF test source and MMIX sized as 3.6/0.1, the

simulated differential voltage gain of the mixer driver is 5.4 dB and IIP3 is +8.6 dBm.

The I/Q mixer driver is extensively voltage biased to freeze the operating points

necessary for reliable operation. Since the DVB-H employs time-slicing operation [7]

a resistor ladder generating the reference and bias voltages avoids wrong voltage

buildup (remove) sequences in internal nodes during power-up (down) transients.

Figure 4.17 shows the simulated internal node voltages of the I/Q mixer drivers

(markers correspond to Fig. 4.15) when the 2 � VDD ramps up from 0 to 2 V. It can

be observed that the potential differences of all internal nodes are within the reliable

guides of AMR and TDDB.

4.3.5 Customized External Preselect Filters

The schematics, S21 andS11of the three preselect filters optimized for the 170-to-240,

470-to-860, and 470-to-750 MHz bands, are shown in Fig. 4.18a–c, respectively. The

source and input impedances of theRF front-end arematchedwith 75O. TheQ-factorsof surface- mount-device (SMD) inductor and capacitor at 1 GHz are 60 (QL) and 80

(QC), respectively. A 1-pF input parasitic capacitance is assumed to be at the input of

the RF front-end. The in-band │S11│ is less than�10 dB in all cases. The 470-to-750-

MHz preselect filter achieves 60 dB rejection at 900 MHz at the expense of 1.66-dB

passband variation near the cutoff. This effect is addressed by a gain roll-off

0

0.2

0.4

0.6

0.8

1

1.2

0 0.5 1 1.5 2

Supply Voltage (V)

Inte

rnal

nod

e V

DC (

V)

A C

C

B C

I/Q MixerDriver

0

ramp up2xVDD

2xVDD

M4 ,M5: VDS =

VGS =

M3: VGS = VDS =

VSS

Fig. 4.17 Simulated DC-node voltage change of Fig. 4.15 with the 2 � VDD ramps up from 0 to 2 V


-100

-80

-60

-40

-20

0

-35

-30

-25

-20

-15

-10

-5

0

56nH

8pF 17pF

56nH

5pF

S21

(dB

)

S11

(dB

)

0 0.5 1 1.5 2Frequency (GHz)

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

-70

-60

-50

-40

-30

-20

-10

0

0 0.5 1 1.5 2Frequency (GHz)

9nH

0.5pF

-70

-60

-50

-40

-30

-20

-10

0

0 0.5 1 1.5 2-40

-35

-30

-25

-20

-15

-10

-5

0

Frequency (GHz)

1.66 dB Variation3.8nH

8.3pF

18nH

5pF 5pF

3.8nH

8.3pF

18nH

5pF 5pF

3.8nH

8.3pF

S21

(dB

)S

21 (

dB)

S11

(dB

)S

11 (

dB)

a

b

c

Fig. 4.18 Simulated S21 and S11 of the three preselect filters for: (a) 170-to-240-MHz band,

(b) 470-to-860-MHz band and (c) 470-to-750-MHz band


compensation technique to be described next. The 170-to-240-MHzpreselect filter can

achieve more than 30 dB rejection at 510 MHz to prevent the harmonic mixing. In

order to measure the frequency response with minimum IL, the 470-to-860-MHz

preselect filter for typical reception is a simplified LC structure. The selected balun

and RF SP3T switch are wideband components. Up to 1 GHz, the 1:2 balun has a 1.2-

dB IL [17] and the SP3T RF switch has a 0.4-dB IL [18].

4.3.6 Feedforward Gain Roll-Off Compensation

The gain roll-off due to the 470-to-750-MHz preselect filter, and the finite BW

limitation of the LNA and C-2C attenuator in conjunction induce significant gain

roll-off near the cutoff. Vout3p (see Fig. 4.7) is a low-impedance output node of

the LNA reusable for gain roll-off compensation. Confirmed by on/off-chip

co-simulation a feedforward path (Fig. 4.19) from Vout3p with inductive peaking

and amplification realizes a low-Q highpass characteristic. The gain block of �1

implies cross-connection of the differential terminals. It compensates the passband

roll-off due to the external preselect filter, the LNA and the C-2C attenuator. The

inductor LFF is differential for area savings and the amplification is based on another

inverter amplifier A5. Since it is a low-Q peaking, the technique is insensitive to the

absolute value of LFF. An error amplifier loop around Mr generates a regulated

1 � VDD supply for reliable operation of A5. The error amplifier is based on a

differential pair with a current mirror load. Its current tail NMOS is diode-connected

to allow self-biasing, avoiding any overstress when the 2 � VDD ramps up. This

current tail is sized to consume a voltage stress of ~0.5 � VDD to reduce the voltage

stressed on the differential pair and current mirror. The simulated passband flatness

with and without compensation are depicted in Fig. 4.20. The passband flatness is

improved by 2.55 dB.

(Reference)1xVDD

-1

-+

A5

Gain Roll-off Compensation

(VDC ª1xVDD)

Mr

Mr

VoutTo NZ

VSSVSS

VSSVSS

CFF

LFF

2xVDD

2xVDD

1xVDD(Buffered)

Vout3p

~1.5xVDD

~0.5xVDD

Fig. 4.19 Simplified schematic of the feedforward gain roll-off compensation path


4.4 Experimental Results, Discussions and Benchmarks

Prototypes of the RF front-end have been fabricated in a 1-V 90-nm CMOS process.

The die micrograph and test fixture for resisting the ambient GSM signals from

affecting the test results are shown in Fig. 4.21a and b, respectively. The RF front-

end employs a single 2-V supply. It occupies 0.28-mm2 active area and is filled

symmetrically by obligatory dummy tiles to avoid mechanical strain differences.

The metal lines are set to 1 mm width per 1 mA DC current to prevent electro-

migration. An inductive-peaking 50-O test buffer was designed to drive the

equipments since the loading effect of the buffer cannot be simply de-embedded.

Figure 4.22a–c show theRF performancesmeasuredwith different preselect filters.

The measured peak voltage gain ranges from 24.9 to 26.5 dB and the minimum NF of

the RF front-end ranges from 3.5 to 3.9 dB, after de-embedding the loss of the RF

switch, balun and preselect filters. The in-band S11 is below �10 dB in all modes. In

TV-GSM interoperation mode, the rejection at GSM-900 uplink measures 68 dB, and

less than 0.7-dB gain roll-off within 470–750 MHz. Since the GSM-rejection filter is

realized in a discrete form, post-tuning for alignment is necessary to ensure a stable

and accurate notching at GSM-900 uplink against PVT. The manufacturable imple-

mentation of the filter prototypes should be with LTCC technology [19, 20] in

the next phase, which can have an accurately controlled frequency response.

Figure 4.23a and b show the voltage gain and gain error, NF and IIP3, measured

against the gain control words, respectively. The gain step error is within �1 dB

throughout a gain control range of 46 dB. It is believed that this error can be mainly

attributed to the C-2C attenuator, which should be re-optimized with the parasitic

capacitance caused by the deep-n-well diodes and the density tilings.

24

25

26

27

28

29

450 750650550

Frequency (MHz)

w/ compensation

w/o compensation

Vol

tage

Gai

n (d

B)

2.55 dB

Fig. 4.20 Simulated magnitude responses of the RF front-end with and without gain roll-off

compensation

4.4 Experimental Results, Discussions and Benchmarks 73

Throughout a 46-dB gain-control range, the IIP3 ranges from �5.5 to +4 dBm

under a 2-tone test at 400 and 500 MHz. Nevertheless, when the RF front-end is

switched to the low-gain mode (10-dB gain back-off), an IIP3 of �1.6 dBm

together with a minimum NF of 6.4 dB is adequate to pass the DVB-H L1 pattern

test with low sensitivity degradation. The RF front-end excluding the test circuitry

consumes 15 mW, out of which 10 mW is due to the LNA and the C-2C attenuator

(plus its associated bias circuit).

The desensitization of the RF front-end to the GSM-900 interference is

characterized by using two 2-tone tests as shown in Fig. 4.24. A 2-tone test at 0.5

and 0.7 GHz measures an IIP3 of �5.5 dBm. With a preselect filter notching at the

0.9 GHz, the 2-tone test at 0.7 and 0.9 GHz shows that the generated third-order

intermodulation distortion (IM3) becomes insignificant.

With no access to industrial long-term reliability testers, the reliability of the

chip was justified by operating it continuously at room temperature for 3 days. No

detrimental effect on the performance was noted. Due to a similar reason, the ESD

robustness could not be strictly characterized experimentally. The achieved ESD-

protection level is based on simulations. Comprehensive system-level

measurements including EVM degradation in a TV-GSM co-integrated scenario

should be chased in the latter stages of the research, with the presence of the digital

demodulator and other analog-baseband circuitry.

There is no similar on/off-chip co-design RF front-end reported in the literature

for direct performance comparison. Nevertheless, it is relevant to compare the

combined performance of the LNA and C-2C attenuator with the state-of- the-art

CMOS variable-gain low-noise amplifiers (VGLNAs) [12, 21, 22] in Table 4.1.

Fig. 4.21 (a) Test fixture for resisting the ambient GSM signals and (b) chip micrograph of the RF

front-end


-60

-50

-40

-30

-20

-10

0

10

20

30

50 100 150 200 250 300 350 400 450 500

5

10

15

20

25

30

35

40

45

0

NF

S11

Voltage gain

Frequency (MHz)

Vol

tage

Gai

n an

d S

11 (

dB)

Vol

tage

Gai

n an

d S

11 (

dB)

Vol

tage

Gai

n an

d S

11 (

dB)

NF

(dB

)N

F (

dB)

NF

(dB

)

In-band

-20

-15

-10

-5

0

5

10

15

20

25

30

50 350 650 950 1250 1550 18500

5

10

15

20

25

30

35

40

45

50

Frequency (MHz)

NF

S11

Voltage gainIn-band

-50

-40

-30

-20

-10

0

10

20

30

0

5

10

15

20

25

30

35

40

50 350 650 950 1250 1550 1850

Frequency (MHz)

NF

S11

Voltagegain In-band

a

b

c

Fig. 4.22 Measured RF performances of the RF front-end with the corresponding preselect filters

for: (a) 170-to-240-MHz band, (b) 470-to-860-MHz band and (c) 470-to-750-MHz band


-18

-13

-8

-3

2

7

12

17

22

27

-3

-2

-1

0

1

2

3

Gai

n E

rror

(dB

)

Vol

tage

Gai

n (d

B)

Gain Control Word

0 10 20 30 40 50 60

Low Gain Mode

High Gain Mode

Voltage Gain

Gain Error

-23

32

0

4

8

12

16

20

24

28

32

36

-25

-20

-15

-10

-5

0

5

10

15

20

Low Gain Mode

High Gain Mode

Low Gain ModeHigh Gain Mode

Gain Control Word

0 10 20 30 40 50 60

NF

IIP3

IIP3

(dB

m)

NF

(dB

)

a

b

Fig. 4.23 Measured RF performances against the gain control word at 600 MHz: (a) voltage gain

and gain error, and (b) NF and IIP3

-90

-70

-50

-30

-10

10

30

-45 -35 -25 -15 -5 5

0.5 0.70.3 0.9f(GHz)

IM3Fundemental

IM3

0.7 0.90.5 1.1f(GHz)

IM3Fundemental

IM3

IM3Fundemental

-5.5 dBm

Input Power (dBm)

Out

put P

ower

(dB

m)

Fig. 4.24 Linearity measurements with 2-tone tests at: 0.5 and 0.7 GHz, 0.7 and 0.9 GHz


Table

4.1

Perform

ance

summaryandbenchmarkwiththestate-of-the-artCMOSVGLNAs

Thiswork

[12]

[21]

[22]

Frequency

(MHz)

170–240

470–750a

470–862

470–862

470–870

174–245

450–862

NF(dB)

3.8

3.9

3.5

2.6

4.3

3.0

4.5

Max.voltagegain(dB)

24.9

26.2

26.5

23

16

28

25

Rejectionat

GSM-900uplink(dB)

67b

68b

2b

n/a

n/a

n/a

n/a

ESD

protection/level

(V)

Yes/4

kc

no

no

Yes/n/a

IIP3(dBm)@

gain(dB)

�5.5

@26.2

�5.4

@23

�1.5

@16

�5to

�4@

25

�1.6

@16(low-gainmode)

+0.6

@9

Variable

gainrange(dB)

46

14

33

50

Power

(mW)@

VDD(V

)10@

2(LNA

+C-2

Cattenuator)

40@

1.2

22@

1.8

16@

1.8

15@

2(+

also

I/Qmixer

drivers)

Activearea

(mm

2)

0.283

0.067

0.32

0.52

Circuittopology

Differential

Single-endin

Single

end

Differential

Differential

out

Technology

90nm

CMOS

90nm

CMOS

0.18mm

CMOS

0.18mm

CMOS

aTV-G

SM

inter-operationmode

bWithexternal

filters

cTheESDprotectionlevel

isbased

onhuman

bodymodel

(HBM)simulation


With similar NF and linearity performances, this work is advantageous for its lowest

power consumption, multi-standard conformity and TV-GSM interoperability.

The chip area is much larger than [12] due to the reason that here a wider gain

range is realized, and additionally two I/Q mixer drivers and one gain-roll-off

compensation path are implemented. The mixer drivers are capable to drive both

resistive and capacitive loads with low gain and BW reduction.

4.5 Summary

This design example has demonstrated thatRF circuits reliably powered by an elevated

VDD are capable of achieving high performances with low power consumption and no

reliability risk. The presented proof-of-concept prototype is a 2 � VDD-enabled

mobile-TV RF front-end with TV-GSM interoperability. Verified in a 1-V 90-nm

CMOSprocesswith standard1-V thin-oxidedevices, the circuit coredraws 15mWat a

custom-elevated 2-V supply. In TV-GSM interoperation mode, an inductive-peaking

feedforward path evens out the passband to 0.7-dB variation, while showing 68-dB

rejection at the GSM-900 uplink. The presented stress-conscious circuit architectures

and self-bias techniques are generally applicable for different designs. It is believed

thatHV-enabledcircuitswithdesign-for-reliability possess a highpotential inboosting

RF circuit performances in sub-1 V technologies at low cost.

References

1. P.-I. Mak, S.-P. U and R. P. Martins, “Transceiver Architecture Selection – Review, State-of-

the-Art Survey and Case Study,” IEEE Circuits and Systems Magazine, Issue 2, pp. 6–25,

Jun. 2007.

2. Vassilios, K. Vavelidis and N. Haralabidis, et al., “A 65 nm CMOS Multistandard, Multiband

TV Tuner for Mobile and Multimedia Applications,” IEEE J. Solid-State Circuits, vol. 43,pp. 1522–1533, Jul., 2008.

3. D. Im, H.-T. Kim, and K. Lee, “A CMOS Resistive Feedback Differential Low-Noise

Amplifier with Enhanced Loop Gain for Digital TV Tuner Applications,” IEEE Trans. onMicrowave Theory and Techniques, vol. 57, no. 11, pp.2633–2642, Nov. 2009.

4. J.A. Weldon, R. S. Narayanaswami and J. C. Rudell, et al., “A 1.75-GHz Highly Integrated

Narrow-Band CMOS Transmitter with Harmonic-Rejection Mixer,” IEEE J. Solid-StateCircuits, vol. 36, no. 12, pp. 2003–2015, Dec. 2001.

5. C.-Y. Cha, H.-B. Lee, and K. K. O, “A TV-Band Harmonic Rejection Mixer Adopting a gm

Linearization Technique,” IEEE Microw. and Wireless Compon. Lett., vol. 19, no. 9,

pp. 563–565, Sept. 2009.

6. V. Rambeau, H. Brekelmans, M. Notten, K. Boyle and J. V. Sinderen, “Antenna and input

stages of a 470–710 MHz silicon TV tuner for portable applications,” in Proc. of Europ. Solid-State Circuits Conf. (ESSCIRC), pp. 239–242, Sept. 2005.

7. Mobile and Portable DVB-T/H Radio Access-Parts 1 and 2: Interface Specification andInterface Conformance Testing, International Standard IEC 62002-1, IEC, Oct. 2005.

8. Datasheet of TDK Low Pass Filters for DVB-H/ISDB-T DEA Series DEA200710LT-1238A1.


9. M.-C. Kuo, S.-W. Kao, C.-H. Chen, T.-S. Hung, Y.-S. Shih, T.-Y. Yang and C.-N. Kuo, “A

1.2 V 114 mW Dual-Band Direct- Conversion DVB-H Tuner in 0.13 mm CMOS,” IEEE J.Solid-State Circuits, vol. 44, no. 3, pp. 740–750, Mar. 2009.

10. D. J. Allstot, L. Xiaoyong, and S. Shekhar, “Design Considerations for CMOS Low-Noise

Amplifiers,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 97–100., Jun.2004.


CMOS for Full-Band Mobile TV Tuners,” IEEE Trans. on Circuits and Systems – I: RegularPapers, vol. 56, no. 5, pp. 933–942, May 2009.

12. L. Tripodi and H. Brekelmans, “Low-Noise Variable-Gain Amplifier in 90-nm CMOS for TV

onMobile,” in Proc. of Europ. Solid-State Circuits Conf. (ESSCIRC), pp. 368–371, Sept. 2007.13. K. Ishida, A. Tamtrakarn, T. Sakurai and H. Ishikuro, “An Outside-Rail Opamp Design

Targeting for Future Scaled Transistors,” in Proc. of Asian Solid-State Circuits Conf.(A-SSCC), pp. 73–76, Nov. 2005.

14. Y.-W. Hsiao and M.-D. Ker, “A 5-GHz Differential Low-Noise Amplifier with High Pin-to-

Pin ESD Robustness in a 130-nm CMOS Process,” IEEE Trans. on Microwave Theory andTechniques, vol. 57, no. 5, pp.1044–1053, May 2009.

15. J. Hu, M. Felder and L. Ragan, “A Fully Integrated Variable-Gain Multi-tanh Low-Noise

Amplifier for Tunable FM Radio Receiver Front-End,” IEEE Trans. on Circuits and Systems –I: Regular Papers, vol. 55, no. 7, pp. 1805–1814, Aug. 2008.

16. L. Larcher, D. Sanzogni and R. Brama, et al., “Oxide Breakdown After RF Stress: Experimen-

tal Analysis and Effects on Power Amplifier Operation,” in Proc. of Int. Reliability PhysicsSymp., pp. 283–287, Mar. 2006.

17. Datasheet of Mini-Circuits, JTX-2-10 T, RF Transformer.

18. Datasheet of Anadigics, AWS5523, SP3T Switch.

19. G. Brzezina, L. Roy, and L. MacEachern, “Design Enhancement of Miniature Lumped-Element

LTCC Bandpass Filters,” IEEE Trans. on Microwave Theory and Techniques, vol. 57, no. 4,pp. 815–823, Apr. 2009.

20. K. Huang and T. Chiu, “LTCC Wideband Filter Design with Selectivity Enhancement,” IEEEMicrow. and Wireless Compon. Lett., vol. 19, no. 7, pp. 452–454, Jul. 2009.

21. J. Xiao, I. Mehr and J. Silva-Martinez, “A High Dynamic Range CMOS Variable Gain

Amplifier for Mobile DTV Tuner,” IEEE J. Solid-State Circuits, vol. 42, p. 292–301, Feb.,2007.

22. T. Kim and B. Kim, “A 13dB IIP3 Improved Low-Power CMOS RF Programmable Gain

Amplifier using Differential Circuit Trans-conductance Linearization for Various Terrestrial

Mobile D-TV Applications,” IEEE J. Solid-State Circuits, vol. 41, pp. 945–953, Apr., 2006.

References 79

Chapter 5

A Mixed-Voltage Unified Receiver Front-End

for Full-Band Mobile TV in 65-nm CMOS

5.1 Introduction

With improved device parasitics in nm-length CMOS processes, wideband RF

circuits offer the desired compactness and power efficiency for realizing multi-

band multi-standard radios. This chapter describes a receiver front-end (RFE)

targeting the mobile-TV applications using mixed-voltage techniques. It covers

the VHF-III (174–248 MHz), UHF (470–862 MHz) and L (1.4–1.7 GHz) bands,

where standards like T-DMB, ISDB-T, DVB-H and DMB-T are resided. In order to

meet the noise and linearity specifications [1], while avoiding external baluns or

repeated RFEs that were still common in existing solutions [1, 2], a number of

circuit techniques are proposed to enhance the performance, power and area

efficiencies [3]. Together they lead to state-of-the-art performance, while saving

58% area compared to the 1.1 mm2 reported in [2]. The key design considerations

are outlined as follows.

A wideband balun low-noise amplifier (LNA) can nullify the cost and insertion

loss of external balun, but might suffer from low IIP2 and weak output balancing

compared to its fully-differential counterpart. The output balancing of a balun-LNA

significantly affects the IIP2 of the mixers following it. The common-gate (CG)

common-source (CS) balun-LNA [4] serves as an example. Although noise cancel-

lation and admittance scaling techniques can lower the NF to <3 dB, the imbalance

load and bias current between the CG and CS branches weakens the IIP2 and output

balancing. Output buffers were employed to alleviate those issues at the expense of

extra power. Alternatively, in [5], IM2 cancellation feedback was introduced to

enhance IIP2. This technique, however, penalizes the output bandwidth (BW) and

noise figure (NF), while the problem of weak output balancing remains unsolved. In

this work, a gain-boosting current-balancing balun-LNA is proposed. It not only

addresses the aforementioned issues, but also offers adequate input matching over

variable gain control (VGC). The VGC assists the balun-LNA in handling high

input power levels.



81

Harmonic mixing and intermodulation distortion are critical concerns of wideband

RFEs. The former is due to the hard switching nature of MOS mixers, i.e., blockers

located at the harmonics of the LO become co-channel interferers after

downconversion. The latter is due to the potential co-existence of large amount of

blockers throughout the passband. Regarding this, especially for interoperableterminals as shown in Fig. 5.1, external SAW filtering is still the most reliable

solution [6]. The cellular transmitter can deliver power as high as 30 dBm whereas

the isolation between the internal terminals is just around 10–15 dB. If uninterrupted

operation of cellular and tuner is desired, external SAW filtering is highly necessary

to avoid saturation. As shown in Fig. 5.2, the SAW filters (e.g., [7]) can specifically

notch to the very nearby cellular bands.

VHF III

UHF

L

SAW

SAW

SAW

SAW

LimitedIsolation

WCDMA

GSM WiFi

TV

BT

FM

Co-Integration Terminal

Fig. 5.1 Limited isolation in co-integration terminal

UHF L

170 245 470 860 1400 1700

3 x VHF III 5 x VHF III

VHF III

3 x UHF

2580

8-PhaseHR Mixing

8-PhaseHR Mixing

4-PhaseQuad. Mixing

[MHz]

SAW

GSM 900

GSM 1800

WiFiWCDMA

SAW SAW

Wideband Balun-LNA

Fig. 5.2 Overview of SAW filtering, balun-LNA’s bandwidth and mixing strategies

82 5 A Mixed-Voltage Unified Receiver Front-End for Full-Band Mobile TV. . .

With adequate pre-filtering the linearity of the RFE will be mainly limited by

the out-of-channel IIP2 and IIP3 [7]. Here, the mixer is merged with a current-mode

third-order lowpass filter (LPF) for improving the out-of-channel linearity,

while saving power and area for its simplicity. A third-order stopband rejection

profile suffices for shifting most baseband (BB) functions to the digital domain via

low-power analog-to-digital converters [2, 7].

When receiving the VHF-III and UHF bands, harmonic-rejection (HR) mixers

[8] can relax the rejection profile of the external SAW filters, and minimize noise

and distortion folding (i.e., the third and fifth harmonic bands are partially within

the BW of the balun-LNA as marked in Fig. 5.2). The entailed 8-phase LO, if

generated via frequency dividers, will necessitate a high master LO frequency (fLO).In fact, the frequency range (�0.9 GHz) of the RFE in [9] is limited by the required

high fLO (7.2 GHz) for generating the 8-phase LO, which significantly increases the

power and complicates the design of the phase locked-loop (PLL) and voltage-

controlled oscillator (VCO). In this work, a direct injection-locking 4-/8-phase LO

generator (LOG) lowers the master fLO. This dividerless solution particularly suits

this receiver-only application, as the problem of “VCO pulling” is irrelevant here in

the absence of power amplifier.

This chapter is organized as follows. Section 5.2 introduces the proposed RFE

architecture, and discusses the technology features which play a key role in

device sizing and topology selection. The conventional and proposed balun-LNAs

are described in Sect. 5.3. Sections 5.4 and 5.5 present the proposed current-reuse

mixer-LPF and the direct injection-locked 4-/8-phase LOG, respectively. In Sect. 5.6,

the experimental results will be presented.

5.2 RFE Architecture and Technology Features

Figure 5.3 depicts the proposed RFE architecture headed by three external SAW

filters. It integrates a wideband balun-LNAwith VGC, dual I/Q mixers, a 4-/8-phase

LOG and dual third-order BB LPFs merged with the mixers for current-reuse and

WidebandBalun-LNAwith VGC

BBout,I

BBout,Q

LOin

Current Reuse

4-/8-Phase LOG

1: 2 :1

IC

3rd-Order LPF

Lext

VHF III

UHF

LSAW

SAW

SAW

Fig. 5.3 Proposed full-band mobile-TV RFE

5.2 RFE Architecture and Technology Features 83

current-modefiltering.One external inductor is entailed at theRF input.Thedifferential

signals from the balun-LNA are ac-coupled to the mixers to prevent the balun-

LNA’s even-order distortion products (i.e., the concern of narrowband IIP2 [10])

and 1/f noise from leaking to the BB. The mixer has two operating modes: (1)

HR mode supports the VHF III and UHF bands, using a gain ratio of 1:√2:1among the three mixer cells and an 8-phase LO [8]; (2) quadrature modesupports the L band where HR is a surplus as the harmonic bands are far out

from the band of interest. In this case, the three mixer cells are parallelized and

the LO is switched to 4 phases. A direct injection-locking LOG synthesizes the

desired 4-phase and 8-phase LOs.

In nm-length CMOS processes the back-end features and options are highly

related to the performances because of the parasitic effects. Here, the available dual

supplies (1.2 and 2.5 V) and dual-oxide transistors (thin and thick) are employed to

optimize the performances of the RFE. Dual-supplies free more design headroom in

65-nm CMOS SoC [1] and beyond [11].

The employed I/O pads are offered by the foundry. They have passed the 2-kV

Human body Mode (HBM) ESD tests, but add roughly 1-pF input capacitance that

has to be taken into account in the design phase.

5.3 Wideband Balun-LNA

5.3.1 CG-CS Noise-Canceling Balun-LNA

Figure 5.4depicts its schematic. The single-to-differential (S2D) utilizes aCGamplifier

(M1) to generate the in-phase output. The source ofM1 is dc-grounded via an external

big inductor Lext to attain a wideband impedance match. The corresponding

Vb1

C1Lext

Vin

(gm1) M1

M2(gm2=ngm1)

VDD

von

vonvIN

vop

vop

RCG

RCG

Rin ≈ 1/gm

IDC nIDCCL CLisig+

isig+

isig+ = gm1Vinisig- = -ngm1Vin

isig-

isig-

RCS=RCG/nOutput balancing

at DC only

S2DS2D

RCG/n

Fig. 5.4 CG-CS noise-canceling balun-LNA [4]


transconductanceofM1 (gm1) is 20mS, given thatRin � 1/gm1 ¼ 50O. ACS amplifier

(M2) generates the anti-phase output, and assists noise canceling of M1. The noise

contribution ofM2 can be reduced by admittance scaling, e.g., gm2 ¼ 4gm1 ¼ 80mS.

To keep a balanced output in [4] a counterbalance load was set (RCS ¼ RCG/4). This

technique regrettably cannot ensure a wideband balanced output when driving the

mixers (with the input impedance modeled as CL). This fact, in addition to the bias

current mismatch between the CG and CS branches, leads to low IIP2, weak output

balancing and limited power supply rejection ratio (PSRR). Extra output buffers only

can reduce the output imbalance at the expense of power, but the problem of low IIP2

remains unsolved.

Another concern of such a balun-LNA is that the S2D cannot be simply bypassed

at high input power level. Tuning the load (RCG and RCS) or current steering-based

VGC does not help much when the linearity is limited by the nonlinearity ofM1 and

M2. This issue will be addressed by the proposed balun-LNA.

5.3.2 Proposed Gain-Boosting Current-BalancingBalun-LNA with VGC

The Single-to-Differential Stage (S2D) – The proposed balun-LNA (Fig. 5.5a) uses

a new S2D. The first idea is to use an ac-coupled gain stage (gmx) to enhance

the gain of the CS branch (Fig. 5.5b), avoiding scaling-up of gm2 with respect to gm1

(i.e., M1 and M2 are of equal size and bias current). The second idea is to reuse the

gain generated by M2 to enhance the gain of the CG amplifier by creating a loop

gain (1 + A) aroundM1, where A is given by │vo1n/vin│ (Fig. 5.5c). Due to the single-stage structure of gmx + gm2, and the low impedance of vo1n, A is ensured to

be stable. This loop gain A not only boosts the effective gain of M1 and lowers its

noise contribution, but also reduces the minimum IDC for M1 to offer input

impedance matching. An external big inductor Lext simplifies the input impedance

match and offers a DC-current path for the CG amplifier M1.

In order to simplify the bias and save component count, gmx is realized as an

inverter amplifier (M3 and M4) with resistive feedback Rfb for self-biasing. This

self-bias structure also handily biases M1-M2 as shown in Fig. 5.5c. Comparing

with the S2D topology in [4], just one capacitor C2 and one resistor Rfb are added as

M3-M4 can be counted as parts of M2.

The Differential Current Balancer (DCB) – Balanced output impedance is critical

to achieve wideband output balancing. Here, the differential balancing is realized in

the current domain by inserting a DCB between the S2D and the load as shown in

Fig. 5.6. The DCB serves as a differential current-control current source with unity

gain, forcing isig+ ¼ �isig� ¼ isig. In principle, a cascode amplifier (M5-M6) with

cross-coupled capacitors (C3-C4) might realize the DCB [12], as what it amplifies is

the difference of the input. However, accounting for the finite output resistance of

M5-M6, a double-cascode amplifier (M5-M8, C3-C6) is adopted to achieve wideband

output balancing.

5.3 Wideband Balun-LNA 85

TheDCB also benefits the S2D in two ways: (1) the condition isig+ ¼ �isig� ¼ isighelps mapping the loop gain of the CG branch to the gain given by the CS branch,

yielding A ¼ gmx/gm1, which is a definable ratio insensitive to process if the channel-

length modulation of M1-M4 is negligible. (2) The DCB improves the balun-LNA’s

reverse isolation and linearity by lowering the swing at vo1p and vo1n, where distortionarising from the nonlinear output resistance ofM1-M4 can be minimized.

The overhead of the DCB is the extra voltage headroom when compared with a

typical cascode stage. The use of dual supplies (1.2 and 2.5 V) overcomes this

limitation and allows more voltage gain without compromising the dynamic range

(DR). A high-voltage design also offers opportunities to realize more functions in

the current domain by cascoding them under one supply rail, potentially leading to a

wider RF BW (i.e., less high impedance nodes), better linearity (i.e., small internal

signal swing) and area savings (i.e., less ac-coupling capacitor between blocks).

Nevertheless, a high-voltage design with thin-oxide MOS requires node-voltage

trajectory checks, to ensure no gate oxide and p-n junction are overstressed at

transient and steady states. The bias scheme of the balun-LNA (Fig. 5.7) is designed

isig+ = (gm1(1+ )vin

Rin ≈1/[gm1(1+ )]

S2D DCB

IDC

VDD

VDD

VDD

IDCIDC

IDCisig+ isig-

-gmxVin

-gmxVin

-gm1vin

-gm1Vin

Vb1

C2

C2

M2 (gm1)

M2 (gm1)

C1

C1

RL

RL (gm1) M1

(gm1) M1

Lext

Lext

Vin

Vin

isig+ = gm1Vinisig- = -(gmx + gm1)Vin

isig- = -(gmx + gm1)Vin

Rin ≈ 1/gm

gmx ≈ gm3 + gm4

vo3n

vo1n

vo1n

vin

vo1n

vin

vINvo3p

vo1p

isig+

isig+

isig-

isig-

gmx

gmx

gmx

M3

M4Rfb

a b

c

Fig. 5.5 Generation of the proposed S2D: (a) the overall balun-LNA. (b) Ac-coupled gain

boosting avoids mismatch of IDC. M1 and M2 are of equal size and bias current. (c) The final

topology: gain-boosting the CG via the CS, where the gain-boost stage (gmx) is a self-biased

inverter amplifier (M3 and M4)


as a single-ended replica of it, generating the bias voltages Vb1 and Vb2 for M5-M8.

Such a scheme can detect the presence of VDD25 and VDD12, ensuring no device is

overstressed in power-up/down conditions. The reliability levels are guided by the

foundry design rule manual. The scheme ensures all terminal voltages meet the

reliability guidelines provided by the foundry.

Combining the S2D and DCB, the single-to-differential voltage gain Av,diff and

input impedance Zin of the balun-LNA can be obtained

Av;diff ¼ vo3p � vo3nvin

¼ 2gm1 1þ Að Þ RL==1

sCL

� �: (5.1)

Zin ¼ 1

gm1 1þ Að Þ ==sLext==1

sCin: (5.2)

respectively. The demand of both high Av,diff and low NF promotes setting a smaller

Zin via increasing gm1, which is, however, constrained by the desire of input

impedance matching. The minimum acceptable input reflection coefficient magni-

tude Gin can be determined as

Ginj j ¼ Zin � Rs

Zin þ Rs

�� 0:32: (5.3)

1/gm5

S2D

DCBVDD25

VDD12

Vss12

RL RLIDC IDC

vo3nvo3n

vo2n

vo3pvo3p

vo1p

vo2p

CL CL

vo1n

vo1n

vo1p

isig

isig-isig+

(gm1) M1C2

C3 C4

C5 C6

C1

gmx

M2 (gm1)Rin

Vin

ZinLext Cin

Vb1 Vb1

Vb2 Vb2

M5 M6

M7 M8

(gm5)

(gm5)

Fig. 5.6 The S2D combined with the DCB. M1 and M2 are of equal size and bias current


It corresponds to a S11 value of < �10 dB. Accordingly, the tolerable ZIN for

RS ¼ 50O ranges from 26 to 97O. In this work, Zin is set to 33O (gm1¼7.5 mS and

gmx ¼ 3gm1) to enhance Av,diff and lower NF, while yielding S11 < �13 dB (3 dB

margin). Though acceptable here for the targeted frequency (0.17–1.7 GHz) in the

employed 65-nm CMOS process, it should be noted that the impedance match BW

is reduced when comparing it with a strict 50-O match.

TheGain-ControlAttenuator (ATT)–Thebalun-LNA is preceded by annMOS-onlyR-

2R network for coarseVGCas depicted in Fig. 5.8. It exploits the properties of partial

signal reflection (i.e., Zin deviates fromRS) and voltage division to realize the desired

attenuation levels. The control range was set to 18 dB, which offers a reasonable

tradeoff between IIP3 andNF at high input power levels.A 6-dB step size is related to

the gain-tuning characteristic of R-2R network when constant input impedance is

sought. The gain switching is executed via Sbypass, S1, S2 or S3 as shown in Fig. 5.9.Operating at the low-impedance input node of the balun-LNA with Lext provides thedc-ground, each nMOS enjoys a large VGS of 1.2 V for high linearity, while offering

VGC with a constant output BW. At the maximum gain, the ATT is bypassed with

Sbypass; it features a 1.8-O on-resistance (rON) under a practical device size of 200/0.06. The combined R0

in varies between 34.8 O (ATT bypassed) and 55 O (with the

ATT). Both values yield S11 < �13 dB, giving room for process variation. The

initial �2.2-dB attenuation at the highest gain is induced by the reflection and

division between ron and Rin (i.e.,�2.2 dB ¼ 20 log {[1 � (RS � R0in)/(Rs + R0

in)] ·

Rin/(ron + Rin)}.

Overdrive Protection

RLB

lb

Vb2

M4b

M3b

M1b

Mpt1

M2b

Vb1

VDD25

VDD12

VDD25 VDD12

Fig. 5.7 The bias scheme

of the balun-LNA


All MOS switches are operated in triode region with an ON-resistance value that

is either RIN or 2RIN. The size of the former is obtained according to

1

mCOX

WSW

LSWðVGS;SW � VTHÞ

zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{NMOS Switch

¼ 1

1

2mCOX

WM1

LM1

ðVGS;M1 � VTHÞ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}gm1

1þ Að Þ:

zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{Rin

(5.4)

ATT

gmx

S1 S2 S3

Sbypass

53

Rin ≈1/[gm1(1+A)]

Rin’ = rON+Rin or Rin

ATT(33W)

(34.8 or 55 W)

Rs

RFin

Rin

Rin

RinRinRin

rON=1.8W

2Rin

Rin

LextVin

C1M2

C2

M1 VDD12

VSS12

vo1p vo1n

Fig. 5.8 The balun-LNA is preceded by a passive ATT for coarse gain control

~2.2 dB attenuation

1.8 W1.8 Ω

33 W

1.8 W1.8 W

33 Ω

33 Ω

66 Ω

66 Ω66 Ω

33 Ω

33 Ω33 Ω

33 Ω

33 Ω

33 Ω

33 W33 W33 W

33 W33 W

33 W

33 W 66 W

33 W

33 Ω33 Ω

33 Ω

33 Ω 33 W33 W 33 W

8.4 dB attenuation

14.4 dB attenuation 20.4 dB attenuation

dc shortedto ground

dc shortedto ground

dc shortedto ground

dc shortedto ground

Ry=61.28 W

Rin=33 W

Ry=49.5 W

Rin=33 W

Ry=1.8 W

Rin=33 W

Ry=22 W

Rin=33 W

Rin’ = 55 WRin’ = 55 W

Rin’ = 34.8 W Rin’ = 55 W

vin

vinvin

vin

IDC,x

IDC,x

IDC,xIDC,x

Fig. 5.9 Equivalent circuits of the nMOS-only ATT in each gain step


On the left of (5.4) VGS,sw � VDD12, since all switches are switched [OFF, ON]

by [0, VDD12]. On the right VGS,SW � VDD12/2, which is set by the self-biased

topology of gmx (see Fig. 5.5c). In the employed process, VDD12 is around 4� of

the device’s threshold voltage VTH. Accordingly, an aspect ratio of Wm1/WSW

¼ 3/2 can be obtained by assuming A ¼ 3 and LSW ¼ LM1. A similar concept

applies for the MOS switch with 2Rin ON-resistance. The scheme is acceptable for

coarse VGC as process variation will affect the accuracy of the step size.

It is noteworthy that the bias current of M1 has to be passed through the ATT.

Considering the impedance back to the ATT (labeled as Ry), the equivalent resis-

tance at each attenuation step varies between 1.8 and 61.28 O. The source of M2,

thus, employs an ATT replica to track this variation (Fig. 5.8), matching the bias

currents of the CG and CS branches against VGC.

Performance Optimization via Using Dual VDD’s – The NF of the balun-LNA is

analyzed based on the simplified noise model shown in Fig. 5.10. For simplicity,

channel-length modulation is neglected and Ms is used to represent the equivalent

of M2-M4 in parallel. The transconductance gms of Ms correspondingly represents

gm2 + gm3 + gm4. Regarding a and g showed in Fig. 5.10 they are the process- and

bias-dependent parameters of the devices, respectively. The differential output

noise voltages due to each source are obtained as,

v2n;Rs;diffout ¼ Vn;RsgmsRL

�� 2 (5.5)

v2n;M1;diffout ¼ 0 (5.6)

v2n;Ms;diffout ¼ In;Ms

2RL

1þ gmsRS

��2 (5.7)

v2n;M5;diffout ¼ In;M5

gm1 1þ A0� �

gm1 1þ A0� �þ 1

RS

� 1

2

" #RL

��2

(5.8)

v2n;M7;diffout ¼ 0 (5.9)

v2n;RL;diffout ¼ In;RLRL

�� 2 (5.10)

where the loop gain around the CG branch is re-defined as 1 + A0 to match the set

assumption in this Section.With gm1 ¼ gm2, 1 + A0 is relatedwith a gm ratio given by,

1þ A0 ¼ 1þ gm3 þ gm4

gm1

(5.11)


The NF of the balun-LNA can be calculated by dividing the total output noise

power due to all devices by the noise power of RS leading to,

NF ¼ 1þ

v2n;M1;diffout þ v2n;Ms;diffout þ 2v2n;M5;diffout

þ2v2n;M7;diffout þ 2v2n;RL;diffoutv2n;Rs;diffout

(5.12)

If the input impedance match is exact (Rin ¼ RS), we can set gm1(1 + A0) ¼ gms

¼ 1/RS to simplify (5.12) as,

NF ¼ 1þ gaþ 2RS

RL: (5.13)

Equation 5.13 is the same as that of CG-CS noise-canceling balun-LNA withoutadmittance scaling: gmCG ¼ gmCS ¼ 1/RS [12]. The main difference here is the

reduction of the minimum Idc for 50-O matching by a factor of 1 + A. A smaller Idcmight compromise the linearity, but the presence of the DCB helps isolating the

In,RL

In,M7

2

2

In,M52

In,M72

In,M12

In,Ms2

Vn,Rs2

VDD

RL RL

RL

M5

M1

MS

MS = M2//M3//M4gms = gm2+gm3+gm4

M6

C3 C4

RS

C5 C6

M7 M8

= 4KTgm7 ag

In,M52

= 4KTgm5 ag

In,Ms2

= 4KTgms ag

In,M12

= 4KTgm1

Vn,Rs2

= 4KTRS

ag

In,RL2

=4KTvo3nvo3p

Fig. 5.10 Simplified noise model of the proposed balun-LNA. g is the excess channel thermal

noise coefficient. a is gm/gd0, with gm the device transconductance and gd0 the zero-bias channel

conductance


high-swing output node from the S2D, reducing the effect of S2D’s nonlinear

output resistance. For a conservative value of g/a ¼ 4/3, the NF is >3 dB.

For that reason, as mentioned before, the targeted Rin is 33 O to achieve better

NF and gain. The factual value can be computed via (5.12) under Rin ¼ 33 O.The 2.5-V supply allows a bigger RL without degrading DR. In the size optimi-

zation the optimum range that can balance IIP2, IIP3 and NF was found to be within

340–570 O under a 150-fF load as shown in Fig 5.11. In this region, the NF is

<2.8 dB and the IIP2/IIP3 is > + 45/+3 dBm. RL was chosen to be 410 O for a

maximum IIP2. The in-band NF justified at boundaries of the desired BW (0.17 and

1.7 GHz) has a difference of<0.1 dB. The corresponding mid-band gain is 25.6 dB

and the output BW is around 2.6 GHz. The size of the components of the balun-

LNA is summarized in Table 5.1.

Startup Considerations – Mixed-voltage circuits raise the concern of improper

power-up/-down sequences. As depicted in Fig. 5.12, in case VDD,12 has a delay in

start-up with respect to VDD25,M1-M4 are in the cutoff region overstressed by VDD25.

The proposed solution is to add two small-size thick-oxide PMOS transistors Mpt1

and Mpt2 to vo1p and vo1n, respectively. With them, the dc voltages at vo1p and vo1ncan be controlled to be within VDD12 when M1-M4 are still in cutoff region. Once

VDD12 ramps successfully, Mpt1 and Mpt2 are automatically turned off. A similar

operation holds in power-down condition when VDD12 is removed before VDD25.

2

2.3

2.6

2.9

3.2

3.5

200 700 1200 1700

NF at 170 MHz

RL (Ω)

NF

(dB

)

IIP2,

IIP

3 (d

Bm

)

@ CL = 150 fF

NF at 1.7 GHz

OptimumWindow

IIP3

IIP2

-15

0

15

30

45

60

Fig. 5.11 Simulated IIP2, IIP3 and NF with respect to RL. The optimum window of RL is

highlighted

Table 5.1 Components size

of the balun-LNAValue Value

M1, M2 2.4/0.07 � 6 C1 4 pF

M3 (for gmx) 2.4/0.06 � 20 C2 6 pF

M4 (for gmx) 2.4/0.06 � 40 C3–C6 2 pF

Rfb (for gmx) 15 kO CLa 150 fF

M5–M8 2.4/0.18 � 6 RL 410 OLext 100 nHaFor simulation only


Differential Balancing – The progression of gain and phase balancing within the

balun-LNA are assessed as shown in Fig. 5.13a and b, respectively. The gain-phase

imbalances are corrected progressively from [vo1p, vo1n] to [vo2p, vo2n] after the firstbalancing, and eventually to [vo3p, vo3n] after the second balancing. The in-band

gain and phase mismatches are <0.037 dB and <1.87�, respectively. From 0.1 to

10 GHz, the former is still acceptably small (<0.2 dB), whereas the latter is limited

at the low frequency side (<3.5�) due to the highpass characteristic of C3-C6 (2-pF

MiM capacitors) that were not oversized due to the add-on parasitics. The output

balancing can be affected by device mismatches. A matching-conscious layout is

entailed between M1 and M2, the differential RL and DCB.

PSRR – The voltage gain from each supply and ground rail to the differential output

(Vo3p�Vo3n) has been simulated as shown in Fig. 5.14. Due to a symmetrical RL and

the equal (and high) output impedance of the DCB, the PSRR with respect to VDD25

is > 48.1 dB. This is a significant result as VDD25 is generally just utilized for I/Os

featuring weaker quality when comparing it with the core supply. Differently, the

PSRR with respect to VDD12 and VSS12 are just 13.5 and 12.75 dB, respectively.

Multiple pads were therefore assigned between VDD12 and VSS12 to minimize noise

coupling and the effect of bondwire inductance on performance degradation.

VGC on Performances – Accounting a bondwire inductance of roughly 3.5 nH, anda 1-pF input parasitic capacitance due to the bondpad and ESD protection circuitry,

the simulated AC responses, S11 and NF against gain control are shown in

Fig. 5.15a–c, respectively. S11 < �10 dB is achieved up to 4 GHz. For the linearity

against VGC (Fig. 5.16), from the highest to lowest gain levels, the IIP2 ranges

Automatic Overdrive Protection for M1– M4

0t

V and I When VDD25 ramps up beforeVDD12 M1 - M4 are cutoff

vo1p

vo1p,n

vo1n

VDD25

VDD25

Mpt1

Mpt1,2 ensures vo1p,n< VDD12

Mpt1,2 is cutoff whenin normal operation

IMpt1

IMpt1,2

IMpt2

Mpt2

VDD25VDD12

VDD12

Fig. 5.12 A simple scheme for overdrive protection (the notations are referred to Fig. 5.6)


-1

0

1

2

3

4

5

6

0.1 1 10

Frequency (GHz)

Gai

n Im

bala

nce

(dB

)P

hase

Imba

lanc

e (D

egre

e)

-140

-120

-100

-80

-60

-40

-20

0

20

0.1 1 10

Frequency (GHz)

[vo2p, vo2n]

[vo2p, vo2n]

[vo3p, vo3n]

[vo3p, vo3n]

[vo1p, vo1n]

[vo1p, vo1n]

a

b

Fig. 5.13 Simulated gain (a) and phase (b) balancing progress inside the balun-LNA

-60

-50

-40

-30

-20

-10

0

10

20

30

0.1 1 10

Frequency (GHz)

20. lo

g(v o

3p-v

o3n)

(dB

)

From VDD25

From VSS12

From VDD12

From RFin

Fig. 5.14 PSRRs with respect to VDD25, VDD12 and VSS12

-30

-20

-10

0

10

20

30

0.1 1 10

Frequency (GHz)

Diff

. Vol

tage

Gai

n (d

B)

-40

-30

-20

-10

0


S11

(dB

)N

F (

dB)

0

10

20

30

40

50

0.1 1 10

Frequency (GHz)

In Band NF@Highest Gain = 2.2 to 2.7 dB

Rin= 55Ω Rin= 34.8Ω

a

b

c

Fig. 5.15 Simulated balun-LNA’s (a) AC responses and (b) S11. (c) NF, against gain control


from +45 to +59 dBm, whereas the IIP3 ranges from +5.6 to +17 dBm. The former

is loosely related with the VGC. The latter is due to the ATT, which attenuates the

input signal before it reaches the S2D.

5.4 Current-Reuse Mixer-LPF

5.4.1 Circuit Description

Typically inwireless receivers, themixer andBBLPF are separately designed, and the

signal transfer is processed with in voltage (Fig. 5.17a). It implies that the out-of-

channel interferers are amplified at the output of the mixer prior to adequate filtering.

Here, with the use of a 2.5-V supply, more voltage headroom promotes the use of a

current-mode LPF to interface (cascode) with the mixer (Fig. 5.17b), offering ade-

quate filtering prior to BB I-V conversion. Figure 5.18 shows the block diagram of the

proposed I/Q mixer-LPF with switchable modes between HR mixing and simple

quadrature mixing. The circuit implementation is shown in Fig. 5.19, a polyphase

double-balanced structure is employed to lower the LO-to-BB leakage and even-order

distortion while rejecting the third and fifth harmonics of the LO. the HRmixer core is

based on a switched-gm cell [13], which is favored against the Gilbert cell in terms of

operating voltage and LO amplitude requirement.Moreover, the LOpath induces only

common-mode noise at the outputs that can be rejected differentially. Also due to the

2.5-V supply,Mm1-Mm4 can feature a large VGS, and use source degeneration (Rdeg) to

enhance their linearity and output resistance.

The LO buffers realized as CMOS inverters use cross-connected weak latches to

minimize the duty-cycle distortion. Small LO buffer’s ON-resistance reduces

the RF-to-LO coupling since Mm1-Mm4 can be well-grounded when they are in

0

5

10

15

20

25

30

5 15

Voltage Gain (dB)

40

45

50

55

60

0.9 & 1 GHz

2-Tone Test @

25

IIP3

(dB

m)

IIP2

(dB

m)

Fig. 5.16 Simulated IIP2 and IIP3 against gain control


BB

LO

RF

VoltageDomain

VoltageDomain

LO

RF

CurrentDomain

VoltageDomain

I/V Conversion

RBB

BB

a b

Fig. 5.17 (a) Voltage-mode mixer cascades with voltage-mode LPF. (b) Current-mode mixer

cascodes with current-mode LPF

0° 180°

-45° 135°

45° 225°

90°

2gm

gm

gm

gm

gm

270°

45° 225°

135° 315°(90° 270°)

(90° 270°)

(0° 180°)

(0° 180°)

Switchable LOI Waveform

Switchable LOQ Waveform

I-to-V

I-to-V

Current-Mode 3rd

Order LPF

Current-Mode 3rd

Order LPF

Voutp,Q

Voutp,I

Voutn,Q

Voutn,I

VRFn

VRFp

2gm

Fig. 5.18 Block diagram of the proposed I/Q mixer-LPF

5.4 Current-Reuse Mixer-LPF 97

Current-Mode Biquad LPF: HBiq(s)

2gm,eff

(8-Phase LO)(4-Phase LO)

LO Buffers

SwitchablePhase

from LOG

2

EquivalentCircuit

VDD25

RBBCBB /2

Cf2 /2

Cf1 /2

Cf1 /2

L=Cf2 /gmf2L=Cf2 /gmf

RBBML1 ML2

VO3p,BB

VO1p,BB

Rdeg

Vb

Vo2n,BBVo2p,BB

Vb

iout(s)

iin(s)

iout(s)

iin(s)

Mf3 (gmf)

Mf1 (gmf)

(gmf) Mf4

(gmf) Mf2

Mm1Mm2 Mm3Mm4

VO3n,BB

VO1n,BB

Vinn

VinpVinp

gm,eff

gm,eff

3rd-OrderLPF

135°180°135°180°180°180°

-45°0° 45°0° 0° 0°

a

b

Fig. 5.19 (a) Circuit implementation of the proposed current-reuse I/Q mixer-LPF. (b) the

schematic and equivalent circuit of the HBiq(s)


the ON-state. Assuming a square-wave-like LO, the conversion gain (CG) in

4-phase and 8-phase operations are given by

CG4PðsÞ ¼ cgm;eff 2þffiffiffi2

p RBB==

1

sCBB

� �HBiqðsÞ (5.14)

CG8PðsÞ ¼ cgm;eff 2ffiffiffi2

p RBB==

1

sCBB

� �HBiqðsÞ (5.15)

where c ¼ 2/p, accounting that only the first harmonic of the LO contributes to the

gain. On the other hand, gm,eff denotes the effective transconductance of Mm1-Mm4

after resistive degeneration, i.e., gm,eff ¼ gm,Mm1/(1 + gm,Mm1Rdeg). CG4p(s) intrinsi-

cally shows 1.6-dB higher gain than CG8p(s) since the polyphase paths in the 4-phase

mode are directly parallelized. This gain difference is indeed helpful as the L band

that uses a 4-phase LO is located much close to the �3-dB cutoff frequency of the

balun-LNA, where more gain droop exists. HBiq(s) is the frequency response of a

current-mode Biquad [14] with Q and cutoff frequency o0 as given by,

HBiqðsÞ ¼ ioutðsÞiinðsÞ ¼

g2mf

Cf1Cf2

s2 þ sgmf

Cf1

þ g2mf

Cf1Cf2

Q ¼ffiffiffiffiffiffiffiCf1

Cf2

ro0 ¼ gmfffiffiffiffiffiffiffiffiffiffiffiffiffi

Cf1Cf2

p (5.16)

This Biquad exhibits several distinct advantages [14]: (1) the Q of the complex

pole pair is insensitive to process; (2) there is no passband loss as the current gain at

dc is unity; (3) a constant-Q BW control can be achieved with C1 and C2 tuned

together; (4) the Biquad exhibits a zero in the noise transfer function of Mf1-Mf4

(Fig. 5.20a), resulting in in-band noise reduction. This property breaks the funda-

mental kT/C limit of the classic LPFs where the noise behavior should follow the

LPF’s profile (Fig. 5.20b); (5) high linearity is achieved since filtering is performed

in the current mode, while Cf1 filters out the high-frequency signals prior to

reaching the active elements (Mf1-Mf4); (6) the noise and linearity are tradable

with the cutoff frequency. A higher cutoff rejects more in-band noise because of the

zero exhibited at DC (Fig. 5.20c).

These good noise and linearity properties render it as a wise “first filter” in

direct-conversion receivers. Here, by integrating it with the mixer having a real pole

load [RBB//(1/sCBB)], a third-order LPF can be constructed without extra bias

currents, V-I and I-V converters that dominate the NF [14]. The BB output

common-mode voltage is controlled via a common-mode feedback circuit around

ML1-ML2. The targeted cutoff frequency is 12 MHz to balance the NF and selectiv-

ity. An automatic cutoff tuning is beyond the scope of this work, but should be

considered when accounting for process and temperature variations. A constant-QBW tuning can be achieved via co-tuning Cf1, Cf2 and CBB. The transistorsMf1-Mf4

are realized as thick-oxide MOS with a big device size to minimize NF and reduce

channel-length modulation. The latter is essential for an accurate filtering profile.


The protection circuit depicted in Fig. 5.12 is also applied here at vo1p,BB and

vo1n,BB to prevent Mm1-Mm4 (thin-oxide devices) from being overstressed during

the start-up/power-down condition. The bias circuit of the mixer-LPF is shown in

Fig. 5.21. The component sizes are given in Table 5.2.

5.4.2 Noise Figure

The simplified noise model of the mixer-LPF is shown in Fig. 5.22. Similar to the

noise analysis in Sect. 5.3, it can be derived that the single-side band (SSB) NF is

given by

NFSSB;MixLPFðsÞ ¼ 1

c2þ 2ggm;effRSc2

þ2

RBB

Rsc2g2m;effH2BiqðsÞ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

switched�gm mixer contribution

þ

2ggmf

sgmf

Cf2

s2 þ sgmf

Cf1

þ g2mf

Cf1Cf2

2664

37752

RSc2g2m;effH2BiqðsÞ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

LPF contribution

þ2ggmf

sCf2

sCf2 þ gmf

� �2

RSc2g2m;effH2BiqðsÞ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

LPF contribution

(5.17)

“kT/C limit”

Flicker

DesiredSignal

Noise ωout-off1

Noise ωout-off2

Blockers

High ωout-off2reduces noise

Low ωout-off2rejects more Blockers

ωcut-off

Filter Profile

Noise

DesiredSignal

ωωpole ω

ωout-off2ωout-off1 ω

a b

c

Fig. 5.20 (a) In-band noise characteristic of Gyrator-C Biquad. (b) In-band noise characteristic of

generic filter. (c) Cutoff frequency poses a tradeoff between in-band noise and out-of-channel

linearity


where CBB is omitted and the noise due to the Rdeg is ignored to simplify the

expression. The first three terms of (5.17) are originated from the switched-gmmixer and are the same as those derived in [13]. The last two terms are due to the

Biquad, both are noise-shaped by an in-band zero as expected. Further design

details of the mixer and LPF are omitted as their individual designs have been

extensively addressed in [13] and [14], respectively.

5.4.3 Simulation Results

The filtering characteristic of the mixer-LPF has been assessed. The passband gain

and stopband rejection are increased progressively as shown in Fig. 5.23. The bias

scheme of themixer-LPF is a singled-ended replica of it generatingVb,BB1 andVb, BB2,

reducing the effects of process variation and mismatch. In Monte-Carlo simulations

Table 5.2 Components

sizes of the mixer-LPFValue Value

Mm1,–Mm4 (gm) 2.4/0.06 � 4 Cf1 160 pF

Mm1,–Mm4 (√2gm) 3.4/0.06 � 4 Cf2 30 pF

Mf1–Mf4 8.2/1 � 20 CBB 18 pF

Ml1, Ml2 8.2/0.5 � 160 RBB 1.5 kORdeg 90 O

VDD25

Vb,BB1(Mm1-Mm4)

Vb,BB2(Mf3-Mf4)

lb

VDD25

M5b M6b

M3b M4b

M1b M2b

R1b R2b

VDD12 VDD12

Fig. 5.21 Bias circuit of the

current-reuse mixer-LPF


(Fig. 5.24), the�3-dBcutoff frequency shows ameanof12.9MHzwith a reasonablesof 0.636MHz. The passband gain variation is from 8.6 to 12.2 dB. A stable 60-dB per

decade stopband attenuation is achieved at the output. Other simulated performances

metrics are summarized in Table 5.3.

5.5 Multi-phase LOG

5.5.1 Brief Overview

Multiphase LOGs have been extensively studied in wireless/wireline applications.

A solution based on an inverter-based ring-VCO [15] is compact and has wide-

range tunability, but the phase noise is still high for most high-tier wireless systems.

-1

VDD25

Vbias

HBiq(s)

RBB In,RBB2

In,M f32

In,Mf12

Vn,Mm12

Vn,Rs/22

vo3p,BB

(gmf) Mf3

(gmf) Mf1

Cf2

Cf1

Mm1 (gm,Mm1)

Rs/2

Fig. 5.22 Noise model of the current-reuse mixer-LPF


Lowering the phase noise promotes the use of coupled LC-VCOs [16]. The overhead

is the excessive number of inductors which will occupy a considerable amount of

chip area. Delay-locked loop (DLL) offers another way to realize a multiphase LOG

[17]. Regrettably, since it is based on delay units, the phase-noise performance is

heavily dependent on the number of output phases required. Currently, the most

common solution is LC-VCO plus frequency dividers [7]. For instance, a quadri-

phase LO can be generated via a divide-by-2 circuit. This division implies that the

associated PLL and VCO have to operate at a frequency that will be double of the

output. Thus, the design complexity dramatically rises with the number of phases

required, without mentioning the power, phase noise and phase error overheads.

Moreover, the PLL and VCO will be more sensitive to parasitic capacitances,

implying narrower locking and tuning ranges, respectively.

5.5.2 Open Loop Multi-phase LO Generators(Conventional and Proposed)

Recently, an open-loop quadri-phase clock generator for wireline applications was

proposed to surmount these constraints [18]. Unlike the active polyphase filter

entailing both inverters and capacitors [19], each phase corrector involves only

inverters in a ring oscillator configuration with interpolation for multi-phase

-120

-100

-80

-60

-40

-20

0

20

0.1 1 10 100 1000

Frequency (MHz)

Mix

er-F

ilter

BB

Gai

n R

espo

nse

(dB

) StopbandRejection

PassbandGain

60dB/dec

vo1p,BB

vo3p,BB

vo2p,BB

Fig. 5.23 Simulated mixer-LPF’s gain-filtering characteristics

5.5 Multi-phase LOG 103

Fig. 5.24 Monte-Carlo Simulation of mixer-LPF baseband AC responses

Table 5.3 Performance summary of the current-reuse mixer-LPF (simulation)

Parameters Value

�3 dB cutoff (MHz) (Monte Carlo simulation) Mean 12.9

s 0.636

LPF stopband profile (dB) 60/decade

Conversion gain (dB) 10.5

DSB NF (dB) 15.2

Out-of-channel IIP3 (dBm) +15.7a

Input capacitance (fF) 43

Power (mW) 9.8aTwo tones at [fLO + 20 MHz, fLO + 31 MHz]

IMD3 @ 9 MHz, IMD2 @ 11 MHz after mixing


outputs, resulting in a much more compact area and with a wider tuning range. The

phase precision can be optimized by increasing the number of phase correctors in

cascade. A master LO direct injection-locks the chain and defines the steady-state

frequency. The tuning range depends on the reference LO and the lock range of the

phase correctors; both can be optimized via proper sizing of the associated

inverters. The prime advantages of this method are its simplicity (i.e., open loop

and inverter only), wide bandwidth and the lack of power-hungry buffers. More-

over, the frequency of the driving source can be the same frequency as the multi-

phase outputs. The achieved frequency range in [18] for a quadri-phase output is

0.37–2.5 GHz, but the phase error is limited to 5�.Here, the proposed 4-/8-phase LOG extends such a concept, appropriately

narrowing the coverage of the LOG by using three chains of 4-/8-phase correctors

individually optimized for a specific band. As such, and through circuit-level

optimization, the phase error is controlled within 1� (simulation), being more

suitable for wireless applications.

The block schematic of the proposed 4-/8-phase LOG is depicted in Fig. 5.25. It is

based on 2 chains of 8-phase corrector (8PC) and 1 chain of 4-phase corrector (4PC);

each is dedicated to a specific mobile-TV band for minimum phase error. Selectors

with logic arrangement feature assign the correct LO phase to eachmixer in different

modes. The injection signal LOin might cover the desired bands by using a 1.27-to-

1.92-GHz PLL + VCO [20] (not integrated in this work) with selectable output

division ratios (1, 2, 3, 6 and 8). This LO plan corresponds to 3.8� relaxation of the

PLL + VCO’s operation frequency when comparing it with [9]. However, here, the

required division ratios can be of any number as they are unrelated to the phases of

LOout. In the L band, the PLL + VCO works at the same RF frequency.

5.5.3 Circuit Implementation and Simulation Results

The circuit implementations of the 4- and 8-phase paths are shown in Fig. 5.26a and b,

respectively. LOin drives a chain of all-digital 4PC/8PC to progressively improve the

phase precision of the 4-/8-phase LOout. A high-level algorithm has been developed

LO Buffers8-Phase LOout @fLO

4-Phase LOout @fLO

VHF-III BandUHF Band

L Band

8PC

LOin

8

8

4@fLO

Se l

ecto

r

Mode and PhaseArrangement

8PC8PC8PC8PC8PC

8PC8PC8PC8PC8PC8PC

4PC4PC4PC4PCS

elec

tor

Mode 4PC: 4-Phase Corrector8PC: 8-Phase Corrector

(From VCO)

Fig. 5.25 A direct Injection-locked 4-/8-phase LOG


in MATLAB to optimize the device size, number of stages and frequency range

using a linearizedmodel [21]. At the transistor level, each 4PC/8PC comprises 16/32

inverters classified into two types and three sets as depicted in Fig. 5.27a and b.

L-type features a larger device size than S-type for optimizing the phase

correctability of each 8PC. Set A is to interpolate the intermediate phases. Set B is

to suppress the self-oscillation frequency and thereby enlarging the locking window.

Set C is for injection lock and direct stage-to-stage cascading. The entire LOG is

implemented with thin-oxide MOSFETs operating at a 1.2-V supply.

4PC#1

in3in2in1in0

out3out2out1out0

4PC#4

in3in2in1in0

out3out2out1out0

Phase (degree)

0

90

180

270

Phase (degree)

0

90

180

270

Phase (degree)

0

90

180

270. . .

Phase (degree)

0

90

180

270

. . .

LO180

LOinLOout

LOin LOout

LO0

LO180

LO0

LO45LO90LO135LO180LO225LO270LO315

LO0

LO90LO180LO270

LO0

8PC#1

in3in2in1in0

out3out2out1out0

in7in6in5in4

out7out6out5out4

8PC#6

in3in2in1in0

out3out2out1out0

in7in6in5in4

out7out6out5out4

Phase (degree)

0

90

180

270

45

135225

315

Phase (degree)

0

90

180

270

45

135225

315

Phase (degree)

0

90

180

270

45

135225

315

. . .

Phase (degree)

0

90

180

270

45

135225

315

. . .

a

b

Fig. 5.26 Block schematic of the LOG path (a) 4-phase. (b) 8-phase


The phase precision of the LOG is mainly limited by the routing in the layout,

where the transistor intrinsic RC value is sensitive to the parasitics. The LOG was

laid out and extracted to tune out this effect in several iterations. In the post layout

simulation (PLS), the phase error for 8-phase output is optimized to be <1� for theVHF-III and UHF bands. This precision fairly meets our target of HR ratio of

A

B

B

A

BAB

A

A

A

A

A

in3

out3C

in0

out0C

in2

out2C

in1

out1C

in5

in4

out5

out4

in2

out2

in7

out7

in0

in1

out0

out1

in3out3

in6

out6

A

A

A

A

A

A

A

A

A

A

A

AA

A

A

A

BB

B

B

B

B

B

B

C

C

CC

C

C C

C

L-type S-type

a

b

Fig. 5.27 Detailed schematic of the (a) 4PC. (b) 8PC


33 dB, even under a possible gain mismatch up to 5%. For the 4-phase output, the

phase error is controlled to be less than 1.5� for the L band, which corresponds to an

image rejection ratio of around 38 dB for a possible gain mismatch up to 2.5%.

Similar to ring oscillators, the robustness of the phase corrector can be improved

by adopting a supply regulator and a Bandgap reference to cope with the voltage and

temperature variations, respectively [22, 23]. Simulations show that the phase noise

of the multi-phased LOwill not be degraded bymore than 1 dB (at 1-MHz frequency

offset) if the random noise superimposed on the supply is less than 80 mV.

5.6 Measurement Results

Prototypes of the RFE were fabricated in 65-nm CMOS. Deep n-well was employed

for essential bulk-source connection of certain nMOS devices (e.g., the ones in

cascode). The chip micrograph is shown in Fig. 5.28. The active die area is

0.46 mm2. A production socket was employed to facilitate tests of multiple samples

under the same fixture and environment (Fig. 5.29). Particular attention has been

paid to the layouts of the LOG and 8PC to avoid parasitic mismatches that can lead

to systematic phase error in the LOG.

Fig. 5.28 Chip micrograph of the implemented RFE


5.6.1 The RFE

The RFE measures 35 � 1-dB maximum voltage gain, 4 � 0.2-dB NF, and

consumes 43-to-55 mW of power over the desired bands (Fig. 5.30). The BB gain

responses show 60-dB/dec rejection and a constant cutoff of around 12 MHz

against gain (Fig. 5.31). The cutoff was not made tunable in this prototype. The

key distortion specification is justified by the out-of-channel linearity [1]; two tones

are applied at [fLO + 20 MHz, fLO + 31 MHz] with a power level sweeping from

�40 to �20 dBm. The measured IIP3 is around �3.4/+11 dBm at the highest/

lowest gain by tuning the ATT gain steps (Fig. 5.32). The IIP2 yields less variation

(32–35 dBm) against gain change. The concerned HR ratios (HRRs) are HRR3

¼ 35 dB and HRR5 ¼ 39 dB, aligning with that achieved in a typical HR mixer [8].

Note that to increase the data accuracy; the IIP2/HRR3/HRR5 is averaged from 12

samples with s of 3.9/1.8/2.4 dB. The worst S11 is close to –10 dB (Fig. 5.33),

which is degraded when comparing it with the simulations. The bondwire, test

socket and PCB parasitics should account for the discrepancy. The S11 curves are

consistent to the designed values of 34.8 O at high gain mode (without ATT) and

55 O at low gain modes (with ATT).

Fig. 5.29 PCB of the implemented RFE

5.6 Measurement Results 109

0

10

20

30

40

50

60

0.1 1

NF

(d

B),

Gai

n (

dB

), P

ow

er (

mW

)

RF Frequency, fRF (GHz)

NF

Power

LUHFVHF III

@ Highest Gain

Gain

Fig. 5.30 Measured RFE’s power, gain and NF

60dB/dec

-10

0

10

20

30

40

0.1 1 10 100

BB Frequency (MHz)

BB

Gai

n R

esp

on

se (

dB

)

UHF band8-Phase LO @ 665MHz

~18dB Gain Range

Fig. 5.31 Measured RFE’s BB gain responses against gain control

24

28

32

36

40

44

48

0.1 1RF Frequency, fRF (GHz)

IIP3

(dB

m)

IIP2(

dB

m)

-8

-4

0

4

8

16

12

IIP2 @ Highest Gain

IIP3 @ Lowest Gain

IIP2 @ Lowest Gain

IIP3 @ Highest Gain

LUHFVHF III

Fig. 5.32 Measured RFE’s IIP2 and IIP3 at the highest and lowest gain levels

-35

-30

-25

-20

-15

-10

-5

0

0 0.5 1 1.5 2

S11

(d

B)

RF Frequency, fRF (GHz)

S11 versus the 4gain steps

1700MHz170MHz

Rin’=34.8W

Rin’=55W

Fig. 5.33 Measured RFE’s S11 against gain control

Based on transient measurements, we can justify that the BB differential outputs

(Fig. 5.34a) and I/Q outputs (Fig. 5.34b) are of high-precision balancing, less than

0.5 dB gain and 1.2� phase errors in downconverting a single tone from 205 to 1MHz.

Fig. 5.34 Measured RFE’s (a) differential and (b) I/Q outputs under single-tone downconversion

from 205 to 1 MHz


5.6.2 The LOG

The performance of the LOG in each band was characterized using a signal

generator as LOin like it is shown in Fig. 5.35. The added phase noises (Fig. 5.36a–c)

are well below to that achieved in [1] which uses a practical PLL + VCO as LOin.

Thus, the phase noise induced by the LOG should be tolerable when the PLL +

VCO is present.

The injection-locking characteristic of the LOG is of interest. When LOin is

deactivated (Fig. 5.37a), LOout is free-running at its natural oscillation frequency of

around 240 MHz and noticeable spurious tones appear throughout the spectrum.

With LOin activated with a frequency of 205 MHz, LOout tracks LOin at the same

frequency and the dynamic range is >60 dB (Fig. 5.37b). On the other hand, the

second to sixth harmonics will be suppressed by the differential I/Q mixer with HR.

These results demonstrate that a high-purity multi-phase LO can be achieved

without frequency division.

5.6.3 Performance Comparison

Benchmarking with the state-of-the-art wideband RFEs that attain 4-dB NF [9, 24]

in Table 5.4, this work succeeds in extending the operating BW and BB selectivity

with comparable power, while reducing the external parts, chip area and fLO that can

ease the design of the PLL and VCO. We note that the on-chip HRR can be further

enhanced by incorporating the two-stage HR technique [9]. Though the pre-gain and

pre-filtering technique [24] can also enhance the HRR and lower the power, it

involves hard tradeoffs in impedance match, IIP3 and consistency of in-band

performances.

SignalGenerator

LOout(1phase)

SpectrumAnalyzer

DUT

8-Phase LOG

Phase-Noise Measurement

655MHz0.35mm

0.18

mm

LOin

Fig. 5.35 Test setup for phase noise measurement


100 1000

-130

-120

-110

-100

Offset Frequency (kHz)

-90

-150

-140Pha

se N

oise

(dB

c/H

z)P

hase

Noi

se (

dBc/

Hz)

Pha

se N

oise

(dB

c/H

z)10

10dB/Dec

PLL-locked 4-Phase Output [5.1]

LOin

@205 MHz

100 1000Offset Frequency (kHz)

10

-130

-120

-110

-100

-90

-150

-140

100 1000Offset Frequency (kHz)

10

-130

-120

-110

-100

-90

-150

-140

LOout

LOout

LOout



10dB/Dec

10dB/Dec

LOin

LOin

@655 MHz

@1.55 GHz

a

b

c

Fig. 5.36 Measured phase

noise of the LOG in each

band comparing with

the data given in [1].

(a) 8-phase at 205 MHz.

(b) 8-phase at 655 MHz

and (c) 4-phase at 1.55 GHz


5.6.4 Architecture Comparison

Cascode of building blocks [25, 26] is an effective solution for current reuse and

maximizing the BW at RF, as the node between the low-noise amplifier (LNA)

and mixer can be of low impedance (Z) as shown in Fig. 5.38. The main

shortcomings are the limited reverse isolation (LO $ RF $ BB leakages) and

DR, due to insufficient voltage headroom in nanoscale CMOS technologies.

-80

01st

2nd 3rd

1st

2nd3rd

100 80070/

0

-90

(Frequency MHz)

(dB

m)

(dB

m)

100 80070/

0

70 MHz/Start 100 MHz Stop 800 MHz

70 MHz/Start 100 MHz Stop 800 MHz

-10

-20

-30

-40

-50

0

-90

(Frequency MHz)

-60

-70

-10

-90

-90

-20

-30

-40

-50

-60

-70

a

b

Fig. 5.37 Measured injection-locking characteristic of the LOG: (a) free-running at ~240 MHz

(b) Injection-locked at the desired 205 MHz


Table 5.4 Measurement summary and benchmark with the state-of-the-art wideband RFEs

Parameters This work ISSCC 2009 [9] JSSC 2010 [24]

Operation frequency

fRF (GHz)

0.17–1.7a 0.4–0.9 0.3–0.8

Required master LO

frequency fLO(GHz)

fLO ¼ fRF (4 and

8 phases)

fLO ¼ 8 fRF (8 phases) fLO ¼ 4 fRF (8 phases)

Maximum gain (dB) 35 34 22–28b

RF gain control (dB) 17–35 No No

External components 1 inductor 2 inductors and

1 balun

2 inductors

Area (mm2) 0.46 1 0.5

BB filter order Third-order LPF

(1 biquad

+ 1 real)

Second-order LPF

(2 real poles)

First-order IIR LPF

(minor channel

selectivity)

Power (mW) @

fRF (GHz)

55 @ 1.7c 60 @ 0.9 18 @ 0.8

Input impedance

matching

Matched Matched Unmatched

DSB NF (dB) 4 [Spec: 4]d 4 0.8–4.3b

IIP3 (dBm) �3.4 [Spec: -5]d 3.5 �14 to �9b

IIP2 (dBm) 32 [Spec: 27]d

(balun LNA)

46 (differential LNA) 38–49c (balun LNA)

HRR3 (dB) 35 60 60

HRR5 (dB) 39 64 60

Supply voltage (V) 1.2 and 2.5 1.2 1.2

Technology 65 nm CMOS 65 nm CMOS 65 nm CMOSaVHF III, UHF and L bandsbIn-band variationcBalun-LNA (11.6 mW), I/Q mixer-LPFs (19.6 mW), LOG + LO buffers (24 mW at 1.7 GHz,

12 mW @ 170 MHz)dFrom [1]

Mixer

Balun-LNA

Load

Mixer

LNA

VCO+Load

Low Z @ RF Low Z @ RF

VDDVDD

VBBVBB

a b

Fig. 5.38 Cascode of building blocks: (a) LMV cell [25] and (b) Blixer [26]


Recently, a mixed-VDD design approach (Fig. 5.39) has been proposed to

alleviate these drawbacks. Both VDD25 (I/O VDD) and VDD12 (core VDD), thick and

thin-oxide devices are employed. The VDD25 enlarges the voltage headroom while

allowing more BW-/linearity-demanding nodes to be operated in the current

domain. Specifically, the balun low-noise amplifier (LNA) employs a differential

current balancer (DCB) to improve the output gain-phase balancing of the single-

to-differential stage (S2D), yielding better IIP2 and reverse isolation. The key

expense is there will be a high impedance node at RF (VRF) that may limit the RF

BW (depends on the required gain). For the analog baseband, the lowpass filter

(LPF) can be cascoded with the mixer for current-mode filtering, leading to lower

noise and better out-of-channel linearity (i.e., filtering happens before I-V conver-

sion). For the local oscillator generator (LOG), since it is operated as digital

circuits, structuring it with only thin-oxide devices and VDD12 (core VDD) are

sufficed to fully benefit the speed, power and area advantages of advanced

technologies.

5.7 Summary

A 65-nm CMOS RFE composed by a wideband balun-LNA with VGC, dual

current-reuse mixer-LPFs and a direct injection-locked 4-/8-phase LOG has been

described. Comparing with the existing wideband RFEs, the external parts and

repeated RF circuitry are reduced and the required master LO frequency is relaxed.

The RFE exploits a dual 1.2/2.5-V supply, allowing more functions to be

implemented in the current domain. The output balancing of the balun-LNA is

DCB

S2D

Load

LPF

Mixer

Load

Dual-VDDThin-Oxide

MOS Balun-LNA

I/O-VDDThick/Thin-OxideMOS Mixer-LPF

Core-VDDThin-OxideMOS LOG

LOG

VDD25

VDD12

VDD12

VBBVRF

VDD25

Fig. 5.39 Device and voltage plan of this work

5.7 Summary 117

enhanced by a capacitively cross-coupled cascode stage, and baseband selectivity is

efficiently implemented via a current-domain Biquad merged with the mixer.

Device reliability is ensured via a hybrid use of thin- and thick-oxide MOSFETs

and voltage-conscious biasing. The fabricated prototypes meet the key

specifications of mobile TV with a small die size of 0.46 mm2.

References

1. Vassilios, K. Vavelidis and N. Haralabidis et al, “A 65-nm CMOS Multistandard, Multiband

TV Tuner for Mobile and Multi-Media Applications,” IEEE J. Solid-State Circuits, vol. 43,pp. 1522–1533, Jul. 2008.

2. M. Jeong, B. Kim and Y. Cho et al, “A 65 nm CMOS Low-Power Small-Size Multistandard,

Multiband Mobile Broadcasting Receiver SoC,” ISSCC Dig. Tech. Papers, pp. 460–461, Feb.2010.

3. P.-I. Mak and R. P. Martins, “A 0.46 mm2 4-dB NF Unified Receiver Front-End for Full-Band

Mobile TV in 65 nm CMOS,” ISSCC Dig. Tech. Papers, pp.172–173, Feb. 2011.4. S. Blaakmeer, E. Klumperink, D. Leenaerts and B. Nauta, “Wideband Balun-LNA with

Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling,” IEEE J. Solid-State Circuits, vol. 43, pp. 1341–1350, Jun. 2008.

5. D. Mastantuono and D. Manstretta, “A Low-Noise Active Balun with IM2 Cancellation for

Multiband Portable DVB-H Receivers,” ISSCC Dig. Tech. Papers, pp. 216–217, Feb. 2009.6. Datasheet of TDK Low Pass Filters for DVB-H/ISDB-T DEA Series DEA200710LT-1238A1.

7. V. Giannini, P. Nuzzo, C. Soens et al, “A 2-mm2 0.1–5 GHz Software-Defined Radio Receiver

in 45-nm Digital CMOS,” IEEE J. Solid-State Circuits, vol. 44, pp. 3486–3498, Dec. 2009.8. J. Weldon, J. Rudell, L. Lin et al, “A 1.75-GHz Highly Integrated Narrowband CMOS

Transmitter with Harmonic-Rejection Mixers,” ISSCC Dig. Tech. Papers, pp. 160–161, Feb.2001.

9. Z. Ru, E. Klumperink, G. Wienk, and B. Nauta, “A Software-Defined Radio Receiver

Architecture Robust to Out-of-Band Interference,” ISSCC Dig. Tech. Papers, pp. 230–231,Feb. 2009.

10. B. Razavi, “Cognitive Radio Design Challenges and Techniques,” IEEE J. of Solid-StateCircuits, vol. 45, pp. 1542–1553, Aug. 2010.


“A 40 nm CMOS Highly Linear 0.4-to-6 GHz Receiver Resilient to 0dBm Out-of-Band

Blockers,” ISSCC Dig. Tech. Papers, pp. 62–63, Feb. 2011.12. W. Zhuo, X. Li, S. Shekhar, S.H.K. Embabi, J. Pineda de Gyvez, D.J. Allstot and E. Sanchez-

Sinencio, “A Capacitor Cross-Coupled Common-Gate Low Noise Amplifier,” IEEE Trans. onCircuits and Systems II: Express Briefs, vol. 52, pp. 875–879, Dec. 2005.

13. E. Klumperink, S. Louwsma, G. Wienk and B. Nauta, “A CMOS Switched Transconductor

Mixer,” IEEE J. Solid-State Circuits, Vol. 39, pp. 1231–1240, Aug. 2004.14. A. Pirola, A. Liscidini and R. Castello, “Current-Mode, WCDMA Channel Filter with In-Band

Noise Shaping,” IEEE J. Solid-State Circuits, vol.45, no.9, pp.1770–1780, Sept. 2010.15. D. Y. Jeong, S. H. Chai, W. C. Song and G. H. Cho, “CMOS Current-Controlled Oscillators

Using Multiple-Feedback-Loop Ring Architectures,” ISSCC Dig. Tech. Papers, pp. 386–387,Feb. 1997.

16. L. C. Cho, C. Lee, and S. I. Liu, “A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13-

mm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1261–1270, Jun.2007.


17. X. Gao, E. A. M. Klumperink and B. Nauta, “Advantages of Shift Registers Over DLLs for

Flexible Low Jitter Multiphase Clock Generation,” IEEE Trans. on CAS–II: Express Briefs,vol. 55, no. 2, pp. 244–248, Mar. 2009.

18. K. H. Kim, P. W. Coteus, D. Dreps et al, “A 2.6 mW 370 MHz-to-2.5 GHz Open-Loop

Quadrature Clock Generator,” ISSCC Dig. Tech. Papers, pp. 458–459, Feb. 2008.19. F. Tillman, H. Sjoland, “A Polyphase Filter Based on CMOS Inverters,” NORCHIP Conf.,

pp. 12–15, Nov. 2005.

20. Lei Lu, Zhichao Gong, Youchun Liao, et al, “A 975-to-1960 MHz Fast-Locking Fractional-N

Synthesizer with Adaptive Bandwidth Control and 4/4.5 Prescaler for Digital TV Tuners”

ISSCC Dig. Tech. Papers, pp. 396–397, Feb. 2009.21. K.-F. Un, P.-I. Mak and R. P. Martins, “Analysis and Design of Open-Loop Multi-Phase

Local-Oscillator Generator for Wireless Applications,” IEEE Trans. on CAS-I: RegularPapers, vol. 57, no. 5, pp.970–981, May 2010.

22. T. Wu, K. Mayaram, and U. Moon, “An On-Chip Calibration Technique for Reducing Supply

Voltage Sensitivity in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4,

pp. 775–783, Apr. 2007.

23. Y.-T. Huang, C. M. Yang, S. C. Huang, H. L. Pan, T. C. Hung, “A 1.2 V 67 mW 4 mm2Mobile

ISDB-T Tuner in 0.13 mm CMOS,” ISSCC Dig. Tech. Papers, pp. 124–125, Feb. 2009.24. Z. Ru, E. Klumperink, C. Saavedra and B. Nauta, “A 300–800 MHz Tunable Filter and

Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF Sampling Receiver,”

IEEE J. Solid-State Circuits, vol. 45, pp. 967–978, May 2010.

25. A. Liscidini et al., “Single-stage low-power quadrature RF receiver front-end: The LMV cell,”

IEEE J. Solid-State Circuits (JSSC), vol. 41, no. 12, pp. 2832–2841, Dec. 2006.26. S.C. Blaakmeer, E. Klumperink, D. Leenaerts, B. Nauta, “The Blixer, a Wideband Balun-

LNA-I/Q-Mixer Topology,” IEEE J. of Solid-State Circuits (JSSC), vol.43, no.12,

pp.2706–2715, Dec. 2008.

References 119

Chapter 6

Conclusions

6.1 Concluding Remarks

Technology downscaling has stressed the use of sub-1V VDD to maintain device

reliability. In this book, high-/mixed-voltage RF and analog CMOS circuits have

been presented as the technology comes of age, being apposite for realizing high-performance wireless systems in ultra-scaled CMOS technologies. Dual voltage

supplies have become very common since the deployment of nm-length CMOS

processes such as the 90-nm node. We also believe that multiple supplies offering a

VDD-on-demand approach will be more efficient in overall system power savings.

This book explored a number of analog and RF circuit techniques. From block level

to sub-system level, the techniques led to enhanced performances, lower power and

cost. When design-for-reliability (i.e., prevent overstress on any device) is included

in the design flow, an elevated VDD outpacing the technology roadmap directly

opens up more flexibility in defining circuit topologies while preserving sufficient

voltage headroom for signal swing. Table 6.1 summarizes the design considerations

of analog and RF circuits with different degrees of freedom, namely area, current

and the topic of this research, supply.Three high-/mixed-voltage design examples that are application-specified to

mobile TV have been presented as proofs of concept. The first design is a 90-nm

CMOS full-band mobile-TV low-noise amplifier (LNA) with mixed-voltage ESD

protection. The second is a 90-nm CMOS high-voltage-enabled mobile-TV RF

front-end with TV-GSM interoperability. The third is a 65-nm CMOS mixed-

voltage unified receiver front-end for full-band mobile TV. Together with a number

of system- and circuit-level techniques and optimization, the performances of the

describedworks have shown significant advances with respect to the state-of-the-art.

In conclusions, differing from digital circuits, analog and RF circuits will benefit

much more from technology scaling if the VDD (high, low or adaptive) is wisely

chosen for each block in a SoC environment. The transistor plan for each block can

be further customized among the available types such as thin-oxide, thick-oxide,



121

high VT, standard VT and low VT. Mixed-voltage mixed-transistor design

methodologies are becoming a new art of circuit design in ultra-scaled CMOS

technologies.

6.2 Recommendations for Future Research

A mixed-VDD wideband transceiver architecture potentially suitable for software-

defined radios (SDRs) and cognitive radios (CRs) is depicted in Fig. 6.1. There are

numerous issues meriting further exploration in future research:

• Inductorless design is already an obvious approach for area savings in RF

receivers. When a high-VDD is adopted, a wideband low-noise transconductance

amplifier (LNTA) can deliver the desired gain with high DR when driving a

current-mode passive mixer. The first BB filter (e.g., OpAmp-based circuits)

worked as an I-V converter can directly benefit from the gain and DR offered by

a high-VDD. With the advance of data converters (both ADC and DAC), a

standard-VDD already can lead to excellent power efficiency for the requirements

of most wireless applications (i.e., speed of 20–60 MS/s and resolution of

8–11 bits). A mixed-VDD, however, will be relevant when more resolution is

entailed. For instance, when speed is not that demanding, the nonlinearity of the

input sample-and-hold circuit can be reduced effectively by using thick-oxide

MOS and a high-VDD clock (CLK). Moreover, the involved OpAmps in the ADC

and DAC can also benefit from a high-VDD to achieve a higher DC gain and a

wider signal swing.

• A high-VDD PA has already been a common practice in wireless transmitters to

boost output power and enhance power efficiency, especially for multi-band

communications where LC resonators should be avoided. For the mixer and

baseband LPF, passive implementation is becoming more relevant to minimize

nonlinearity and output noise floor; both are critical parameters for wideband

SDRs and CRs where external SAW filters may not be possible.

Table 6.1 Design strategies of analog and RF circuits in nanoscale CMOS

RF Analog

Increase area ✓ Gain-bandwidth (e.g., via inductors) ✓ Matching (DC-Offset)

✓ kT/C noise

Increase current ✓ Unity-gain frequency (e.g., higher device fT) ✓ Slew rate

✓ Bandwidth

Increase supplya ✓ Gain (e.g., allows a larger RL load) ✓ Gain precision

✓ Bandwidth (e.g., cascode of blocks to avoidhigh impedance nodes)

✓ PSRR (e.g., via LDO)

✓ Dynamic range

✓ Dynamic range ✓ Buffering and level

shifting in I/Os✓ Power efficiency (e.g., in PA)aDeviceoverdrive voltagesmustbewithin the technologyguidelines in both transient and steady states

122 6 Conclusions

• A low-power, area-efficient, power-management unit with multiple voltage

outputs based on single-inductor DC-DC converters and/or low-dropout

regulators (LDOs) are worth to explore in the nanoscale CMOS such that the

benefits of mixed-voltage design will become more obvious at the system level.

In particular, inductor-less and capacitor-less solutions will be highly beneficial

in silicon area savings, which is getting more and more expensive in ultra-scale

process nodes. High power supply rejection ratio (PSRR) over a wide bandwidth

will be a very challenging design goal for power-management circuits.

• The local oscillator (LO)/CLK generator can be based on a high-VDD VCO

which uses LDOs to enhance PSRR. Maximizing the VCO tuning range can be

resorted from thick- oxide varactor or MOS capacitor; both can withstand a

wider tuning voltage. For the involved frequency dividers that operate as digital

circuits, thin-oxide MOS and core-VDD are adequate.

• Last but not least, a time-adaptive VDD for the different digital blocks should be

an important direction for global power reduction (e.g., a very low-VDD in

standby mode to minimize leakage power).

High-VDD

High-VDDHigh-VDD

LNTA

ADC

Mixed-VDD

Mixed-VDD

Mixed-VDD

DAC

Mixer

PA

Mixer

LPF

LPFI I V

LO /CLK Generator

VVV

Power Mgr.Battery

... DifferentVDD’s

DSP

Adaptive-VDD

Device Oxide Thickness: Thick and ThinDevice VT: High, Standard, LowDC/DC

LDO

Passive

Passive Passive

Fig. 6.1 A prospective mixed-VDD wideband transceiver architecture for SDRs and CRs

6.2 Recommendations for Future Research 123

Appendix: Open-Loop MultiphaseLO Generators

A.1 Introduction

Many different types of multi-phase LO/clock generators have been proposed for

wireless and wireline applications. A ring voltage-controlled oscillator (VCO)

using inverters (Fig. A.1a) is a compact solution to realize a multi-phase LO with

a large frequency range [1, 2]. However, its phase noise performance is normally

unacceptable for high-tier wireless systems. Although the phase noise can be

substantially reduced by replacing all inverters with LC VCOs (Fig. A.1b) the

associated inductors occupy a significant part of chip area [3, 4]. Delay-locked

loop (DLL) using numerous delay units can also be a multi-phase clock generator

(Fig. A.1c) [5, 6]. The key drawback is that the phase-noise performance is heavily

dependent on the number of output phases required.

Alternatively, a multi-phase LO signal can be generated in an open-loop way by

using a low-noise LC VCO followed by a frequency divider (Fig. A.1d). Elementa-

rily, a quadri-phase LO can be generated via a div-by-2 circuit. Such a division factor

implies that the associated phase-locked loop (PLL) and VCO have to operate at a

doubled frequency. The design complexity, however, rises dramatically with the

number of phases required. For instance, to generate an octave-phase LO a div-by-4

circuit is necessary while the PLL and VCO have to operate at 4� of the output

frequency. A higher operating frequency unavoidably calls for more power to

lower the phase noise and phase error. Moreover, the PLL and VCO will be more

sensitive to parasitic capacitances, implying narrower locking and tuning ranges,

respectively. To surmount these constraints the frequency divider can be replaced

by a passive RC-CR polyphase filter (Fig. A.1e) [7, 8], but the performance can be

strongly affected by the temperature and process variations, while power-hungry

buffers are required for proper interface. Recently an open-loop quadri-phase clock

generator was proposed for wireline applications [9, 10]. Multiple phase correctors

are cascaded in an open-loop way to improve the phase precision (Fig. A.1f).


DOI 10.1007/978-1-4419-9539-1, # Springer Science+Business Media New York 2012

125

The prime advantages of this method are its simplicity (i.e., open loop and inverter

only), no power-hungry buffer, and the number of output phases is independent of

the operation frequency of the circuit itself and its driving source. The achieved

frequency range in [9] is 0.37–2.5 GHz and the phase precision is �5� for a quadri-phase output.

In this content, we extend the concept of such open-loop architecture for wireless

applications with different requirements on the phase precision and the number of

output phases [11]. The targeted phase error is �1� and both quadri- and octave-

phase LO generators will be designed and analyzed.

...PLL

Inverter

...

PLL

LCVCO

LCVCO

LCVCO

LCVCO

LCVCO

LCVCO

LCVCO

LCVCO

DelayUnit 1

DelayUnit 2

DelayUnit N

Multi-Phase LO/Clock

PLL

Div-by-NPLLMulti-Phase

LO/Clock

Multi-PhaseLO/Clock

Multi-PhaseLO/Clock

PLLRC-CR

PolyphaseFilter

Multi-PhaseLO/Clock

Multi-PhaseLO/Clock

buffersbuffers

PLLPhase

CorrectorN

PhaseCorrector

1

…

……

…

………

…

…

a

b

c

d

e

f

Fig. A.1 Multi-phase LO/clock generation methods: (a) ring with inverters, (b) ring with LCVCOs,

(c) DLL (d) frequency divider, (e) RC-CR polyphase filter and (f) phase correctors in cascade

126 Appendix: Open-Loop Multiphase LO Generators

A.2 Mathematical Model of Open-Loop Multi-phaseLO Generator

A.2.1 Quadri-phase LO Generator

Architecture – The block diagram of a quadri-phase LO generator is depicted in

Fig. A.2. It is structured by putting numerous phase correctors in cascade to

interpolate a multi-phase LO from a two-phase differential input (vclk and vclkp).From left to right the phase correctors improve the phase precision progressively

until reaching the desired accuracy. The schematic of each inverter-based quadri-

phase corrector is shown in Fig. A.3. Every corrector is composed by 16 inverters

(CMOS) classified according to two different device sizes as L-type or S-type.L-type inverters feature a larger geommetrical size than the S-type to optimize the

phase precision in a specific frequency range. The inverters can be divided into

three groups according to their functionality: (1) Set A is for phase correction. With

three inverters in a loop it is able to oscillate and interpolate the intermediate

phases; (2) Set B is for natural-frequency suppression. It leads to a larger operating

frequency range [16]; (3) Set C is for signal injection. It allows multiple phase

correctors to be directly cascaded to improve the output phase precision.

Mathematical Model – In order to determine the optimum conditions in terms of

frequency range and phase precision, the quadri-phase corrector is modeled by a

signal flow graph (SFG) as shown in Fig. A.4. For simplicity, a linear model is

assumed [12, 13]. Each inverter is modeled as a single-pole amplifier with a transfer

function of h( f ) as given by,

hð f Þ ¼ � G

1þ jf

fC

; (A.1)

. . .

Cascade of Repeated Cell

Phase (degree)

090

180270

Open LoopQuadri-Phase

CorrectorN

...

vclk_270

vclk_180

vclk_90

vclk_0pq0(N)

pq1(N)pq2(N)pq3(N)vclkp

vclkvo0vo1vo2vo3

vi0vi1vi2vi3


CorrectorN

vo0vo1vo2vo3

vi0vi1vi2vi3


CorrectorN

vo0vo1vo2vo3

vi0vi1vi2vi3

pq0(N-1)pq1(N-1)pq2(N-1)pq3(N-1)

pq0(2)pq1(2)pq2(2)pq3(2)

pq0(1)pq1(1)pq2(1)pq3(1)

pq0(0)pq1(0)

pq2(0)pq3(0)

Fig. A.2 Block diagram of a quadri-phase LO generator. Phase error is reduced down progressively

from the correctors 1 to N

A.2 Mathematical Model of Open-Loop Multi-phase LO Generator 127

where G is the normalized DC gain and fC is the �3-dB cutoff frequency.

The constants a and b in Fig. A.5 represent the driving capability of L-type and

S-type inverters, respectively.Phasor-domain analysis is applied to obtain the phase correction transformation

of the nth phase corrector as expressed by,

ah

bh

ah

bh

ah bh ahbh

ah

ah

ah

ah

bh

bh

bh

bh

pq2(n-1)

pq2(n)pq1(n)

pq0(n) pq3(n)

pq3(n-1)pq4(n-1)

pq1(n-1)

Fig. A.4 SFG of a quadri-phase corrector

A

B

B

A

BAB

A

A

A

A

A

C

C

C

C

L-type S-type

vo2vo1

vo0 vo3

vi3

vi2vi1

vi0

Fig. A.3 Architecture schematic of an inverter-based quadri-phase corrector


AqpqðnÞ ¼ pqðn�1Þ

Aq ¼

1 �ah �ah �bh

�bh 1 �ah �ah

�ah �bh 1 �ah

�ah �ah �bh 1

26664

37775

pqðnÞ ¼ pq0ðnÞ pq1ðnÞ pq2ðnÞ pq3ðnÞ� �T

8>>>>>>>>><>>>>>>>>>:

; (A.2)

where Aq is the phase transformation matrix and pq(n) is the output phase vector.

Re-arranging (A.2) it yields,

pqðnÞ ¼ A�1q pqðn�1Þ: (A.3)

For N quadri-phase cascaded correctors pq(N) becomes,

pqðNÞ ¼ A�Nq pqð0Þ; (A.4)

where pq(0) is the input phase vector represented by,

pqð0Þ ¼ 1 1 �1 �1½ �Tbh; (A.5)

1.5 2 2.5 3 3.5-40

-30

-20

-10

0

10

20

30

40

n = 1n = 2n = 3n = 4

Reference Line

Normalized Frequency (f/fC)

Arg

(jpq1

(n)/p

q0(n

)) (

Deg

ree)

Fig. A.5 Static phase error of quadri-phase corrector with a/b ¼ 3.4 and G ¼ 10 (linear-model

simulation)


since the input phase can be either 0� or 180�. In the phasor domain only 1 or�1 are

available for the input vector. Figure A.5 shows the steady-state phase error

function defined by (A.6) with different number of stages in cascade,

FeqðnÞ ¼ Argð j pq1ðnÞpq0ðnÞ

Þ: (A.6)

wherea/b is chosen tobe3.4 toprovide anacceptable frequency range andG is selected

as 10 (practical DC gain value of a CMOS inverter in nanometer technologies).

The steady phase error depends on the ratio of the output frequency ( f ) to the cornerfrequency of an inverter (fc), as well as the number (n) of phase correctors in cascade.With n ¼ 4, the phase error is minimized over a wide range of f/fc (between 2.1

and 2.7). Figure A.6 also shows that the steady-state phase error can be minimized

by cascading additional stages of quadri-phase correctors for certain frequency ranges.

Based on the above definitions and following a particular context the transfer

function of the linearized quadri-phase LO generator will be derived next.

According to it, the optimal conditions for minimizing the phase error are obtained

to build-up the device-sizing strategy. From (A.2), we can simply prove that,

pq0ðnÞ ¼ �pq2ðnÞpq1ðnÞ ¼ �pq3ðnÞ

(: (A.7)

Thus, (A.2) and (A.3) can be simplified as,

1þ ah �ða� bÞhða� bÞh 1þ ah

� �pq0ðnÞpq1ðnÞ

� �¼ pq0ðn�1Þ

pq1ðn�1Þ

� �: (A.8)

OpenLoop

OctavePhase

Corrector1

. . .

Cascade of Repeated Cell

Phase (degree)

0

90

180

270

OpenLoop

OctavePhase

Corrector2

OpenLoop

OctavePhase

CorrectorN

vclk_315

vclk_270

vclk_225

vclk_180

vclk_135

vclk_90

vclk_45

vclk_0

vclkp

vclk

45

135

225

315

...

po0(N)vo0vo1vo2vo3vo4vo5vo6vo7

vi0vi1vi2vi3vi4vi5vi6vi7

vo0vo1vo2vo3vo4vo5vo6vo7


vo0vo1vo2vo3vo4vo5vo6vo7


po1(N)po2(N)po3(N)po4(N)po5(N)

po6(N)po7(N)

po0(2)po1(2)po2(2)po3(2)po4(2)po5(2)

po6(2)po7(2)

po0(1)po1(1)po2(1)po3(1)po4(1)po5(1)

po6(1)po7(1)

po0(0)po1(0)po2(0)po3(0)po4(0)po5(0)

po6(0)po7(0)

po0(N-1)po1(N-1)po2(N-1)po3(N-1)po4(N-1)po5(N-1)

po6(N-1)po7(N-1)

Fig. A.6 Block diagram of an octave-phase LO generator


And also for a simplification of the notations, A, B and C are introduced as

follows:

A ¼ 1þ ah

B ¼ ða� bÞh

C ¼ A �B

B A

� �: (A.9)

Similar to (A.4), we can obtain,

pq0ðNÞpq1ðNÞ

� �¼ C�N pq0ð0Þ

pq1ð0Þ

� �¼ C�N 1

1

� �: (A.10)

Since the matrix C can be diagonalized as,

C ¼ 1ffiffiffi2

p j �j1 1

� �� Aþ jB 0

0 A� jB

� �1ffiffiffi2

p �j 1

j 1

� �� ; (A.11)

Substituting it in (A.10) will finally lead to,

pq0ðNÞpq1ðNÞ

� �¼ 2N

ð1þ jÞðAþ jBÞ�N þ ð1� jÞðA� jBÞ�N

ð1� jÞðAþ jBÞ�N þ ð1þ jÞðA� jBÞ�N

� �: (A.12)

Finally, the transfer function of pq1(N) divided by pq0(N) can be obtained as,

pq1ðNÞpq0ðNÞ

¼jþ 1þ ah� jða� bÞh

1þ ahþ jða� bÞh� �N

1þ j1þ ah� jða� bÞh1þ ahþ jða� bÞh

� �N : (A.13)

The criteria for phase error minimization is equivalent to set,

pq1ð1Þpq0ð1Þ

¼ �j; (A.14)

which implies a 90� phase shift. Substituting (A.14) into (A.13) leads to,

1� 2Gaþ Gbþ f

fc¼ 0

1� Gb� f

fc¼ 0

8>><>>: : (A.15)


By solving (A.15) the optimal conditions for phase error minimization can be

obtained as,

a ¼ G�1

f ¼ Gða� bÞfc

: (A.16)

It implies that an ideal 90� phase shift happens at the natural frequency of the

circuit: fn ¼ Gða� bÞfc. Also, a larger a/b ratio can provide a stronger phase

correcting ability.

A.2.2 Octave-Phase LO Generator

Architecture – Octave-phase LO generation can be obtained by further extending

the quadri-phase LO concept and architecture previously outlined. As such, the

block diagram of an octave-phase LO generator can be drawn as illustrated by

Fig. A.6. From left to right an octave-phase LO can be composed by multiple

octave-phase correctors. The number of stages in cascade will directly depend on

the final phase-precision requirement. The architecture schematic of an octave-

phase corrector is shown in Fig. A.7 which is composed by 32 inverters (CMOS).

Similar to the quadri-phase design the inverters are also classified as L-type or

S-type and the three sets (A, B and C) previously mentioned are also maintained.

C

A

B

BB

B

B

B

B

B

A

A

A

A

A

A

A

A

A

A

A A

A

A

A

C

C C

C

C

C Cvo4vo1

vo6

vi1

vi6

vi3

vo3

vi0

vo0 vo5

vi5

vo2

vi2

vo7

vi4

L-type S-type

Fig. A.7 Architecture schematic of an octave-phase corrector


Mathematical Model – The SFG of the octave-phase corrector is presented in

Fig. A.8 where a linear model is also assumed and each inverter is modeled,

similarly, as a single-pole amplifier. Again, phasor-domain analysis is applied to

obtain the phase transformation of the nth octave-phase corrector as given by,

AopoðnÞ ¼ poðn�1Þ

Ao ¼

1 �ah 0 0 �ah 0 0 �bh

�bh 1 �ah 0 0 �ah 0 0

0 �bh 1 �ah 0 0 �ah 0

0 0 �bh 1 �ah 0 0 �ah

�ah 0 0 �bh 1 �ah 0 0

0 �ah 0 0 �bh 1 �ah 0

0 0 �ah 0 0 �bh 1 �ah

�ah 0 0 �ah 0 0 �bh 1

266666666666664

377777777777775

poðnÞ ¼ po0ðnÞ po1ðnÞ ::: po7ðnÞ� �T

8>>>>>>>>>>>>>>>>>>><>>>>>>>>>>>>>>>>>>>:

; (A.17)

bh

bh

bh

bh

bh

bh

bh

bh

bh

bh

bh

bh

bhbh

bh

bh

ah

ah

ah a h

ah

ah

ahah

ah

ah

ah

ah

ah

ah

ah

ah

po4(n-1)

po4(n)po3(n)

po2(n)

po1(n)

po0(n) po7(n)

po6(n)

po5(n)

po3(n-1)

po2(n-1)

po1(n-1)

po0(n-1) po7(n-1)

po6(n-1)

po5(n-1)

Fig. A.8 SFG of an octave-phase corrector


where Ao is the octave-phase transformation matrix and po(n) is the output phase

vector of the nth octave-phase corrector. Re-arranging (A.17) it will yield,

poðnÞ ¼ A�1o poðn�1Þ: (A.18)

For N octave-phase correctors in cascade, po(N) is given by,

poðNÞ ¼ A�No poð0Þ: (A.19)

where po(0) is the input phase vector,

poð0Þ ¼ 1 1 1 1 �1 �1 �1 �1½ �Tbh; (A.20)

since the input phase can be either 0� or 180�. In the phasor domain, only 1 or�1 is

available for the input phase vector. The steady-state phase error function can be

defined by,

FeoðnÞ ¼ Arg ejp4po1ðnÞpo0ðnÞ

� �: (A.21)

As illustrated by Fig. A.9 the steady-state phase error can be minimized by

cascading additional stages of octave-phase correctors for a certain frequency range

from 0.7 to 1.3 (normalized frequency: f/fc). The a/b ratio is set to be 3.5 and G is

10. Although the optimum conditions in terms of frequency range and phase

Arg

(ejπ

/4p o

1(n)

/po0

(n))

(D

egre

e)

Normalized Frequency (f/fC)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8-50

-40

-30

-20

-10

0

10

20

30

40

n = 2n = 3n = 4n = 5n = 6

ReferenceLine

Fig. A.9 Static phase error of octave-phase corrector with a/b ¼ 3.5 and G ¼ 10 (linear-model

simulation)


precision can be derived from the linear model the final phase permutation can only

be determined from transistor-level simulation because not all the transistors can be

operated, simultaneously, in the saturation region.

A.2.3 Design Considerations

Sizing – Both quadri- and octave-phase correctors have a limited operating frequency

range. The channel length of the inverter’s transistors is correlated to the upper

frequency limit (i.e., a smaller channel length allows a higher operating frequency).

When the channel length is fixed the a/b ratio is correlated to the range and the phasecorrecting ability of the phase corrector. A smaller a/b ratio can increase its operatingrange at the expense of a weaker phase-correcting ability. Thus, subject to different

applications, the optimum a/b ratio should be chosen such that the desired frequencyrange can be covered. On the other hand, the optimum number of phase correctors

needed in cascade can be determined according to the required phase precision.

PVT Variations – Similar to the ring oscillator the frequency range covered by the

phase corrector can be sensitive to process, voltage and temperature (PVT)

variations. For fast-fast (FF)/slow-slow (SS) process corner with temperature and

voltage variations, the covered frequency range is shifted up/down significantly, as

shown in Fig. A.10. For a reliable design the channel length of the inverters is

determined at “SS corner + low supply voltage + high temperature” for the highest

operating frequency to be larger than the desired frequency. Then, a suitable a/b at

“FF corner + high supply voltage + low temperature” is chosen for the lowest

operating frequency which is also lower than the desired. Increasing the width of

the transistors can only lead to a better variability control at the expense of power.

The operating principle is not dependent of the transistors’ width.

Again, similar to the ring oscillator, the robustness of the phase corrector can be

improved by adopting a supply regulator and a bandgap reference to cope with

the voltage and temperature variations, respectively [14, 15]. Simulations show that

Frequency

UsableFrequency Range

Frequency RangeCovered by Typical

FF + Supply+ Temperature

Typical

SS + Supply+ Temperature

Fig. A.10 Usable frequency range accounting for PVT variations


the regulator should stabilize the power supply with less than 80-mV fluctuation

such that the phase noise of the multi-phased LO will not be degraded by more than

1-dB at 1-MHz frequency offset. Those schemes are under development and have

not been included in this work.

Design and Verification Flow – The design and verification flow is graphically

summarized in Fig. A.11a and b. For simplicity only the quadri-phase LO generator

is considered. Based on the developed linear model and equations the phase error

Linear Model ofthe Quadri-Phase LO

Generator

Find phaseerror vector

Eq. (A1), (A2),(A4) & ( A5)

Evaluate thephase error

Eq. (A6)

Meets thespecifications?

Yes

To Transistor-LevelDesign

No

Adjusta/b or n

Modeling andParameter Determination

Transistor-Level Design,simulation and layout

Transistor Sizing[according to G, a/b & n obtain from theModeling and Parameter Determination]

TransientSimulation

Cover thedesired frequency

range?

Adjusttransistor’s

channellength

Adjusta/b No

No

Yes

Yes

Layout, Parasitics Extraction& Post-Layout Verification

Yes

DesignComplete

No

If ne

cess

ary

Eq. (A16)

InitialG, a/b & n

Confirm finalphase

permutation

Meet thespecifications ?

Phase precisionin the desired

frequency range?Phase noise?

a b

Fig. A.11 Design and verification flow: (a) modeling and parameter determination and

(b) transistor-level design, simulation and layout


vector can be determined with initial values of G, a/b ratio and n. These values canbe adjusted to minimize the phase error over the desired frequency range with fast

simulation speed. The obtained circuit parameters are then transferred to the

transistor-level design. Since the circuit is dynamic the optimization involves

mostly transient simulations. Except for the particular case of the phase noise

which was checked through periodic noise (pnoise) simulations. Although the

linear model can provide a set of parameters that are close to the optimum values,

transistor-level fine tuning is still necessary to account for PVT variations. Circuit

nonlinearity may also affect the final phase permutation and it must be confirmed at

transistor level. Finally, the optimized circuit can be transferred to the layout design

phase. Post-layout verification with parasitic effects is needed to re-confirm all

performance metrics and it will be repeated until all specifications are met.

References

1. D. Y. Jeong, S. H. Chai, W. C. Song and G. H. Cho, “CMOS Current-Controlled Oscillators

Using Multiple-Feedback-Loop Ring Architectures,” IEEE Int. Solid-State Circ. Conf.(ISSCC) Digest, pp. 386–387, 491, Feb. 1997.

2. J. Y. Chang, C. W. Fan, C. F. Liang, and S. I. Liu, “A Single-PLL UWB Frequency

Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier,”

IEEE Trans. on Circuits and Systems – II: Express Briefs, pp. 107–111, vol. 56, no. 2, Feb.2009.

3. L. C. Cho, C. Lee, and S. I. Liu, “A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in

0.13-mm CMOS Technology,” IEEE J. of Solid-State Circuits (JSSC), pp. 1261–1270, vol.42, no. 6, Jun. 2007.

4. A. Rofougaran, J. Rael, M. Rofougaran and A. Abidi, “A 900 MHz CMOS LC-Oscillator

with Quadrature Outputs,” IEEE Int. Solid-State Circ. Conf. (ISSCC) Digest, pp. 392–393,Feb. 1996.

5. X. Gao, E. A. M. Klumperink and B. Nauta, “Advantages of Shift Registers Over DLLs for

Flexible Low Jitter Multiphase Clock Generation,” IEEE Trans. on Circuits and Systems – II:Express Briefs, pp. 244–248, vol. 55, no. 2, Mar. 2009.

6. J. M. Chou, Y. T. Hsieh and J. T. Wu, “Phase Averaging and Interpolation Using Resistor

Strings or Resistor Rings for Multi-Phase Clock Generation,” IEEE Trans. on Circuits andSystems – I: Regular Papers, vol. 53, no. 5, pp. 984–991, May 2006.

7. M. J. Gingell, “Single-Sideband Modulation Using Asymmetric Polyphase Networks,” Elect.Commun. Vol. 48, pp. 21–25, 1977.

8. F. Behbahani, Y. Kishigami, J. Leete and A. A. Abidi, “CMOS Mixers and Polyphase Filters

for Large Image Rejection,” IEEE J. of Solid-State Circuits (JSSC), pp. 873–887, vol. 36, no.6, June 2001.

9. K. H. Kim, P. W. Coteus, D. Dreps, S. Kim, S. V. Rylov and D. J. Friedman, “A 2.6 mW

370 MHz-to-2.5 GHz Open-Loop Quadrature Clock Generator,” IEEE Int. Solid-State Circ.Conf. (ISSCC) Digest, pp. 458–627, Feb. 2008.

10. K. H Kim, D. M. Dreps, F. D. Ferraiolo, P. W. Coteus, S. Kim, S. V. Rylov, D. J. Friedman,

“A 5.4 mW 0.0035 mm2 0.48psrms-Jitter 0.8-to-5 GHz Non-PLL/DLL All-Digital Phase

Generator/Rotator in 45 nm SOI CMOS,” IEEE Int. Solid-State Circ. Conf. (ISSCC) Digest,pp. 98–99,99a, Feb. 2009.


11. K.-F. Un, P.-I. Mak and R. P. Martins, “Analysis and Design of Open-Loop Multi-Phase

Local-Oscillator Generator for Wireless Applications,” IEEE Trans. on Circuits and Systems –I: Regular Papers, vol. 57, no. 5, pp. 970–981, May 2010.

12. A. Rezayee and K. Martin, “A Three-Stage Coupled Ring Oscillator with Quadrature

Outputs,” in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), pp.484–487, May 2001.

13. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third.Ed.,New York: Wiley, 1993.

14. T. Wu, K. Mayaram, and U. Moon, “ An on-chip calibration technique for reducing supply

voltage sensitivity in ring oscillators,” IEEE J. Solid-State Circuits (JSSC), pp. 775–783,vol. 42, no. 4, Apr. 2007.

15. Y.-T. Huang, C. M. Yang, S. C. Huang, H. L. Pan, T. C. Hung, “A 1.2 V 67 mW 4 mm2Mobile

ISDB-T Tuner in 0.13 mm CMOS,” IEEE Int. Solid-State Circ. Conf. (ISSCC) Digest,pp. 124–125, Feb. 2009.


Biography of Authors

Pui-In Mak (S’00-M’08-SM’11) received the Ph.D. degree from University of

Macau (UM), Macao, China, in 2006. He is currently Associate Professor at UM.

He has been with the UM State-Key Laboratory of Analog and Mixed-Signal VLSI

as Research Assistant (2003–2006), Invited Research Fellow (2006–2008) and

Co-Faculty-in-Charge (2008–Present) coordinating the wireless and biomedical

research lines. He has a short-term work in Chipidea Microelectronics (’03), and

was a Visiting Fellow/Scholar at University of Cambridge, UK (2009), INESC-ID,

Portugal (2009) and University of Pavia, Italy (2010). His current research interests

are on analog, mixed-signal and RF circuits and systems for wireless, biomedical

and physical chemistry, and engineering education.

ProfessorMak authored two books: Analog-Baseband Architectures and Circuitsfor Multistandard and Low-Voltage Wireless Transceivers (Springer 2007), and

High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS(Springer 2012) and 90+ papers in journals and conferences. He holds three US

patents. He co-holds numerous research grants supported by Macau Government,

National Natural Science Foundation of China and UM. He is a frequent presenter at

leading fora such as DAC, ISSCC, ISCAS, VLSI and CICC, and has published

papers in JSSC, TCAS, TMTT and CASM, etc.

139

His service includes: Appointed/Elected Member of IEEE Circuits and Systems

Society (CASS) Board-of-Governors (2007–2011); Associate Editor of IEEE

POTENTIALS (2012–2014); Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS II – EXPRESS BRIEFS (2010–2013); Associate Editor of IEEE TRANSACTIONS ON

CIRCUITS AND SYSTEMS I – REGULAR PAPERS (2010–2011); Associate Editor of IEEE

CIRCUITS AND SYSTEMS SOCIETY NEWSLETTER (2010–Present); Member of CASS Publi-

cation Activities (2009–2011); Member of IEEE CASS CASCOM (2008–Present)

and CASEO (2009–Present) Technical Committees; Organization or Technical

Committee Member of AVLSIWS’04, APCCAS’08, PrimeAsia’09–’11,

ISCAS’10, VLSI-SoC’11, RFIT’11, SENSORS’11, APCCAS’12 and ISCAS’15.

He co-initiated the three special GOLD sessions in ISCAS’09–’11.

His paper awards include: ASICON Student Paper Award’03; MWSCAS Stu-

dent Paper Award’04; IEEJ VLSI Workshop Best Paper Award’04, DAC/ISSCC

Student Paper Award’05 and CASS Outstanding Young Author Award’10. He was

the (co)-recipient of University of Cambridge Visiting Fellowship’09; IEEE MGA

GOLD Achievement Award’09; CASS Chapter-of-the-Year Award’09; UM

Research Award’10; UM Academic Staff Award’11 and the National Scientific

and Technological Progress Award’11.

Professor Mak was decorated with the Honorary Title of Value for scientific

merits by the Macau Government in 2005.

140 Biography of Authors

Rui Paulo da Silva Martins (IEEE Member’88 – Senior Member’99 –

Fellow’08), born in April 30, 1957, received the Bachelor (5-years), the Masters,

and the Ph.D. degrees as well as the Habilitation for Full-Professor in electrical

engineering and computers from the Department of Electrical and Computer

Engineering, Instituto Superior Tecnico (IST), TU of Lisbon, Portugal, in 1980,

1985, 1992 and 2001, respectively. He has been with the Department of Electrical

and Computer Engineering/IST, TU of Lisbon, since October 1980.

Since 1992, he has been on leave from IST, TU of Lisbon, and is also with the

Department of Electrical and Computer Engineering, Faculty of Science and

Technology (FST), University of Macau (UM), Macao, China, where he is a Full-

Professor since 1998. In FST he was the Dean of the Faculty from 1994 to 1997 and

he has been Vice-Rector of the University of Macau since 1997. From September

2008, after the reform of the UMCharter, he was nominated after open international

recruitment as Vice-Rector (Research) until August 31, 2013. Within the scope of

his teaching and research activities he has taught 20 bachelor and master courses

and has supervised 24 theses, Ph.D. (11) and Masters (13). He has published: 16

books, co-authoring (5) and co-editing (11), plus 5 book chapters; 204 refereed

papers, in scientific journals (38) and in conference proceedings (166); as well as

other 70 academic works, in a total of 295 publications. He has co-authored three

US Patents (1 issued in 2009 and 2 in 2011) and has also submitted other 4. He has

created the Analog and Mixed-Signal VLSI Research Laboratory of UM: http://

www.fst.umac.mo/en/lab/ans_vlsi/website/index.html, recently elevated to State

Key Lab of China (the first in Engineering in Macao), being its Founding Director.

Professor Rui Martins is an IEEE Fellow, was the Founding Chairman of IEEE

Macau Section from 2003 to 2005, and of IEEE Macau Joint-Chapter on Circuits

And Systems (CAS)/Communications (COM) from 2005 to 2008 [2009World Chap-ter of the Year of the IEEE Circuits And Systems Society (CASS)]. He was the GeneralChair of the 2008 IEEE Asia-Pacific Conference on Circuits And Systems –

APCCAS’2008, and was elected Vice-President for the Region 10 (Asia, Australia,

the Pacific) of IEEE CASS, for the period of 2009–2012. He is Associate Editor of theIEEE Transactions on Circuits and Systems II: Express Briefs, for the period of

Biography of Authors 141

http://www.fst.umac.mo/en/lab/ans_vlsi/website/index.html

http://www.fst.umac.mo/en/lab/ans_vlsi/website/index.html

2010–2011. He was the recipient of two government decorations: the Medal of

Professional Merit from Macao Government (Portuguese Administration) in 1999,

and the Honorary Title of Value fromMacao SARGovernment (Chinese Administra-

tion) in 2001. In July 2010 was elected, unanimously, as Corresponding Member of

the Portuguese Academy of Sciences, Lisbon, Portugal.

142 Biography of Authors

Index

AAnalog, 1–4, 6, 9–33, 58, 74, 83, 116, 121, 122

Analog-to-digital converter (ADC), 24, 27, 29,

83, 122

Area, 1, 7, 9, 10, 13, 29, 31, 46, 72, 73, 77, 78, 81,

83, 86, 103, 105, 108, 113, 116, 121–123

Attenuator, 64, 65

BBalun, 6, 7, 14–15, 36, 37, 41, 43, 55, 59, 60,

72, 73, 81–96, 99, 116, 117

Bandwidth (BW), 6, 9, 15, 22, 24, 31, 42–44,

47, 52, 55, 59, 61, 63, 65, 69, 70, 72, 78,

81–83, 86, 88, 92, 99, 105, 113, 115,

116, 122, 123

Baseband (BB), 10, 18, 27–29, 31, 74, 83, 84,

96, 99, 101, 104, 110, 112, 113,

115–117, 122

Battery, 1, 10

BB. See Baseband (BB)

BW. See Bandwidth (BW)

CCircuit, 1, 2, 4, 6, 9–14, 16, 18, 20, 29–31,

33, 36–46, 50, 56, 58–74, 77, 78, 81,

96–101, 103, 105–108, 121, 122

CMOS, 1, 2, 4, 6, 7, 9–12, 14, 16, 17, 33,

35–53, 55–78, 81–118, 121–123

Cognitive radios (CRs), 9, 122, 123

Common-gate amplifier, 81

Common-source (CS) amplifier, 3, 4, 62, 81, 85

Constant transconductance bias, 6, 35, 44–45

Corner effect, 48

Cost, 29, 41, 55, 78, 81, 121

CRs. See Cognitive radios (CRs)CS amplifier. See Common-source (CS)

amplifier

Current, 6, 7, 11, 12, 15–19, 21, 22, 26, 27, 29,

31, 35, 36, 39–41, 44–47, 51, 53, 60, 64,

66, 68, 72, 73, 81, 83–102, 104,

115–118, 121, 122

balancer, 85–88, 116

domain, 85, 86, 117, 118

reuse, 6, 7, 35, 39–41, 83, 96–102, 104,

115, 117

DDC-DC converter, 123

Delay, 32, 47, 92, 103

Digital multimedia broadcasting–terrestrial

(DMB-T), 5, 81

Digital video broadcasting–handheld

(DVB-H), 5, 6, 45, 47, 57, 58, 70, 74, 81

Diode, 37–39, 45, 46, 52, 64, 67, 73

Direct conversion, 36, 55, 99

DMB-T. See Digital multimedia

broadcasting–terrestrial (DMB-T)

DVB-H. See Digital videobroadcasting–handheld (DVB-H)

DVB-H, 5, 6, 45, 57, 58, 70, 74, 81

Dynamic range, 2, 4, 9, 15, 59, 86, 92, 113,

115, 122

EElectrostatic discharge protection (ESD), 6, 11,

35–53, 64, 65, 74, 77, 84, 93, 121

143

FFolded-cascode, 18–27

Frequency divider, 83, 103, 123

GGain-bandwidth product, 19

Gain compensation, 57, 63, 70, 72–73, 78

Gain precision, 26, 27, 122

Global system for mobile (GSM), 57, 73, 74

Gyrator-C Biquad, 100

HHarmonic rejection, 7, 36, 57, 83

IInductor, 15, 70, 72, 84, 85, 116, 123

Integrated services digital broadcasting–

terrestrial (ISDB-T), 5, 6, 81

Inverter, 6, 55, 58, 60–63, 66, 72, 85, 86, 96,

102, 103, 105, 106

Inverter amplifier, 60, 72, 85, 86

ISDB-T. See Integrated services digital

broadcasting-terrestrial (ISDB-T)

KKT/C noise, 122

LLevel shifting, 28, 29, 122

Linearity, 2, 7, 10, 15, 16, 24, 26, 27, 31, 35,

41, 42, 47, 48, 51, 56, 57, 60, 61, 63, 64,

67, 68, 76, 78, 81, 83, 85, 86, 88, 91, 93,

96, 99, 100, 109, 116

Line driver, 9, 13, 32–33

LNA. See Low-noise amplifier (LNA)

Low-dropout (LOD) regulator, 29–31,

122, 123

Low-noise amplifier (LNA), 6, 7, 9, 12, 14–15,

35–53, 55, 56, 58–65, 69, 72, 74, 81–96,

99, 115, 116, 121

Lowpass filter, 7, 15, 21, 83, 116

MMatching, 2, 37, 40, 43, 44, 81, 85, 87, 89, 91,

93, 116, 122

Mixer, 14, 16, 48, 57, 66, 68, 70, 78, 83, 84, 96,

97, 99, 101, 105, 109, 115, 116, 118, 122

Mobile TV, 2, 5–7, 35–53, 55–78, 81–118, 121

Modeling, 41, 46, 66, 67, 83, 89, 91, 100,

102, 106

Multi-phase local oscillator generator, 7

NNoise, 3, 6, 7, 17, 21, 26, 27, 29, 35, 41, 55–57,

60, 81, 83–85, 89, 91, 93, 96, 99–102,

108, 116, 122

Noise cancellation, 6, 35, 41–42, 53, 60, 81,

84–85

OOperational amplifier, 9, 10, 15, 17–27

Overdrive protection, 9, 93

PPassive attenuator, 64

Phase corrector, 103, 105, 108

Phase-locked loop (PLL), 83, 103, 105, 113

Phase noise, 102, 103, 108, 113, 114

PLL. See Phase-locked loop (PLL)

Power, 1–4, 6, 7, 9–15, 17, 19–22, 27, 29, 31,

33, 35, 39, 42, 44–46, 48, 51–53, 55, 57,

61, 64, 68, 70, 77, 78, 81–83, 85, 87, 88,

91, 92, 100, 103–105, 109, 110, 113,

116, 121–123

amplifier, 9–12, 14–15, 33, 83

efficiency, 1, 6, 9, 35, 55, 58, 81, 122

Preselect filter, 6, 55–57, 70–75

RRadio frequency (RF), 1–4, 6, 7, 9–33, 36, 37,

42, 46–51, 53, 55–78, 81, 84, 86, 105,

115–117, 121, 122

Receiver front-end, 7, 81–118, 121

Recycling folded-cascode (RFC), 18–27

Reliability, 2, 4, 7, 9–12, 14, 18–20, 22, 32, 33,

45, 53, 55, 60–63, 66, 68, 74, 78, 87,

118, 121

RF. See Radio frequency (RF)

RFC. See Recycling folded-cascode (RFC)

Robustness, 48, 108

SSample-and-hold, 9, 31, 122

Simulation, 17, 26, 42, 46–52, 64, 68, 74, 77,

101–102, 104–109

144 Index

Slew rate, 21, 27, 122

Software defined radio, 2, 9

Supply, 2, 5, 10, 15, 16, 19, 32, 37, 38, 45, 46,

48, 50, 52, 59–62, 64, 66, 72, 73, 78, 86,

92, 93, 96, 106, 108, 116, 117, 121, 122

Supply voltage, 2, 5, 9, 10, 37, 48, 50, 87,

116, 121

System, 1, 2, 4, 6, 9–33, 41, 74, 102, 121, 123

TT-DMB. See Terrestrial–digital multimedia

broadcasting (T-DMB)

Temperature effect, 4, 11, 74

Terrestrial–digital multimedia broadcasting

(T-DMB), 5, 6, 81

Time-adaptive design, 123

TV-GSM co-operation, 6, 55–58, 73, 74, 77,

78, 121

UUltra high frequency (UHF), 5, 6, 55–57, 81,

83, 84, 107, 116

Ultra-wideband (UWB), 14, 35, 51

VVCO. See Voltage-controlled oscillator (VCO)

Very high frequency (VHF), 6, 55

Voltage-controlled oscillator (VCO), 29, 30,

83, 102, 103, 105, 113, 123

Voltage domain, 97

WWideband, 2, 4, 7, 10, 14–15, 36, 50, 52,

56, 58, 59, 72, 81–96, 113, 116, 117,

122, 123

Wireless technology, 1–2, 9

Index 145

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High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

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