High performance ds e-triggeae flip-flop using a merged feedback t

S.M.Mishra, S.S.Kofail ancl I<.-S.Yeo

'-c>- - ou t

INV3

Table 1: Quality ineastires of existing double edgc-triggered flip-flops

I lcsigi i style ~ ~ ~ _ _ ~

.Ii l ie single pliiise clocltiii$] CZMOS Diflcrciitial Pass lraiisisloi/lransiiiissioii gate

Dt.'l F H 1)k.I kk7 so (:-I)Y Dk-DLT1.t 1's-DY- ~I R - I I Y I-IIi- I'roposed I91 L9I D H I - k I31 IjE-Ikk 1131 I111 D t l FF 151 D t I FF IIt-l FF 161 MF-DF 1 FF

_~~____

DE1 FF Iliillll: ' Ty 11 c Dyiiarnic Dyiiainii: rJynamic: Dyiiiirnic Scini-staiii: DyiiaiTiic Dyiiii i i i ic Sialic Uyiininic

Maximiin CilSi! 1 333 396 464 600 4'/6 !i33 463 5811 605 owrat ing 3 . 3 ~ Cil!:t: 2 !,I1 750 4ti0 47 6 5x3 !J17 613 689 cIocI( ireri.' (M0Cr.I (MHIi 3 3 103 2 63 2 'I li 200 311 357 350

r,ll~l!r Iiigic 0 10.90 0.52 '1.(105 10.93 11.4 6.4 !1.885 679s 8.739

tlissip.3 lociic 'I 33.89 25.9(i 0.6'1 ti/ 11.8 11.4 8.214 9.831 625 7.98 50MI l ~ i SA .~ O.!) l b .45 X / O ? 7!,.07 /O.G7 2'1.Y/ 25.36 6-/6 3S.6li ixw, n.#!iiil,

~~ ~ ~ ~ ~~ ~ ~~~ ~ ~~~~ ~ ~ ~ ~~~~~ ~~ ~~~~ ~~~~~~~ ~~ ~~~ ~ ~ ~ ~

case 1 700 7 32 125 313 216 200 2 ( 3 310 303

SA ~ '1.0' ciisc 1 !27!j 4 58.8Y 19.7/ .l46.7 41.25 41.59 850 77.34

easi! 7 30.9!> 40.00 :EX13 55.95 116.7 38.69 3641 339 70.54

'II_ ci t isisto~ :, N I (Si 18(35.?) %0(37) 'lti(36.8) 16i34.4) 72i55.7) 12113.2) I(ii28) ?0(44) 18(33.(i)

i:oiiriP 4i6.4) 4.iF.4) 411.7) l i3 .7) Z(3.Z) Z(3.7) z(3.2) 7(3.21 G(9.6)

N14.4) Bi9.6) il(9.6) ti(l3.6) 4(10.4) 4iti.4) G(10.4) 4i8.8) 4i6.4)

node:; XI i i i i c l X2 swiiig, tl1e p'lwel voliay~! ciicirit diilrgl! dissipatioii swing ;it i:iirrciil sharing cif ritlici iiiicriirll

DL I I Fs Ilcldes

Prolilciii:; i:Iiiir$jo mi ip l i i ig ;it ti:diii:cd 2.6 tiii ics rcdiiccd shori cascadaliility

~ ~~ ~~~ ~ ~ ~~~~~ ~ ' All circiiils were nptiinised io i 1110 smallest pow[ ion prtir:cdule ilcir iniiltiplc-conslraiiii) iii tisplct. r l6l .

MOCr tiiciisiireiiioiits werc iiiarle by i:oiiiicciiiig tlic outliiit of tho flip-tlop io its iriput tli iouyti i l r i oild iiuiiiticl- ot iiivcitcrs ifoi iiivoiiing ilip flops tlic mitpLit is tied direcily 111 LIii? iiiput) aiid l l ic ilip flops cIocl~!d at the i i i i ix i i i i i i in frcqiiciicy ;it which 11111 swing was still acliicvi!d. Ttic irivei~tcis were :ii7ed lo cnsiirc t l ia l thi: first irivcrici d i v c i i Iiy this i l ip flop picstiritcd ii r:;ipscitivo loail cquivalciil to an idciitical f l ip-f lop I h c lasi irivcrlei provicled a di-ivc ciipiihility siiii i l i i i lo tlic tlip flop t i i idei oliseivalioii. The delay of these ii-ivei~lets was subtracted ironi ilk l ime I m i o d to i i l i k i i i 11ie actiial i~p i~rat i i i i ia l cIocI( fri:qticiicy. Tlic rise i i i i c l fiill l i i i ics ( i f the clock iinc the inpiit wcrc 1% of tlic t i i i iu liciiotl. MOCF iiieasuicinoriis wero tiiaili! ~ i i ider the i w o cases: Case 1: tlic input i i iakcs ii liigcli io I~iwti:ii isitii i i i wl ioi i i:IiicI~ is a low ancl a low to high transition whci i Ihc clock is i i IiiLlli (:ase 2: the iiipiit i i iakcs ii t i igj l i - tdirw lroiisiticiii wliori i l ic cIiii:I( is a high iiiid a low to-high Lraiisition wl ic i i tlic clocli is a low. 1 lie power dissipation calr:ulatioiis wcie 1poi i i i i i i i cd a i :5.3V witli a I:ICICI( speecl of 5 0 M t I ~ and clocl~ i i i id inpi i l iise/fall iitnes o l 200 ps, A

faiioiit of two siinilai flip-ilops was i iss i i i i id. rl t h r a swilc1iiii:j aclivily or 1 .O, a circiiii ca i i operate ciiider eiilicr olthr: two CJWS: Case 1 or Case 2 . Since the cipniation of most (;iiciiits is very dillereill iindnr tho two cases, two valiic!s aic prcscnioil iui SA ~ 1 .U. The raiidoin inputs used for SA: 0.5 were the saino for all circuits. i3 Tho iircii riiciisiircs iiicluilc Ilie iii i i i iber 01 lrarisistors i N I ), I l i c nui i ihcr (if ii iput tiaiisistors (NIT) aiid the number clocl~ccl transistors ( N U ) aloiicj wit l i iicliia silicoii ;iri!;i c!!;tiiii;ilos (S, S

If a l l tiaiisistors iirc iiiade i i i i i i i i r iui i i s i x w

y priiiltict tisiri, tiio 'GOAL' optiini

/J('lO ! i i ~ii iwi i i dissipiilioii o i 5551iW.

111') Iiascd on llaiisistot area alone. The channel Icnglli iiscd was 0.8 !mi.

_h.

CA x 9 T T I

YI ~.

~ ah I N V C

i n -

C K b C i ( 2

out h

4 J s r 1 I"

PP 6

SN

>o - out

h i g i i s (DICI'I~I~I: sec I'ig. 5) coiilprising LWO coiiiplctc l l i ~~ - l l ops iii pa~ i l l c l , con. 01' I S tfiiiisistorb, 01' which 8 iirc cIockcc1. 'l'hc second clcsign (I )lTl~l? sec Pig. 6) improvcs over tlic lirst hy reducing tlic nniiihci- 01' clocltcd tfiinsislors to 6 tliocigli the L O L ~ nuiiibcr of' transistors iiicrciiscs to 20. I h t h designs sul'Fcr il.oiii cliiiigc shariiig prohlcnis, wliicli tlcgfirdc their pcrlimiancc iind powcr dissipiitioir iis cxplainctl iii I 101. A third Ilip-llop proposctl hy Wang 131 nialtcs use 01' the spli l-outpti~ 1'SI'c' sliigcs (SO-I~I~IFI ' : sec I:ig. 7). 7'liis l l i p l l o l i stil'i'crs lroiii rcclticcd swing ;it nodes XI I iiiicl X22, which clcgl.aclcs i ts Iicrl'oriiiaiicc a1 2V. I'Lirtlicr I-ISI'ICI~~ siititilalions intlicatc charge sliariiig hcl\vccn nodes YI I and )'I2 wlicii ilic clock is high iiiiil hctwccn iiodcs Y21 iiiicl Y22 when the clock i s low. ' I ' l i is cliargc sharing occ~it-s wlicii SO-DL:'I'I'I.' is conligLirctl l'or M O W calculations iii Case 2. I n sticli ii conlignration, Y12 is ptillctl low wlicii tIi input iirc hotli low. When the input iiiiilc

Lraiisitioti, iioelc XI I is p~ i l lcd low ( 1 [,'/,,I) tilid node YI I is ptillccl high. I 'r ir~licr, XI2 is ~ ~ i i l l c t l low, Icliving 1'1 2 lloat- ing. When the clock switches to IOW, M4 turns oll' and cli;ii.gc sharing occiirs hctwccii nodes YI I and Y12. ' l ' l i is

SN I 6

PP ' i

i o u t b

sliaring rcduccs t l ic voltage ;it iiodc YI I to 2.05V (supply voltage 01' R.3V and ii technology of O.Xp in ) and iiicroiiscs the voltage at node Y12 to tlic same vollagc IcvcI. A h i i i i i l w situation occtirs Ihr nodes Y2 I ;incl Y22 during the clock low pliiisc. Tlicsc iiitcrmcdialc \dues on YI I / YI 2/ Y2 I / Y22, rcducc Lhc drive strength ol' L r u i s i s l o i s M7, Mi(, M I5 iiiid M 16, icstiltitig i n poor ~~crlhrm;incc Ibr Case 2,

2.3 Differential designs Blair I I 11 titiliscd the r>SIC2(l') iiiid S S ' K I ( N ) liitclics proposed in 141 lo develop ii clil'l'crcnti;il I > l T f l ; ( I l l : - Dli'l'k'l;: sec I:ig. 8) . Wliilc its sliced pcrlbrmancc crosscs llic 5 0 0 M 1 I ~ mark, i ts power dissipalion is a1 least 2.5 tiiiics that 01' tlic other l)Kl'l'l 's prolilctl in l 'ahlc I. Anolhcr difl'crcntial l)L,l'l-'k' l i i i s hccn proposed hy I .ti ('1 d. 1121. It uses two latchcs a n c l it comhiniiig section. I-low- cvcr, its speccl is cxtrcmcly ~ o I : 311s at ii supply voltage 01' 5v antl il 1cchnology 01'2~~l l i .

in -

XI2

2.4 C2MOS based designs ,A tlyiiamic l l l ~ l ' l ~ l ~ Ixiscd on two C'MOS l l ip l lops iii par- iillcl (C-UY-U1i'1'1~I;: sec Fig. 9) Iix also bccii proposcd [ 131. Thc inpul transislors iii the Master C:'MOS latches liiivc hccn nicrgcd to rctlucc tlic tl'ansistor count. The C- DY-lllCl'l-'l~' c m operate a1 ;I clock I~rcqucncy ol 460MI Iz wliicli is oiic ol' the Iiiglicsl ;imoiig the scalahlc Ilip-flops (i.e. DEIFI'I, L)liTI;k'2, C~- l )Y- l ) l i lF l~ ant1 TI<-DY- I > I (1 'I la') with modcra t c poacr il iss i pa t i on.

p w c r dissip;ition a n c l poor stipply voltage scaling piopcrtics, cvc lint1 that the i i i i ixi i i i t i i i i operating clock li.ccluciicy o l l r c d hy cxistiiig Ilip-llops is around 4GOMIHz.

3 Proposed double edge-triggered flip-flop: merged feedback (MF) DETFF

3.1 Design philosophy Ik ist ing 1lli'I'l;b's arc constrtictctl, in gciicl-al, li.om either coi i iplctc IiitcIia o r coiiiplctc llip-llops witl i niiiior optimi- sitions to rcducc t l ic ntiiiibcr 01' ti-ansistors. The approach tiscd in the dcvclopmcnl 01' the proposcd circuit l i i i s hccii to aii;ilysc tlic operation 01' thcsc circtiits hasctl oii the relative phases ol' tlic cloclc aiid thc input (clock: Iiighilow and input: Iiigh/low) i i i i c l constriict spccilic circuits lor ciich case i i t i d t hus red~icc tlic iiiiiltistngc tlclap inlicrciit in thc tisc 01' coiiiplctc Iatclics or Ilip-llo1is. Fig. IO shows ii hloclc dia- grani representation 01' this iippi-oiich. l l i c output 01' Stage I (XI) is ptillccl IOW wlicii the clock i s high and the input gocs high. %age 11. 011 the other hand, is pt11Icd low wlicii the clock is low and the i n p i goes high. Thcrclorc, the cir- cuits ol Stages I antl I I , clctcct i i cloclc tfiiiisition iiiid p i s s ii high iiiptit Lo tlic otilptit. Stages I l l and I V do tlic same Ibr a low inpil l.

E,xcluding the Ilip-ilops with ex

1- out

3.2 Proposed circuit The proposed circuit (mcrgctl fccdhack DETFF MI;- DtTl;l;) of I'ig. I I, is hasctl on tlic coiiccpl advuiccd iii I'ig. IO. Stages I~ I V liiivc hccn i i ia ikcd in the ligtirc. Also i i i i i ikcd is the mcrgcd I'ccdb;iclt I W P N section: MI ;-l'l'/l'N (li)rmcd by iiicrging ii pi'ccliargcd 1,-stage (1'1') ;incl a prc- charged n-stage (1") 141). 111 the ahscncc 01' lcctlback, llic circuit i s highly susccptiblc to charge cotipling (sec [IO] lor an analysis ol charge cotipliiig in dynamic Ilip-flops). Imag- ine iin im~~ lc i i i cn~a t ion 01'Stagc I I which ~LIIIS X2 low when cloclc is i t low ancl input is ii high and Icavcs i t Iloating i'or all other comhiiiations 01' Llic input and the clock. Siich ;I scction can be conslrnctctl hy using a structure siiiiiliir IO

Stage I to dl.ivc X2, with thc exception t1i;it ilic iiivcrsc 01' t l ic clock is L I S C ~ f i i t l icr than the clock itsell'. I Iciicc. wlicti the clock would liiivc ch;ingc:ctl pliiisc, node X? hcing lc l i Iloating. would have ciilxicilivcly coupled to aiiy voltage changes at t l ic oiitptiL t i n c l node U . Similar charge coupling coriltl also a1'1'cct node YI . l ' l i c Iircsciicc 01' Mt-I'I'A'N ciistircs tliat nodcs X2 i i i id YI l ire i iot l c l i Iloating wlicii they iirc highly stisccptihlc to capiicitivc r:oupliiig.

111 the MI;-I)ITI'I:I~'~ nodcs ,\'> iiiicl YI ;ire L I S C ~ iis inpiits to Ihc Ml,'-l'I'/l'N section. TIic outpii i could tis \ d I hc tiscd 10 licrlbriii tlic siiiiic t a s k hut t h n t ~ ~ i i l d iiicrc;isc tl ic capacitive load driven hy tlic outpiit.

3.3 Performance analysis 'I'Iic iii'cii, tiiiixiiiiiiiii operating clock I'rcqiiciicy (MOCF). ant1 power clissipation ligiircs of' the M I ~ - l > E T I ~ l arc given in 'l':ilAc I, wliilc Lhc supply vollagc iiiid tcchiiology scaling Iigtircs i i i c provitlcti in 'l'iildc 2. As sccii li.oiii tlrc tables, the MI~-I)ICI'I;I" ciiii operate at (:lock I'rcqucticics 01' over OOOMI Iz. scalcs well with the sripply voltage aid tcclinol- ogy, iiiid occupies iiii iircii comp;iriihlc with o~hcr tlotiblc cdgc-t riggcrctl lli~)-llops.

Table 2: Scaling of the MF-DETFF with the supply voltage and technology

Casc2 689 350 847 762 .__ ' For all simulatiiins, the sainc aspecl r a i i i ~ was inaintaincd (i.e. all lransislors wcre minimum s i x d exccpt M I with WIL = 3/1 and M2 for which W/L - 2/11, Thc initii i i iti in lraiisistur widths for l l ic O.R! i in, 0.5!im, atid 0.35!11n technologics are 2.0piri. 2 . O ! m , and 1.01~tn. rcspcctivcly. Tlia threshold vd layc and oxidc tliiclmcss lor thc 0.5~1rn and 0.35lim technologies arc (V,,,(nMOS) L 0.65V, Vtlj(p- MOS) = -0.65V and 7,, 12niri) and (V,,,(i)MOS) = 0.42V. Vt,,(p- MO3 =-0.42V aiitl 7;>,.- grim), rcspectivcly. ' Thc MOCF calcirlations werc porlormctl will) risc arid fall timcs o l the clock ancl the inptit being 1% or thc tinic pcriod.