IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 1

HIGH PERFORMANCE FLOW MATCHING ARCHITECTURE FOR OPENFLOW DATA PLANE

T M Dananjaya, V B Wijekoon, P Kariyawasam, S Iddamalgoda, A PasqualDepartment of Electronic and Telecommunication Engineering

University of MoratuwaSri Lanka

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 2

Outline

• Challenges in SDN and NFV• Flexible and programmable but inexpensive• Openflow aware RISC network processor for SDN-NFV• Novel and comprehensive flow matching architecture• High performing data plane architecture• FPGA implementation with minimum hardware resources• Conclusion

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 3

Background

• Performance of the SDN systems depends on how efficient it can carry out flow matching and flow management

• One of the integral parts of SDN is forwarding traffic according to the rules sent by central controller using southbound protocols such as Openflow

• Recent SDN research focuses on highly programmable high performance networks

• Most of the prevailing solutions are expensive and consume more resources such as TCAMs to achieve high performance

• Increasing demand for the more manageable and programmable SDN devices

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 4

Challenges

• Complete ASIC approach has higher performance, but lack of flexibility• Complete processor approach is more flexible and inexpensive, but

lacks performance• Providing low cost, inexpensive solution with low resource utilization,

keeping the high performance is challenging• Enhancing flexibility and programmability of the SDN solutions is

another aspect• Facilitating changing needs of the evolving southbound protocols

(openflow etc.) is another big challenge

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 5

Proposed Architecture

• Integrated approach of a custom processor and dedicated parallel logics

• Customized RISC network processor with custom instruction set architecture (ISA) for SDN

• Processor takes care of sequential tasks providing more flexibility and programmability

• Dedicated logic for performance intensive tasks of flow matching with match-action pipeline with reduced TCAM usage

• Implementation of the system with minimum FPGA resources

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 6

ArchitectureDPL INT – Data Plane InterfaceMEM INT – Memory InterfaceINS – Instruction MemoryPKTS – Packet BufferOFB – OpenFlow Buffer

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 7

OpenFlow Aware RISC Network Processor

• Consist of custom instructions to handle SDN packet forwarding tasks

• Provide flexible interface to programming as well as communication interface to access data forwarding plane

• Can handle Openflow agent inside SDN switches and responsible for the secure southbound (Openflow) communication

• Customized instruction such as DPLRD, DPLWR, ENQUE, DEQUES is used to make it more Openflow and SDN aware

• Provide general network and packet processing tasks (CRC etc)

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 8

OpenFlow Aware RISC Network Processor

Instruction Description

DEQUES Dequeue Packet From input queue

ENQUE R1 Enqueue packet into queue R1

DPLRD R1 R2 A Read From Flow Tables/Data Plane

DPLWR R1 R2 A Write to Flow Tables/Data Plane

PDROP Drop Last Processed Packets

TABLE R1 Choose Table Given by R1

CRC R1 R2 R3 Carry out Cyclic Redundancy Check

CHKSM R1 R2 R3 Introduce Checksum Fields

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 9

RISC Instruction Format

• All Instruction are fit into four main instruction formats

• ISA Can be divided into four broad categories (Memory Access, Control, ALU and Data Plane)

Opcode

opcode

opcode

opcode

R R R C F

R R Address/Immediate

Address

R R C C F

Opcode : 6 bitRegister (R) : 5 bitConstant (C) : 5 bitFunction (F) : 6 bit

Address (A) : 26 bitImmediate(I) : 16 bit

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 10

Data Forwarding Plane

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 11

Flow Matching and Action Execution

• Packets coming to the Ingress are parsed by the classification/parsing unit by extracting Match Fields to field buffer from Headers

• Then the Match Field is matched against the Flow Cache which reduces the look up time of the TCAM by storing the most recent flows

• Flow Matching Pipeline consists of several pipeline stages and collects the action need to be executed against the Packet Header

• If a Match is found, Action Execution Unit (EU) executes OpenFlow actions against the Header

• In addition EU consist of Recombination of the Header and Payload

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 12

Flow Matching Architecture

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 13

Flow Matching and Action Execution

• When a flow is not matched in the matching pipeline, a table miss packet is found

• Then the processor takes care of handling the packet according to the OpenFlow protocol

• The packet is de-queued from the packet buffer, assigned an OpenFlow buffer id and generated a packet out for the controller

• Then it gets the controller rules for the flow as a packet out and program the TCAM

• Resubmit the packet to the data plane

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 14

Processor and Flow Matching Architecture

• Programming/Configuration (AXI4) interface can be driven by processor to configure Data Plane (DP) according to OpenFlow

• Communication Interface (AXI4) used to transmit and receive packets from and to data plane

• In order to process table missed packets, processor dequeue and encapsulate it and send it to SDN controller through secure OpenFlow Channel

• Then Interpret Controller’s Instruction to Program Data Plane

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 15

Resource Utilization

LUTS

REGS

MUXS

0 20 40 60 80 100 120

FPGA RESOURCE UTILIZATION

Utilized (%) Available

Resource Used Available %

LUTs 48359 303600 15.93

Registers 47629 607200 7.84

F7 Muxs 707 151800 0.47

F8 Muxs 238 75900 0.31

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 16

Results

INSTRUCTION CYCLES

Memory Access and Control Instruction (Except LORD)

4

Data Plane (OpenFlow) Instruction (Except DPLRD)

4

ALU Instruction (Except BRE, JMP) 4

LORD,DPLRD 5

BRE,JMP 3

• Generated Network Traffic comes into the Data Plane as 512/1024 bit AXI4 Stream via Ethernet Sub system

• Classification Engine was operated at 250MHz

• Pipeline Stage Can go beyond 1GHZ• Initially using single classification

engine data plane was tested at 250 MHz

• Processor was operated at 150MHz frequency

• Average Throughput of the match unit is about 250 Gbps and it contain two pipeline stages

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 17

Conclusion

• OpenFlow Aware Custom RISC Network Processor provides more flexibility and programmability to Dedicated Hardwired Data Plane Approach

• Neither complete ASIC type hardware approach nor complete processor approach offer optimal solution

• Introducing integrated architecture with custom RISC processor and dedicated Data Forwarding plane will increase performance.

• This approach reduces the resource utilization and enhances flexibility and programmability of the complex network hardware in the future

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 18

THE END

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 19

Timing Results

Module Min Period (ns)

MAX FREQ (MHz)

Min Set-Up Time (ns)

Max Hold Time (ns)

Classifier 2.965 337.268 2.718 0.845

Match Stage 0.831 1203.370 3.089 11.404

Memory 2.363 423.191 2.948 0.687

Flow Meters 4.058 246.441 4.124 3.192

Execution Engine

1.95 512.014 3.641 1.032

TM Handler 0.981 1019.368 1.578 0.687

IEEE NFV-SDN CONFERENCE 2016, PALO ALTO, USA 20

References

[1] Nick McKeown, Tom Anderson, Hari Balakrishnan, Guru Parulkar, Larry Peterson, Jennifer Rexford, Scott Shenker and Jonathan Turner, “OpenFlow: Enabling Innovation in Campus Network“, ACM SIGCOMM Computer Communication Review, vol 38, no.2, pp.69-74, 2008[2] ONF, “OpenFlow Switch Specication 1.4.0“ Oct. 2013[3] Omar El Ferkouss, Ilyas Snaiki, Omar Mounaouar, Hamza Dahmouni, Racha Ben Ali, Y ves Lemieux, Cherkaoui Omar, “A 100Gig Network Processor Platform for OpenFlow“, In proceedings of the 7th International Conference on Network and Service Management, pp.286-289, 2011[4] Keissy Guerra Perez, Sandra Scott-Hayward, Xin Yang, Sakir Sezer, “Memory cost analysis for OpenFlow multiple table lookup“, 28th IEEE International System-on-Chip Conference (Beijing, China), Sep. 2015[5] Fei Hu, Qi Hao and Ke Bao, “A Survey on Software-Dened Network and OpenFlow: From Concept to Implementation“, IEEE Communication Surveys & Tutorials, vol. 16, no. 4, 2014