HIGH PERFORMANCE GOLD PLATING FOR MICRODEVICES A. Gemmler, W. Keller Fraunhofer Institute of Manufacturing and Automation (IPA), Eierstr. 46, D-7000 Stuttgart 1, Germany H. Richter, K. Ruess Alcatel - SEL Research Center, Lorenzstr. 10, 0-7000 Stuttgart 1, Germany Abstract Tremendous improvements in the performance of microelectronic devices have been creating increased demands on fabrication processes such as gold plating. By means of continuous bath control and consequent application of a synergistic operational model, high quality gold layers have been deposited from a sulfitic gold electrolyte. Periodic recording both of existing process data and resulting layer properties yielded a synergistic model to control the plating process. Sources of voids by nodules or pits were characterized using SEM and acoustomicroscopy. Further factors that influence quality of gold deposits (hardness, roughness, uniformity) could be optimized by flexible process control. Introduction VLSI - techniques (very large scale integration) have been key components for developing future products in micro-electronics, -mechanics and -optics. The increase in performance of semiconductor circuits demands adapted miniaturized fine pitch packages with high interconnection densities. Several techniques have been developed to diminish the electronic gap between the wiring densities of chip and board: MCMs (multi-chip-modules) are an attractive packaging solution, if interchip delays are critical to the system performance. TAB (tape automated bonding) and FC (flip chip) techniques for the mounting of bare dice are promising assembly alternatives to wire bonding /1-5/. TAB requires the bonding of tape leads to gold bumps on the semiconductor (Figure la). The gold bumps serve the immediate Purpose of elevating the height of the semiconductor bond pad in order to avoid shorting. Alignment accuracy, bonding speed and Process control are crucial criteria for reliable TAB applications. 1 553
Transcript
HIGH PERFORMANCE GOLD PLATING FOR MICRODEVICES
A. Gemmler, W. Keller
Fraunhofer Institute of Manufacturing and Automation ( I P A ) , Eierstr. 4 6 , D-7000 Stuttgart 1, Germany
H. Richter, K. Ruess
Alcatel - SEL Research Center, Lorenzstr. 10, 0-7000 Stuttgart 1, Germany
Abstract
Tremendous improvements in the performance of microelectronic devices have been creating increased demands on fabrication processes such as gold plating. By means of continuous bath control and consequent application of a synergistic operational model, high quality gold layers have been deposited from a sulfitic gold electrolyte.
Periodic recording both of existing process data and resulting layer properties yielded a synergistic model to control the plating process. Sources of voids by nodules or pits were characterized using SEM and acoustomicroscopy. Further factors that influence quality of gold deposits (hardness, roughness, uniformity) could be optimized by flexible process control.
Introduction
VLSI - techniques (very large scale integration) have been key components for developing future products in micro-electronics, -mechanics and -optics.
The increase in performance of semiconductor circuits demands adapted miniaturized fine pitch packages with high interconnection densities. Several techniques have been developed to diminish the electronic gap between the wiring densities of chip and board: MCMs (multi-chip-modules) are an attractive packaging solution, if interchip delays are critical to the system performance. TAB (tape automated bonding) and FC (flip chip) techniques for the mounting of bare dice are promising assembly alternatives to wire bonding /1-5/. TAB requires the bonding of tape leads to gold bumps on the semiconductor (Figure la). The gold bumps serve the immediate Purpose of elevating the height of the semiconductor bond pad in order to avoid shorting. Alignment accuracy, bonding speed and Process control are crucial criteria f o r reliable TAB applications.
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Another fast-growing microtechnological area represents the fabrication of small three-dimensional microstructures by application of the LIGA process /6-10/. Main advantages of this technology are the very high aspect ratio as well as its wide material selection. Microstructures of copper or gold are preferably produced to meet demands on conductivity, such as nickel (Figure lb) Nickel cobalt alloys are used to obtain good mechanical strengths. The large potential of LIGA-applications could be significantly extended through techniques with sacrificial layers as intermediates. As a latest novelty, an electrostatic micromotor has been introduced /ll/.
Electroforming of microstructures
Both the bumping and the LIGA process start by sputtering a Ti/W diffusion barrier on a silicon substrate and a gold strike layer as a plating base. Microstructural patterning is achieved by photolithographic processes. During the subsequent plating operations within the resist windows the metal is deposited up to a nominal height of typically 25 q n for bumps or 100 - 300 qm for LIGA-products (Figure 2 ) . Finally, the photoresist and the conductive layer are removed.
Successful processing depends on several conditions: While resist layers of insufficient thickness result in mushroom shaped structures, excessively thick resist deposits may lead to an uncontrolled amount of residues after developing /12/. However, the most important step for high-accuracy electroforming is due to the knowledge to manage a flexible control of the plating process. Analogous methods have been recently described for electroless nickel /13/. In this paper, the aspects of high performance gold plating will be demonstrated and discussed exemplarily for the bump plating process.
Gold Plating
Gold has fought off many challenges in the last forty years to remain the first choice in two major areas of electronics /14/: Surface finishing and interconnection technologies. Gold is preferred to cheaper alternatives such as solder when high performance and reliability is
Pure gold deposits have usually been obtained from potassium cyanide gold plating baths at neutral pH ranges. Due to the poor resist compatibility of such electrolytes, resists are partially underplated at their bases and, as a result, the formation of a bump foot is a common feature /15/. Non-cyanide pure gold electrolytes are available based on the sulfitic gold complex . In contrast to cyanide baths, they have a better compatibility towards comparable resists. Furthermore, they have an increased throwing power and yield deposits which exhibit more
[ A u ( S O ~ ) ~ ~ - ]
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uniformity in thickness. Along with the improved grain refinement and smoother topography of the deposited gold bumps (Figure 3 ) , all these advantages have led to the almost exclusive utilization of sulfite gold baths for high performance plating processes like wafer bumping.
The plating process
The gold (I) sulfite complex dissociates according to the following equation into free aurous and sulfite ions:
A~ (soj) 23- - AU+ + 2 ~ 0 ~ 2 -
The gold (I) sulfite complex is about lo2* times weaker than the gold ( I ) cyanide complex (K = 1 0 - 3 8 ) . Although its stability is improved through a high free sulfite concentration i n the electrolyte, a gradual precipitation of gold can happen. Cathodic reduction of sulfite to dithionite and its subsequent reaction with free aurous ions must additionally be taken into account /16-18/.
Considering the sensitivity of gold plating and its application in microforming, sophisticated process engineering must be realized t o optimize the plating process to allow us to predict failures before they occur. This method involves using a model of the process in order to calculate the output or hard-to-measure variables from other, easy to measure input variables. Mathematically, the set of existing process parametersxm have to be mapped on the set of the deposit properties Yn (Figure 4 ) . To create the graph of corresponding relation, all measurable plating parameters and selected deposit characteristics are monitored in the C O U K S ~ of processing one hundred wafers. These process parameters and their values are shown in the upper part of Figure 5, whereas in the lower part some objective deposit characteristics are listed.
In Figure 6 a, the concentrations of gold and leveller/grain refiner are documented as "input variables"' hardness and roughness of the gold deposits as "output variables".
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Gold has been monitored by two different analyzing methods: Atonic absorption spectroscopy (AAS) and gravimetry ( G M ) . Figure 6 clearly suggests, that AAS-values are dependent on the metal turnovers of the bath. Therefore, a more reliable analytical procedure is represented by gravimetry. Trivalent arsenic ions act as levelling and grain refining agents. They operate at extremely low concentrations of only a few ppm (Figure 6 b). Arsenite was obtained from modified bath samples by differential pulse polarography (DPP) as the only reliable method.
Gold bumps for TAB interconnections must meet a rigid set of criteria including excellent height uniformity, good coplanarity and adhesion to the bump base, and no type of deposit defects. Furthermore, they should be sufficiently ductile and of hardness low enough to prevent cracking of the passsivation and cratering which is a common ILB (inner lead bounding) failure mechanism /19/.
By nature oE the plating process utilized to grow gold bumps, tensile and compressive stresses are encountered and must be annealed out. Figure 6 c demonstrates an increasing hardness (vickers, load 25 g) of the deposit as plated versus number of processed wafers. This corresponds very significantly with arsenite concentrations in the range of about 60 to 70 processed wafers where lower arsenite concentrations produce lower hardness. As described by Wilkinson /18/, the hardness is not due to arsenic in the deposit, but to grain refining. This is in accordance with an almost constant level of hardness after annealing.
The surface roughness of the deposit as plated and after quick etch - to remove the conducting strike layer - has a slight tendency to increase, depending on the number of processed wafers (Figure 6 d). In general for pure gold deposits, the roughness obtained from sulfitic solutions is 18 to 2 0 times lower than that from cyanide electrolytes (see Figure 3 ) . Concentrations of essential bath components at the start and after processing of 100
indicates that the total amount of salts in the bath has considerably increased: however, the deposit characteristics cannot be derived directly thereof.
Process modelling
wafers including replenishments are shown in Figure 7. It
Due to complex cross-linking between process variables and resulting deposit characteristics an operational model of sulfitic gold plating was developed. This synergistic model is identical with the graph of the relation between the set of the existing process parameters (%m) and the set of the deposit properties (Y,) which was mentioned above. The qualitative chemical part of the operational model is presented in Figure 8.
The quality of the gold deposit is influenced by the process parameters, pictured at the top and bottom lines of Figure 8.
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Thus, causes of occurring 'effects are classified to distinguish primary and secondary origins. Primary causes can be derived from plating variables like current density, pH, sulfite or arsenite concentrations; secondary causes stem from external process parameters e.g. resist impurities or uncarefully prepared Au(S03)23- solutions.
As shown in Figure 9 the concentration of different trivalent arsenic species substantially depends on pH. The sulfitic gold electrolyte is maintained at a pH of 9.0. Arsenic additives-of pH 14 contain as main component H2As03 . Practically, H2AS03 is protonated in the bath to glve corresponding amounts of polyarsenite [As(OH)3], . The part of polyarsenite which preliminarily remains soluble acts as levelling and grain refining agent (polyarsenite active ) . Aged polyarsenite precipitates (see in Figure 8: polyarsenite particles ) and is incorporated into the deposit. The effect of polyarsenite active is influenced among others by salt enrichment and filtration. Due to the mass transport control in the cathodic diffusion layer, salt enrichment implies a lower amount of the active species at the cathodic surface. As a result, the deposit roughness is slightly increased. Salt enrichment can be traced to higher concentrations of sulfate, sulfite and chloride (see Figure 7). Conditionally, fine filtration can diminish polyarsenite actlve . Deposit defects
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Periodically, a characteristic deposit defect can be observed during bump plating: Nodules may vary in size and height (Figure 10 a ) . Their presence leads to increased stresses at ILB- processes and finally to a less reliable TAB assembly. Lateral bump nodules can cause short circuits between adjacent bumps after quick etching. Subsurface imaging was achieved by scanning acoustic microscopy (SAM). In the SAM-photograph, Figure 18 b, the penetration depth of ultrasonic was calculated to be about 9-15 qm. The two centered discs illustrate the growing of two gold particles which were trapped during plating and adhered on the intermediate layer surface. A comparison between the cross section and a computer simulation (Figure 10 c,d) demonstrates the effect o f nodular bump growth by incorporating very small metallic particles.
According to the operational model in Figure 8 , gold particles can either be produced by reactions in the electrolyte (primary causes) or are dragged in with uncarefully prepared gold sulfite complex (secondary causes). Both the filtration of the particle containing solution and/or dummy plating are methods to remove Such gold particles.
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The following primary causes originate from the bath:
- Precipitation of gold results when the concentration of uncomplexed Au ( I ) -ions in the gold sulfite solution is locally exaggerated e.g. by anodic oxidation of sulfite to sulfate or by its oxidation at the phase boundary liquid/air. Controlling anode potential and minimizing the extension of the phase boundary liquid/air will hinder gold precipitation.
- Dithionite which is formed from sulfite at the cathode and subsequently transported to the bulk electrolyte reduces aurous ions to gold. By using a stabilizer, the formation of dithionite is restrained.
Another typical defect which affects gold plating is the appearance of pits (Figure 11 a). Pits can be traced to secondary causes. Scanning acoustic microscopy indicates a characteristic irregular shape of gold growth (Figure 11 b). The process model (see Figure 8 ) and supplemental investigations give evidence of two possible failure mechanisms:
- residues in the resist openings (Figure 11 c),
- incorporation of dragged-in resist or other non-conductive particles (Figure 10 d)
Like nodules, pits give rise to less reliable TAB-assemblies by weakening the bumping strength between bumps and inner leads of the TAB-frame. They can be avoided by careful control of the lithographic process and proper operating conditions.
The results of interactions between particles and cathodes are supported -by recent calculations of J.P. Celis, et.al., which describe the primary current distributions at cathodes, with both adjacent conductive and nonconductive particles / 2 0 / . The modification of the current field around absorbed particles is characteristically evident. In compliance with the current distributions, pit formation in the presence of non-conductive species, like resist residues (upper part of Figure 12) and nodules growing from conductive gold particles (lower part of Figure 121, can be easily understood.
Summarized, the presented investigations yield a synergistic operational model by periodic recording of existing process data and the resulting layer properties. The functionality of the deposit is provided by the concurrence of the plating parameters and deposit characteristics. Consequent application of the model allows installation and effective control of high performance.
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gold plating. plating process.
Figure 13 shows series of bumps after optimizing the
conclusions
Semiconductor complexity has been advanced to VLSI-techniques with 100,000 or more components per chip. Interconnection and packaging densities are to follow. A similar trend towards continuously decreasing pattern sizes is expected for devices in micromechanics, microsensoring and micro-optics.
High pereformance electroforming will participate with a higher standard of process engineering. High performance plating exhibits improved understanding, improved controlling and improved precision.
Acknowledgments
The authors would like to thank M. Worbs, W.Jb'rg and H. Hanisch for the experimental work, L. Brummer, 8. Frey and W. Leonhard for analytical assistance. The cooperation and support of H. Reichl, 0. Ehrmann, G. Englemann and J. Simon, Technical University of Berlin, is gratefully acknowledged.
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a) Bumps on a test-IC
Figure 1. Representative microdevices
b) LIGA-fabricated micro-gear inside of a needle eye (by courtesy of MicroParts GmbH, Karlsruhe, / 8 / )
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