High-speed encoder for the 16S9Q linecode

A.H. Prystajecky, M.Sc, Mem.I.E.E.E., Prof. P.A. Goud, Ph.D.,Sen.Mem.I.E.E.E., and Prof. C.G. Englefield, Ph.D., Mem.I.E.E.E.

Indexing terms: Logic, Circuit theory and design

Abstract: A novel approach is described for the high speed implementation of a 2nB/(n + l)Q transmission linecode. Input data are processed so that the (n + l)th control symbol is available well before it is required at theend of each word. The performance of this codec scheme was verified experimentally using the \6B9Q code in amultimode optical fibre link at 44.736 Mb/s.

1 Introduction

Line coding, the process of matching data signal propertiesto transmission system characteristics to facilitate optimaltransmission, is an important aspect of digital communica-tion system design. A number of line codes have beendesigned and implemented for this purpose [1-7].

In this paper we consider the high speed implementa-tion of a newly developed 2nB/(n + \)Q line code whichhas good spectral and timing characteristics, an increasedinformation capacity compared to binary line codes, andbit rate and range extension capability. The particularcode considered is the \6B9Q line code, which transformswords of 16 input binary digits into words of 9 four-leveloutput symbols [8]. The running digital sum (RDS) of theoutput sequence is constrained by the selective inversion ofgroups of 8 bit input half-words in order to minimise thelow frequency spectral content. Each output word consistsof two 4-symbol half-words, obtained from the 16-bit inputword. A ninth symbol is added to each output block toindicate which of the half-words, if any, have beeninverted.

This code was originally implemented at a fairly low bitrate (640 kb/s) [8]. Thus, sufficient time was available toobtain the digital sum variation (DSV: the change in theRDS after each 8 bit half-word of the incoming bit stream)to determine whether to invert the half-words, and to cal-culate the outgoing RDS including the value of the ninth

C/2

binarydata in

serial toparallel mag

pol

serial to,parallel * tj

symbol. At high bit rates, however, time constraints arisedue to limitations of the circuit components (switching anddelay times), limiting the maximum data rate that can beprocessed to less than 20 Mb/s, even when high speedlogic forms such as MECL 10 KH are used.

A novel method has been developed for implementingthe \6B9Q line code at a high bit rate (45 Mb/s) for trans-mission along a multimode optical fibre. It permits thehigh speed addition of incoming data using serial adders,with parallel addition to determine the RDS [9].

2 High speed implementation

Fig. 1 shows the overall block diagram of the \6B9Q linecoder. All coding operations are performed on the datasignal in binary form. The final state of the coder convertsthe coded binary signal into a four-level signal accordingto Table 1, before sending it to the transmitter. Binarydata entering the coder are separated into two parallel bit

Table 1 : Translation algorithm for binary to quaternarysymbols

Binary input Quaternary output

10000111

- 3-1+ 1+3

C/2 C/2

serial toparallel (B)

4-bitlatch (O C/8

A-bitlatch (D)

invert

parallel ,_.to serialy '

Di0202

nnagpol

C/8C/2"

LSB

• / -

C i n

DSVadder

LSB

MSB

Cm • / -

RDSadder

L— eomoare —-Icompare

parallelto serial

2-6 levelconverter

C/16- F F D

16

QD FF

pol9th

compare

-C/8

-C/8

-icsymbol I mag I 16

SIS0 SI SO

U-level signal outPaper 4474G (E10, C2), first received 17th September 1985 and in revised form 10thJanuary 1986The authors are with the Dept. of Electrical Engineering, University of Alberta, F i 9 - 1 Schematic diagram of\6B9Q coderEdmonton, Alberta, Canada T6G 2G7 mag = magnitude pol = polarity

IEE PROCEEDINGS, Vol. 133, Pt. G, No. 2, APRIL 1986 115

streams, the odd numbered bits representing the magni-tude of the four-level signal, and the even numbered bitsrepresenting the polarity (see Table 1).

In order that the DSV and RDS adders have sufficienttime to process incoming data, a parallel storage structureis used in the input section of the coder. At the same timethat data bits are accepted by the coder and sent to theDSV adder, they are loaded into shift registers (A and B ofFig. 1) and stored. By the time the entire 16 bit input wordis accepted, the first half-word is coded and ready to besent to the transmitter. The holding time of 8 bit periods isimplemented by two sets of four-bit shift registers (A, B, Cand D of Fig. 1). Data are serially shifted into the first setof shift registers (A, B) which, when full, perform a parallelload into the second set of registers (C, D). If a decision toinvert is made, a signal is sent to the polarity bits of thehalf-word stored in the shift register C. This signal invertsthe polarity bits, after which the entire half-word is loadedinto shift registers E and F and sent serially to the 2-4level converter. Fig. 2 shows the timing diagram for this

clock

XX

*

XX2

X24

246

468

4

MUJ

6810

[7146

l8j

81012

ft4

18

101214

[2"46

U

121416

RuH12141M6

14162'

iol121416j

162'4"

1214U6

9 th polarity(18)

it"°" Jinnju^nruinnjuuinnnniL

magnitude(17)

E outgoing polarity data-

TFig. 2 Timing diagram of the coder for the polarity bits, showing thecontents of the registers

The numbers refer to the bit locations in a 16 bit wordThe polarity and magnitude of the 9th symbol are available at the times shown

portion of the circuit. The contents of polarity bit shiftregisters A, C and E are displayed, as one 16 bit inputword is coded. Identical operations occur in magnitude bitregisters B, D and F.

Both DSV and RDS adders are constructed as 6 bitripple through adders, using 2s complement arithmetic.The DSV adder determines the digital sum variation of theincoming 8 bit half-word (4 magnitude bits and 4 polaritybits) by performing serial additions; i.e., one symbol(2 bits) at a time. Magnitude and polarity bits are clockedinto the DSV adder at a rate of C/2 (where C is the inputclock rate). The polarity bits determine whether additionor subtraction occurs, while the magnitude bits determinethe magnitude of the number to be added or subtracted.The result of an addition is stored in flip-flops, andbecomes the second operand of the adders in the nextaddition. Using appropriate logic families, an addition canbe completed in less than 10 ns, allowing the adder tooperate at rates exceeding 100 Mb/s. Upon completion offour additions, the DSV of the 8 bit half-word is knownand is available for addition to the previous RDS toobtain the current RDS.

The current RDS is determined by a parallel addition ofthe DSV to the previous RDS. That is, every C/8 the entireDSV 2s complement number is clocked into the secondoperand of the RDS adder, while at the same time the pre-vious RDS 2s complement number is clocked into the firstoperand. This addition also takes less than 10 ns, afterwhich the RDS adder remains idle until the succeeding C/8pulse.

The correct RDS for the transmitted symbol streammust include the value of the ninth symbol. However, thisextra addition may be avoided by initialising the DSVadder to —2 for the first half-word, and to —1 for thesecond half-word. This procedure will give the correctoverall RDS value at the end of each 9-symbol word, asinversion of the half-words, if any, will change the RDS by+ 2 and/or + 1 . The various possibilities are given in

Table 2: Creation of the 9th symbol in the 16B9Q line code

First word Second word Result on Result on 9th Symbolfirst word second word DSV

not inverted not inverted - 2 - 1not inverted inverted - 2 +1

inverted not inverted +2 - 1inverted inverted +2 +1

- 3- 1+ 1+3

Table 2. By avoiding the direct addition of the ninthsymbol, each word can be processed completely before thenext incoming word is stored. This also simplifies circuitimplementation. In addition, the ninth symbol is createdby the coder at a time when the entire coded word isstored in shift registers C to F of Fig. 1. Through the useof SISO registers, the ninth symbol is delayed sufficientlyso that it appears in the outgoing data stream followingthe second half-word.

The design approach for the decoder is similar to thatof the coder [9].

3 Conclusion

The circuit described above was constructed and tested at44.736 Mb/s in an optical fibre link. Fig. 3 displays key

3589.w w v > *. Wv

200»M 2M I 1 lOOn$«j>

Fig. 3 Experimentally observed waveforms

a 16 bit binary input wordb Magnitude input to level converterc Polarity input to level converterd 9-symbol 4-level output wordThe vertical dotted lines indicate the 9th symbol

experimentally observed waveforms of the coder. Goodsystem performance was obtained, indicating that theimplementation of the 16B9Q line code as well as that ofother similar codes is feasible at high bit rates. By produc-ing the codec in the form of.a semi-custom integrated

116 IEE PROCEEDINGS, Vol. 133, Pt. G, No. 2, APRIL 1986

circuit, even higher data rates of hundreds of Mb/s couldbe processed.

4 Acknowledgment

This work was partly supported by the Natural Sciencesand Engineering Research Council of Canada (NSERC)under grants A-1710 and A-3725. A.H. Prystajecky wouldlike to thank NSERC for the award of a post graduatescholarship.

5 References

1 MORRIS, D.J.: 'Pulse code formats for fiber optical data communica-tion' (Marcel Dekker Inc., New York, 1983)

2 BROOKS, R.M., and JESSOP, A.: 'Line coding for optical fibersystems', Int. J. Electron., 1983, 55, (1), pp. 82-120

3 BYLANSKI, P., and INGRAM, D.G.W.: 'Digital transmissionsystems' (Peter Peregrinus Ltd., UK, 1976)

4 PETROVIC, R.: 'Multilevel signals in digital optical-fibre communica-tions'. Electron. Lett., 1978, 14,(25), pp. 806-808

5 WATERS, D.B.: 'Codes for digital line transmission', Commun. Int.,1978,5,(3), pp. 19-27

6 BUCHNER, J.B.: 'Ternary line signal codes', Philips Telecommun. Rev.,1976,34,(2), pp. 72-86

7 GAME, C, and JESSOP, A.: 'Random coding for digital opticalsystems'. IEE Conf. Publ. 132, 1975, pp. 171-173

8 BETTS, M.C., GRAVES, A.F., PASCOE, F.M., and DILLEY, J.E.:'Method and apparatus for code conversion of binary to multilevelsignals', Canadian Patent 1,153,118, August 30, 1983

9 PRYSTAJECKY, A.: 'A study of the \6B9Q line code for multimodeoptical fiber communications' M.Sc. thesis, University of Alberta, 1985

Ann H. Prystajecky was born in Edmon-ton, Alberta, Canada, in 1961. She receivedthe B.Sc. degree in electrical engineering(with distinction) in 1983 and the M.Sc. inelectrical engineering in 1985, both fromthe University of Alberta. She received apost graduate award from the Natural Sci-ences and Engineering Research Council ofCanada to assist in her post graduateresearch. She has wide research interests,including line coding in optical fibre com-

munications and high-speed digital circuitry. Currently, she isworking with Transport Canada as a design engineer.

Paul A. Goud was born in the Hague, theNetherlands. He received the B.Sc. degreein electrical engineering (with distinction)from the University of Alberta, Edmonton,Alberta, Canada in 1959, and the M.A.Sc.and Ph.D. degrees in electrical engineeringfrom the University of British Columbia,Vancouver, Canada in 1961 and 1964respectively. From 1965 to 1966, he waswith Bell-Northern Research Ltd., Ottawa,Canada. Since 1966, he has been with the

University of Alberta, holding the rank of Professor of ElectricalEngineering since 1972. During leaves from the University ofAlberta, he has been at Bell Telephone Laboratories, Allentown,PA in 1969, at Philips Research Laboratories, Eindhoven, theNetherlands, in 1973-1974 and the University Paraiba, CampinaGrande, Brazil, in 1976-1977. The latter leave was on assignmentto CIDA (Canadian International Development Agency) as anexpert in microwave telecommunications. His current research isin the area of coding and modulation for optical fibre communi-cations.

Colin G. Englefield was born in London,United Kingdom, in 1935. He obtained theB.Sc. degree in electrical engineering fromQueen Mary College, University ofLondon, in 1957, and the Ph.D. degree,specialising in microwave engineering, in1961. From 1959 to 1964, he was aResearch Associate at the University ofBritish Columbia, Vancouver, Canada,working on travelling wave tubes andlinear accelerators. Since 1964 he has been

with the Department of Electrical Engineering at the Universityof Alberta, Edmonton, Canada. He has conducted research intomicrowave solid state devices and microwave amplifiers andoscillators. His present research interests include communicationtheory and coding techniques, particularly with regard to opticalfibre communications systems.

IEE PROCEEDINGS, Vol. 133, Pt. G, No. 2, APRIL 1986 117