High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Designs. Vishal Saxena Department of Electrical and Computer Engineering Boise State University 1910 University Dr., MEC 108 Boise, ID 83725 [email protected] and [email protected] Abstract : - PowerPoint PPT Presentation
Baker/Saxena High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Designs Vishal Saxena tment of Electrical and Computer Engineering Boise State University 1910 University Dr., MEC 108 Boise, ID 83725 [email protected] and [email protected]chnology continues to evolve, the supply voltages ing while at the same time the transistor voltages are remaining relatively aking matters worse, the inherent gain available nano-CMOS transistors is dropping. Traditional for achieving high gain by vertically stacking oding) transistors becomes less useful in sub- esses. Horizontal cascading (multi-stage) must be rder to realize op-amps in low supply voltage This seminar discusses new design techniques for ation of multi-stage op-amps. Both single- and rential op-amps are presented where low l VDD, and high speed are important. The and experimentally verified, op-amps exhibit improvements in speed over the traditional op- s while at the same time having smaller layout
Transcript
Baker/Saxena
High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Designs
The Operational Amplifier (op-amp) is a fundamental building block in Mixed Signal design. Employed profusely in data converters, filters, sensors, drivers etc.
Continued scaling in CMOS technology has been challenging the established paradigms for op-amp design.
With downscaling in channel length (L) Transition frequency increases (more speed). Open-loop gain reduces (lower gains). Supply voltage is scaled down (lower headroom) [1].
Baker/Saxena
CMOS Scaling Trends
VDD is scaling down but VTHN is almost constant. Design headroom is shrinking faster.
Transistor open-loop gain is dropping (~10’s in nano-CMOS) Results in lower op-amp open-loop gain. But we need gain!
Random offsets due to device mismatches.
[3], [4].
Baker/Saxena
Integration of Analog into Nano-CMOS?
Design low-VDD op-amps. Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
Explore more effective op-amp compensation techniques. Offset tolerant designs. Also minimize power and layout area to keep up with the
digital trend. Better power supply noise rejection (PSRR).
Baker/Saxena
Cascoding vs Cascading in Op-amps
A T
eles
copi
c T
wo-
stag
e O
p-am
p
A C
asca
de o
f lo
w-V
DD
A
mpl
ifier
Blo
cks.
(Com
pens
atio
n no
t sh
ow
n he
re)
1
VDD VDD
Vbiasn
vp vm
VDD
CL
vout
2
VDD VDD
Vbiasn
VDD VDD
Vbiasn
n-1
n
Stage 1 Stage 2 Stage (n-1) Stage n
VD
Dm
in>
4Vov
n+V
ovp+
VT
HP
with
w
ide-
swin
g bi
asin
g. [1
]
VD
Dm
in=
2Vov
n+V
ovp+
VT
HP
.
Even if we employ wide-swing biasing for low-voltage designs, three- or higher stage op-amps will be indispensable in realizing large open-loop DC gain.
Baker/Saxena
TWO-STAGE OP-AMP COMPENSATION
Baker/Saxena
Direct (or Miller) Compensation
1
2
vm v p vout
Vbias4
Vbias3
CC10pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD VDD
30pF
CL
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
750Ω
iC fb
iC ff
Compensation capacitor (Cc) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation.
An RHP zero exists at Due to feed-forward component of
the compensation current (iC).
The second pole is located at The unity-gain frequency is
A
ll th
e o
p-a
mp
s p
rese
nte
d h
ave
be
en
de
sig
ne
d in
AM
I C
5N
0.5
μm
CM
OS
pro
cess
with
sca
le=
0.3
μm
an
d L
min=
2.
Th
e o
p-a
mp
s d
rive
a 3
0p
F o
ff-c
hip
loa
d o
ffe
red
by
the
te
st-s
etu
p.
Baker/Saxena
Drawbacks of Direct (Miller) Compensation
The RHP zero decreases phase margin Requires large CC for
compensation (10pF here for a 30pF load!).
Slow-speed for a given load, CL.
Poor PSRR Supply noise feeds to the output
through CC.
Large layout size.
1
2
vm v p vout
Vbias4
Vbias3
CC
10pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD VDD
30pF
CL
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
Baker/Saxena
Indirect Compensation
The RHP zero can be eliminated by blocking the feed-forward compensation current component by using A common gate stage, A voltage buffer, Common gate “embedded” in the
cascode diff-amp, or A current mirror buffer.
Now, the compensation current is fed-back from the output to node-1 indirectly through a low-Z node-A.
Since node-1 is not loaded by CC, this results in higher unity-gain frequency (fun).
An
indi
rect
-com
pens
ated
op-
amp
usin
g a
com
mon
-gat
e st
age.
1
2
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD VDD
30pF
220/2
100/2
100/2
x10
VDD
Vbias3
Vbias4
vm
vp
voutCc
CL
ic
MCGA
M3 M4
M1
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
M2
M9
M10T
M10B
Baker/Saxena
Indirect Compensation in a Cascoded Op-amp
1
2
vm v p voutCC
1.5pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 44/2.
VDD VDD
VDD
30pF
CL
Vbias2
Vbias3
Vbias4
A
50/2
50/2
110/2
M1 M2
M6TL
M6BL
M6TR
M6BR
M3T
M3B
M4T
M4B
M8T
M8B
M7
ic
Indi
rect
-com
pens
atio
n us
ing
casc
oded
cur
rent
mir
ror
load
.1
2vm v p
voutCC
1.5pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
CL
Vbias3
Vbias4
A
100/2
100/2
220/2
M1B M2B
M5T
M5B
M3
M1T
M4
M2T
M8T
M8B
M7
VDD
M4Vbias1
30/2
30/2
10/10
ic
Indi
rect
-com
pens
atio
n us
ing
casc
oded
dif
f-pa
ir.
Employing the common gate device “embedded” in the cascode structure for indirect compensation avoids a separate buffer stage. Lower power consumption. Also voltage buffer reduces the swing which is avoided here.
Baker/Saxena
Analytical Modeling of Indirect Compensation
A1 A2
Cc
1 2
vin vout
DifferentialAmplifier
Gain Stage
RcA
ic
Blo
ck D
iagr
amS
mal
l sig
nal a
naly
tica
l mod
el
RC is
the
resi
stan
ce
atta
ched
to n
ode-
A.ic
voutsCc Rc
1
+
-
+
-
1 2
gm1vs gm2v1R1 C1 R2 C2 vout
Cc
Rc
The
com
pens
atio
n cu
rren
t (i C
) is
indi
rect
ly
fed-
back
to n
ode-
1.
Baker/Saxena
Analytical Results for Indirect Compensationj
z1
un
p1p2p3P
ole-
zero
plo
t
Pole p2 is much farther away from fun. Can use smaller gm2=>less power!
LHP zero improves phase margin. Much faster op-amp with lower
power and smaller CC.
Better slew rate as CC is smaller.
LH
P z
ero
Baker/Saxena
Indirect Compensation Using Split-Length Devices
As VDD scales down, cascoding is becoming tough. Then how to realize indirect compensation as we have no low-Z node available?
Solution: Employ split-length devices to create a low-Z node. Creates a pseudo-cascode stack but its really a single device.
In the NMOS case, the lower device is always in triode hence node-A is a low-Z node. Similarly for the PMOS, node-A is low-Z.
A
VDD M1T
W/L1
M1BW/L2
M1
W/(L1+L2)Equivalent
M1T
W/L1
M1BW/L2
M1
W/(L1+L2)
VDD
Triode
Triode
Low-Z node
Low-Z node
Equivalent
A
NM
OS
PM
OS
Spl
it-l
engt
h 44
/4(=
22/2
) P
MO
S la
yout
S
D
A
Low-Z node
G
Baker/Saxena
Split-Length Current Mirror Load (SLCL) Op-amp
1
2
vm v p vout
Vbias4
Vbias3
CC
2pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
CL
M3B M4B
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7T
M3T M4T
M7B
50/2
50/2
220/2
220/2
Aic
funz1
p2,3
The current mirror load devices are split-length to create low-Z node-A.
Here, fun=20MHz, PM=75° and ts=60ns.
ts
Fre
quen
cy R
espo
nse
Sm
all s
tep-
inpu
t set
tlin
g in
fol
low
er
conf
igur
atio
n
Baker/Saxena
SLCL Op-amp Analysis
12
vout
A
1
gmp
id1id2vs2
1
gmp
gm vs12
+-
vs2
CL
Cc
v=0
12
vout
A
1
gmp
id1
vs2
CL
Cc
g
gv
m
mps
1
(a) (b)
+
-
+
-
1 2
gm2v1R1 C1
vout
Cc
v1
rop
CA
+
-
vsgA
C2R2
A
g
gv
m
mps
1
1
gmpgmpvsgA
ic
vout
sCc gmp
1 1
+
-
+
-
1 2
gm2v1R1 C1
vout
Cc
v1
C2R2ic
gm vs1 1
gmp
gm vs12
1
gmp
Here fz1=3.77fun
LHP zero appears at a higher frequency than fun.
Baker/Saxena
Split-Length Diff-Pair (SLDP) Op-amp
The diff-pair devices are split-length to create low-Z node-A.
Here, fun=35MHz, PM=62°, ts=75ns.
Better PSRR due to isolation of node-A from the supply rails.
Fre
quen
cy R
espo
nse
Sm
all s
tep-
inpu
t set
tlin
g in
fol
low
er
conf
igur
atio
n
1
2
vm v pvout
Vbias4
Vbias3
CC
2pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD VDD
30pF
CL
M3 M4
M1B M2B
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
M1T M2T
20/2
20/2
20/2
20/2
ic
110/2
50/2
50/2
Afun
p2,3
z1
ts
Baker/Saxena
SLDP Op-amp Analysis
12
vout
A
id1id2
vs2
vs2
CL
Cc
v=0
1
gmn
1
gmn
12
vout
A
id2vs2
CL
Cc1
gmn
rop
(a) (b)
id
gmnvs2 4
Here fz1=0.94fun, LHP zero appears slightly before fun
and flattens the magnitude response. This may degrade the phase margin.
Not as good as SLCL, but is of great utility in multi-stage op-amp design due to higher PSRR.
+
-
+
-
1 2
gm2v1CA
voutvA
ron
C1
+
-vgs1
C2R2
A
gmnvgs1
vs2
1
gmnR1gmnvs
4
Cc
1
gmn
ic
vout
sCc gmn
1 1
+
-
+
-
1 2
gm2v1R1 C1
vout
Cc
v1
C2R2ic
gmnvs2 1
gmn
Baker/Saxena
Test Chip 1: Two-stage Op-amps
Miller 3-Stage Indirect
SLCL Indirect
SLDP Indirect
Miller with Rz
AMI C5N 0.5μm CMOS, 1.5mmX1.5mm die size.
Baker/Saxena
Test Results and Performance Comparison
vin
vout
vin
vout
vin
vout
Mil
ler
wit
h R
z (t
s=25
0ns)
SL
CL
Ind
irec
t (t s=
60ns
)S
LD
P I
ndir
ect (
t s=75
ns)
Perf
orm
ance
com
pari
son
of th
e op
-am
ps f
or C
L=
30pF
.
10X gain bandwidth (fun).
4X faster settling time. 55% smaller layout area. 40% less power consumption.
Baker/Saxena
MULTI-STAGE OP-AMP DESIGN
Baker/Saxena
Three-Stage Op-amps
Higher gain can be achieved by cascading three gain stages. ~100dB in 0.5μm CMOS
Results in at least a third order system 3 poles and two zeros. RHP zero(s) degrade the phase
margin. Hard to compensate and stabilize. Large power consumption compared
to the two-stage op-amps.
zLHP
s plane
j
p1p2,3
zRHP
un
Clustered non-dominant poles
Pol
e-ze
ro p
lot
Baker/Saxena
Biasing of Multi-Stage Op-amps
1
VDD VDD
Vbiasn
vp vm
~Vbiasp
Vbiasp
M1 M2
M3L M3R
M4 M5
3
VDD
CL
vout
M12
M11
2
VDD VDD
Vbiasn
~Vbiasp Vbiasp
M6 M7
M8L M8R
M9 M10Current flowing in this branch is set
by Vbiasp.
Diff-amps should be employed in inner gain stages to properly bias second and third gain stages Current in third stage is
precisely set. Robust against large offsets. Boosts the CMRR of the op-
amp (needed). Common source second stage
should be avoided. Will work in feedback
configuration but will have offsets in nano-CMOS processes.
1
VDD VDD VDD
Vbiasn
vp vm
2
~Vbiasp
Vbiasp
Unknown Voltage level, can move up or down.
M1 M2
M3L M3R
M4 M5
M6
M7
3
VDD
CL
vout
Current in this branch is unknownM8
M9
Rob
ust B
iasi
ngF
alli
ble
Bia
sing
Baker/Saxena
Conventional Three-Stage Topologies
1
2
VDD VDD VDD VDD VDD VDD
CL
vm vp voutCc1
Cc2
Rc
VB1
VB2
VB4
VB5
VB3gm1
gm2
gm3
3
40uA
10uA 10uA
10uA
10uA
100uA
100pF
Requires p3=2p2=4ωun for stability (Butterworth response) Huge power consumption
RHP zero appears before the LHP zero and degrades the phase margin.
Second stage is non-inverting Implemented using a current
mirror. Excess forward path delay (not
modeled or discussed in the literature).
-A1 +A2
Cc1
1 2
vs vout -A3
3
Cc2
Nes
ted
Mil
ler
Com
pens
atio
n (N
MC
) [6
]
Baker/Saxena
Conventional Three-Stage Topologies contd.
gm1 +gm2
Cc1
1vs vout -gm3
Cc2
2 3
-gmf1
-gmf2
Employs feed-forward gm’s to eliminate zeros. gmf1=gm1 and gmf2=gm2
Class AB output stage. Hard to implement gmf1 which
tracks gm1 for large signal swings. Also wasteful of power.
gmf2 is a power device and will not always be equal to gm2. Compensation breaks down.
Still consumes large power.
Nes
ted
Gm
-C C
ompe
nsat
ion
(NG
CC
) [7
]
1
2
3
VDD
vm vpgm1
VDD VDD VDD
VDD
VB1
VDD
20uA
Cc1
VB2
CL
voutCc2
gm2gmf1
gm3
gmf224/3
60/3
120/3 180/3120/3
24/3 24/3
48/3
48/3
120/3
48/3
420/3
24/3
20uA 70uA
Baker/Saxena
Conventional Three-Stage Topologies contd.
Four poles and double LHP zeros One LHP zero z1 cancels the pole p3.
Other LHP zero z2 enhances phase margin.
Set p2=2ωun for PM=60°.
Relatively low power. Still design criterions are complex. Complicated bias circuit.
More power. Excess forward path delay.
Tra
nsco
nduc
tanc
e w
ith C
apac
itive
F
eedb
ack
Com
pens
atio
n (T
CF
C)
[14]
1
2
VDD VDD VDD VDD VDD VDD
vm vp
vout
CC2
VB1
VB3
VB7
VB2gm1
gm3
3
gm2/2gmf
VB4
VB5
1:2
VB6
gmt
CC1
-A1 +A21 2
vs vout -A3
3
CC2
-gmf
+gmt
CC1
Baker/Saxena
Three-Stage Topologies: Latest in the literature
Employs reverse nesting of compensation capacitors Since output is only loaded by only
CC2, results in potentially higher fun.
Third stage is always non-inverting. Uses pole-zero cancellation to realize
higher phase margins. Excess forward path delay. Biasing not robust against process
variations. How do you control the current in the output buffer?
Rev
erse
Nes
ted
Mill
er w
ith V
olta
ge B
uffe
r an
d R
esis
tanc
e (R
NM
C-V
BR
) [8
] -A1 -A2
Cc1
1 2
vs vout +A3
3
Cc2
Rc2
Rc1
CG
1
VDD
vm vp
gm1
VDD
20uA
2
3
VDD VDD VDD VDD
vout
CL
Cc1
Cc2
gm2
gm3
gmf
gmVB
RC1
Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.
Reversed nested with elimination of RHP zero. High gain block (HGB) realizes gain
by cascading stages. High speed block (HSB) implements
compensation at high frequencies. Complex design criterions. Excess forward path delay. Again,
uses a non-inverting gain stage. Employs a complicated bias circuit.
More power consumption.
Act
ive
Fee
dbac
k F
requ
ency
C
ompe
nsat
ion
(AF
FC
) [9
] -A1 +A2
Ca
1 2
vs vout -A3
3
Cm
-gmf
+gma
High-Gain Block (HGB)
High-Speed Block (HSB)
Input Block
1
2
VDD VDD VDD VDD VDD VDD
vm vp
voutCm
VB
VB2
VB5
VB1gm1
gm3
3
gm2 gmf
VDD
VB1
VB4
Ca
gma
HGB HSB
Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.
Various topologies have been recently reported by combining the earlier techniques. RNMC feed-forward with nulling resistor (RNMCFNR) [17]. Reverse active feedback frequency compensation (RAFFC) [17].
Further improvements are required in Eliminating excess forward path delay arising due to the compulsory non-
inverting stages. Robust biasing against random offsets in nano-CMOS. Further reduction in power and circuit complexity. Better PSRR.
Baker/Saxena
Indirect Compensation in Three-Stage Op-amps
Indirectly feedback the compensation currents ic1 and ic2. Reversed Nested
Thus named RNIC.
Employ diff-amp stages for robust biasing and higher CMRR.
Use SLDP for higher PSRR. Minimum forward path delay. No compulsion on the polarity of gain
stages. Can realize any permutation of stage
polarities by just changing the sign of the fed-back compensation current using ‘fbr’ and ‘fbl’ nodes.
Low-voltage design. Note Class A (we’ll modify after
theory is discussed).
-A1 +A2
Cc1
1 2
vs voutic1
-A33
Cc2
ic2
-+
VDD VDD
VDD
Vbiasn
vpfbl fbr
Cc2
CL
vm
VDD VDD
voutCc1
fbl
fbr
+ve
-ve
ic1
ic2
1
2
3
Baker/Saxena
Indirect Compensation in Three-Stage Op-amps contd.
VDD VDD
VDD
Vbiasn
vpfbl fbr
Cc2
CL
vm
VDD VDD
voutCc1
fbl
fbr
+ve
-ve
ic1
ic2
1
2
3
Note the red arrows showing the node movements and the signs of the compensation currents. fbr and fbl are the low-Z nodes used for indirect compensation (have
resistances Rc1 and Rc2 attached to them). The CC’s are connected across two-nodes which move in opposite direction
for overall negative feedback the compensation loops. Note feedback and forward delays!
Baker/Saxena
Analysis of the Indirect Compensated 3-Stage Op-amp
iv
sCc Rcc
1
2
1 11
+
-
+
-
1 2
gm1vs gm2v1R1 C1 R2
C2v2
Cc1
Rc1
v1
+
-
3
gm3v2 R3
C3 vout
Cc2
Rc2
iv
sC Rc
out
c c2
2 21
ic1 ic2
Tw
o L
HP
zero
s
Four
non
-dom
inan
t pol
es.
Plug in the indirect compensation model developed for the two-stage op-amps.
Baker/Saxena
Pole-zero Cancellation Poles p4,5 are parasitic conjugated poles located far away in frequency.
Appear due to the loading of the nodes fbr and fbl.
The small signal transfer function can be written as
The quadratic expression in the denominator describing the poles p2 and p3 can be canceled by the numerator which describes the LHP zeros.
Results in LHP zeros z1 and z2 canceling the poles p2 and p3 resp.
The resulting expression looks like a single pole system for low frequencies. →Phase margin close to 90°.
Baker/Saxena
Pole-zero Cancellation contd.
s plane
j
p1
p2,z1 un
p3,z2
Non-dominant pole zero doublets
p4,5
Des
ign
Equ
atio
ns
Place pole-zero doublets (p2-z1 and p3-z2) out of fun for clean transients. i.e. fp2, fp3 > fun.
Best possible pole-zero arrangement for low power design.
Results into design equations independent of parasitics (C3≈CL here).
Rc1 and Rc2 are realized by adding poly R’s in series with CC1 and CC2. Also Rc1, Rc2≥Rc0, the impedance
attached to the low-Z nodes fbr/fbl. Robust against even 50% process
variations in R’s and C’s as long as the pole-zero doublets stay out of fun.
Baker/Saxena
Pole-zero cancelled Class-A Op-amp
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
220/2
100/2
CL
vm
VDD VDD
vout
1
2
3
M4 M5
M1T
M1B
M2T
M2B
M3L M3R M7L M7R
M8 M9
M5 M6
M10
M11
Cc2
fbrR2c
Cc1
fblR1c
30/2 30/2
7.65K
4.08K
1p
2p
A Here, the poly resistors are estimated as
Low power, simple, robust and manufacturable topology*. The presented three-stage op-amps have been designed with transient and SR performances to
be comparable to their two-stage counterparts.
Baker/Saxena
Pole-zero cancelled Class-AB Op-amp 1
A dual-gain path, low-power Class-AB op-amp topology (RNIC-1).
The design equation for Rc1 is modified as
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
220/2
100/2
Cc2 CL
vm
VDD VDD
vout
Cc1
fblfbr
1
2
3
M4 M5
M1T
M1B
M2T
M2B
M3L M3R M7L M7R
M8 M9
M5 M6
M10
M11
R1cR2c
Vbiasp
66/2 66/2
124 1p2p1.14K
Baker/Saxena
Pole-zero cancelled Class-AB Op-amp 2
A single-gain path, Class-AB op-amp topology for good THD performance. Floating current source for biasing the output buffer. Here, Vncas= 2VGS and Vpcas=VDD 2VSG. Note the lack of gratuitous forward delay.
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
220/2
100/2
CL
vm
VDD VDD
vout
1
2
3
M4 M5
M1T
M1B
M2T
M2B
M3L M3R M7L M7R
M8 M9
M5 M6
M10
M11
Vbiasp
66/2 66/2
Vbiasn
VDD
Vpcas
Vncas
10/2
11/2
MFCP
MFCNCc1
fblR1c
Cc2
fbrR2c
7.65K
4.08K
1p
2p
Baker/Saxena
Simulation of Three-stage Op-amps
-150
-100
-50
0
50
100
Mag
nitu
de (
dB
)
102
104
106
108
1010
-225
-180
-135
-90
-45
0
Phase
(deg)
Bode Diagram
Frequency (Hz)
Analytical model of the Class-AB (RNIC-1) topology is simulated in MATLAB.
The pole-zero plot illustrates the double pole-zero cancelation (collocation). p4 and p5 are parasitic poles located at frequencies close to that of the fT limited
(or mirror) poles.
Here, fun≈30MHz and PM=90° for CL=30pF.
Baker/Saxena
Simulation of Three-stage Op-amps contd.
SPICE simulation of the same Class AB op-amp. CL=30pF: fun=30MHz, PM≈88°, ts=70ns, 0.84mW, SR=20V/μs.
As fast as a two-stage op-amp with only 20% more power, at 50% VDD and with the same layout area (simpler bias circuit).
Operates at VDD as low as 1.25V in a 5V process (25% of VDD).
SPICE simulation match with the MATLAB simulation Our theory for three-stage indirect compensation is validated.
Baker/Saxena
Chip 2: Low-VDD 3-Stage Op-amps
PZC Class AB CL=30pF
PZC Class A CL=30pF
Class A CL=30pF
PZC Class AB Dual gain path
CL=500pF
PZC Class AB Single gain path
CL=500pF
PZC High Performance
Class AB CL=500pF
Bes
t Pe
rfor
man
ce
A
MI
C5N
0.5
μm C
MO
S, 1
.5m
mX
1.5m
m d
ie s
ize.
Baker/Saxena
Performance Comparison
Figures of Merit FoMS=funCL/Power
FoML=SR.CL/Power
IFoMS=funCL/IDD
IFoML=SR.CL/IDD
RNIC op-amp designed for 500pF load for a fair comparison.
FoMs>2X than state-of-the-art at VDD=3V.
Comparable performance even at lower VDD=2V.
Practical, stable and production worthy.
Baker/Saxena
Performance Comparison contd.
0
10000
20000
30000
40000
50000
60000
MNM
C
NGCC
NMCFNR
DFCFC
AFFC
ACBCF
TCFC
DPZCF
RNMC V
B NR
SMFF
C
RNMCFNR
RAFFC
RAFFC LP
RNIC-2
(Thi
s wor
k)
RNIC-3
(Thi
s wor
k)
RNIC-2
A (This
wor
k)
RNIC-3
A (This
wor
k)
FOM_S
FOM_L
IFOM_S
IFOM_L
Higher performance figures than state-of-the-art.
10X faster settling. Better phase margins. Layout area same or smaller.
Baker/Saxena
Flowchart for RNIC Op-amp DesignStart with the initial
specifications on fun, CL, Av, and SR.
Select the overdrive (% of VDD) which will set VGS, fT and transistor gain gm*ro.
Identify gm1. Can initially set gm2 equal to gm1 or a to lower value.
Select Cc2 = gm1/fun
Select Cc1 and gm3 such that the p2-z1 and p3-z2 doublet locations are outside fun.
Calculate R1c and R2c.
Is either of R1c and R2c negative?
Are the parasitic poles p4,5 degrading
PM by closing on fun?
Simulate the design for frequency response
and transient settling.
Does the design meet the
specifications?
No
Lower power?
Smaller layout area?
More Speed?
Better SR?
Split DC gain AOLDC across A1, A2 and A3.
Move the corresponding p i-zj doublet to a lower frequency by changing Cci and Rci. May
have to sacrifice fun.
Yes
End
Yes
Increase gm1 or decrease Cc2.
Yes
No
Decrease gm3 or gm2. In the worst case
scenario decrease gm1.
Yes
No
Reduce Cc1, Cc2 or gm3.
Yes
No
Increase bias current in the first stage (i.e. ISS1) or use
smaller CC’sYesNothing works!
Revisit biasing.No
Increase gm2.Yes
No
No
Baker/Saxena
N-Stage Indirect Compensation Theory
A1 -A21 2
vs vout -A3
3+
- -An-1 -An
n-1 n
Cc1
Cc2
Ccn 2
Ccn 1
ic1
ic2
icn 1icn 2
The three-stage indirect compensation theory has been extended to N-stages and the closed form small signal transfer function is obtained.
Baker/Saxena
MULTI-STAGE FULLY-DIFFERENTIAL OP-AMPS
Baker/Saxena
Fully Differential Op-amps
Analog signal processing uses ‘only’ fully differential (FD) circuits. Cancels switch non-linearities and even
order harmonics. Double the dynamic range.
Needs additional circuitry to maintain the output common-mode level. Common-mode feedback circuit
(CMFB) is employed.
CMFB
Vref
VCMFB
CL
CLvinm
vinp
vop
vom
v op-
v om=
-A(v
inp-
v inm
)
Baker/Saxena
Three-Stage FD Op-amp Design: Problems
-A1 +A2
Cc1
vp vop -A3
Cc2
-+ 1p 2p 3p
-A1 +A2
Cc1
vm vom -A3
Cc2
-
+1m 2m 3m
CM
FB vCM
The CMFB loop disturbs the DC biasing of the intermediate gain stages. Degrades the gain, performance and may cause instability.
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
vm
VDD
20/2
20/2
VCM
vop1vom1
VCMFB1
VDD
vomCc2
fblR2c
110/2
100/2
50/2
VCMFB3
VDD
VDD
vopCc2
fbrR2c
110/2
100/2
50/2
VDD
VCM
30K
100f
30K
100f
vom
vop
VCM
VCMFB1
vop2vom2
First Stage Second Stage
Output Buffer(Third Stage)
100/2 100/2
Cc1
VDD VDD
Vbiasn
VDD
vop2vom2 R1cfbr fbl
R1c
vop1 vom1 Vbiasp
Cc1
VDD
Blo
ck D
iagr
am
Cir
cuit
Im
plem
enta
tion
Baker/Saxena
Three-Stage FD Op-amp Design: Solutions
-A1 +A2
Cc1
vp vop -A3
Cc2
-+ 1p 2p 3p
-A1 +A2
Cc1
vm vom -A3
Cc2
-
+1m 2m 3m
CM
FB
vCM
CM
FB vbiasn
CM
FB vbiasp
v CM
FB
1
v CM
FB
2
v CM
FB
3
-A1 +A2
Cc1
vp vop -A3
Cc2
-+ 1p 2p 3p
-A1 +A2
Cc1
vm vom -A3
Cc2
-
+1m 2m 3m
CM
FB vCM
vCMFB
-A1 +A2
Cc1
vp vop -A3
Cc2
-+ 1p 2p 3p
-A1 +A2
Cc1
vm vom -A3
Cc2
-
+1m 2m 3m
CM
FB vCM
vCMFB
Employ CMFB 1. Individually across all the stages.
2. Only across the last two stages as the biasing of the output buffer need not be precise.
3. Only in the third stage (output buffer).
1.
2. 3.
Baker/Saxena
Three-Stage FD Op-amp Design
VDD VDD
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
vm
VDD
20/2
20/2
VCM
vop1vom1
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
30K
100f
30K
100f
vom
vop
VCM
VCMFB3
VDD VDD
Vbiasn
vop2
VDD VDD
Vbiasn
vom2Cc1
fblR1c
Cc1
fbrR1c
First Gain Stage
Second Gain Stage
VDD
vomCc2
fblR2c
110/2
100/2
50/2
VCMFB3
VDD
VDD
vopCc2
fbrR2c
110/2
100/2
50/2
VDD
VCM
vop2vom2
Output Buffer(Third Stage)
100/2 100/2
Use CMFB only in the output (third) stage. → Manufacturable design. Leaves the biasing of second and third stage alone without disturbing them.
Employ diff-amp pairs in the second stage for robust biasing.
-A1 +A2
Cc1
vp vop -A3
Cc2
-+ 1p 2p 3p
-A1 +A2
Cc1
vm vom -A3
Cc2
-
+1m 2m 3m
CM
FB vCM
vCMFB
Blo
ck D
iagr
am
Cir
cuit
Im
plem
enta
tion
Baker/Saxena
Three-Stage FD Op-amp: Enlarged
VDD VDD
20/2
20/2
20/2
20/2
Vbiasn
vpfbl fbr
vm
VDD
20/2
20/2
VCM
vop1vom1
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
30K
100f
30K
100f
vom
vop
VCMFB3
VDD VDD
Vbiasn
vop2
VDD VDD
Vbiasn
vom2Cc1
fblR1c
Cc1
fbrR1c
First Gain Stage
Second Gain Stage
VDD
vomCc2
fblR2c
110/2
100/2
50/2
VCMFB3
VDD
VDD
vopCc2
fbrR2c
110/2
100/2
50/2
VDD
VCM
vop2vom2
Output Buffer(Third Stage)
100/2 100/2
VDD
Vbiasp
VCM
Baker/Saxena
Chip 3: Low-VDD FD Op-amps
2-stage CL=30pFCMFB across all
the stages.
2-stage CL=30pFCMFB across the
output stage.
3-stage CL=30pFCMFB across the
output stage.
3-stage CL=30pFDiffamp pair for biasing
CMFB across the output stage.
3-stage CL=500pFDiffamp pair for biasing
CMFB across the output stage.
Bes
t Pe
rfor
man
ce
A
MI
C5N
0.5
μm C
MO
S, 1
.5m
mX
1.5m
m d
ie s
ize.
Baker/Saxena
Simulation and Performance Comparison
DC
beh
avio
r
Tra
nsie
nt r
espo
nse
82dB
gai
n
t s=27
5ns
>2.5X figure of merit (FoM).
Baker/Saxena
Flowchart for Three-Stage FD Op-amp DesignStart with the initial
specifications on fun, CL, Av, and SR.
Does the design meet specifications?
End
Yes
Design a singly-ended pole-zero cancelled three-stage op-amp for the given
specifications.
Add a CMFB circuit in the output buffer.
Convert the singly-ended op-amp into a fully differential one by mirroring it. Use a pair of
diff-pairs for the second stage for robust biasing.
Simulate the design.
No
Update the value of gm3 corresponding to the output buffer and recalculate R1C and R2C.
Baker/Saxena
Conclusions
Indirect compensation leads to significantly faster, lower power op-amps with smaller layout area.
Indirect compensation using split-length devices facilitates low-VDD op-amp design.
Novel pole-zero canceled three-stage RNIC op-amps exhibit substantial improvement over the state-of-the-art.
A theory for multi-stage op-amps is presented. New methodologies for designing multi-stage FD op-amps proposed which
improve the state-of-the-art. All proposed op-amps are low voltage
Open new avenues for low-VDD mixed signal system design.
Baker/Saxena
Future Scope
Mathematical optimization of PZC op-amps. Design of low-VDD systems in nano-CMOS process
Pipelined and Delta-Sigma data converters, Analog filters, Audio drivers, etc.
Further investigation into indirect-compensated op-amps for n≥4 stages.
Baker/Saxena
References
[1] Baker, R.J., “CMOS: Circuit Design, Layout, and Simulation,” 2nd Ed., Wiley Interscience, 2005. [2] Saxena, V., “Indirect Compensation Techniques for Multi-Stage Operational Amplifiers,” M.S. Thesis, ECE Dept., Boise
State University, Oct 2007.[3] The International Technology Roadmap for Semiconductors (ITRS), 2006 [Online]. Available:
http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm[4] Zhao, W., Cao, Yu, "New Generation of Predictive Technology Model for sub-45nm Design Exploration" [Online].
Available: http://www.eas.asu.edu/~ptm/[5] Slide courtesy: bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/ASPDACJanuary05.pdf [6] Leung, K.N., Mok, P.K.T., "Analysis of Multistage Amplifier-Frequency Compensation," IEEE Transactions on Circuits
and Systems I, Fundamental Theory and Applications, vol. 48, no. 9, Sep 2001. [7] You, F., Embabi, S.H.K., Sanchez-Sinencio, E., "Multistage Amplifier Topologies with Nested Gm-C Compensation,"
IEEE Journal of Solid State Circuits, vol.32, no.12, Dec 1997.[8] Grasso, A.D., Marano, D., Palumbo, G., Pennisi, S., "Improved Reversed Nested Miller Frequency Compensation
Technique with Voltage Buffer and Resistor," IEEE Transactions on Circuits and Systems-II, Express Briefs, vol.54, no.5, May 2007.
[9] Lee, H., Mok, P.K.T., "Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient Improvement," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol.51, no.9, Sep 2004.
[10] Eschauzier, R.G.H., Huijsing, J.H., "A 100-MHz 100-dB operational amplifier with multipath Nested Miller compensation," IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
[11] Leung, K. N., Mok, P. K. T., "Nested Miller compensation in low-power CMOS design," IEEE Transaction on Circuits and Systems II, Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001.
[12] Leung, K. N., Mok, P. K. T., Ki, W. H., Sin, J. K. O., "Three-stage large capacitive load amplifier with damping factor control frequency compensation," IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.
Baker/Saxena
References contd.
[13] Peng, X., Sansen, W., "AC boosting compensation scheme for low-power multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
[14] Peng, X., Sansen, W., "Transconductances with capacitances feedback compensation for multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 7, pp. 1515-1520, July 2005.
[15] Ho, K.-P.,Chan, C.-F., Choy, C.-S., Pun, K.-P., "Reverse nested Miller Compensation with voltage buffer and nulling resistor," IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1735-1738, Oct 2003.
[16] Fan, X., Mishra, C., Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 3, pp. 584-592, March 2005.
[17] Grasso, A.D., Palumbo, G., Pennisi, S., "Advances in Reversed Nested Miller Compensation," IEEE Transactions on Circuits and Systems-I, Regular Papers, vol.54, no.7, July 2007.
[18] Shen, Meng-Hung et al., "A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensation," IEEE Asian Solid-State Circuits Conference, 2006, p 171-174.
