High-speed Serial Interface

Lect. 8: Linear Equalizers

Why equalization?• Inter-symbol interference (ISI) caused by frequency-

dependent loss of channel

TxDriver Channel Rx

RxEqualizer

Equalizer Frequency ResponseGain [dB]

Frequency (log)

0

fBW

-3

fBW,EQ

High-pass filter / High-frequency boosting

Continuous Time Linear Equalizer (CTLE)

CTLE Frequency ResponseAssuming channel has one pole, CTLE should provide 1 zero and 2 poles

Gain [dB]

Frequency (log)

ADC,EQ

fz fp1

AAC,EQ

fp2

High frequency boosting

Tunability• CTLE should be tunable

– Channel variation• Variations in channel fabrication • Uncertainty in channel modeling• Channel degradation/defect after usage

– PVT variation of equalizer

Tunability is a must

Tunability• Tuning pole/zero locations

Gain [dB]

Frequency (log)

TuningZero location

FixedADC,EQ

ControllingAAC,EQ

Controllability• Tuning DC gain

Gain [dB]

Frequency (log)

TuningDC gain

ControllingADC,EQ

FixedAAC,EQ

Passive CTLE– Various passive high-pass filters available

No power consumption

But - Lossy- PVT dependent- Difficult to achieve 50-ohm matching- Difficult to tune- Often large size

Active CTLE • Differential amplifier

– Basic differential amp. has 1 pole from load capacitance

| |~ //1

VDD

VSS

OUT-

IN+

OUT+

IN-

Ibias

Zload Zload

gm gm

Cload Cload

1

Active CTLE• Inductive load

– Shunt inductor providesa pole/zero pair

| |~ //1

VSS

OUT-

IN+

OUT+

IN-

Ibias

Rload Rload

gm gm

Cload Cload

Lload Lload

VDD

1

1

Source Degeneration for CTLE

| |~ ′ //1

1 2

//1

VDD

VSS

OUT-

IN+

OUT+

IN-

Ibias/2

Zload Zload

gm gm

Cload CloadIbias/2

Zdeg

Source Degeneration for CTLE– Capacitive generation provides high-frequency boosting since a

capacitor has lower impedance at high frequency

VDD

VSS

OUT-

IN+

OUT+

IN-

Ibias/2

Zload Zload

gm gm

Cload CloadIbias/2

Rdeg

Cdeg

1 2

//1

1

1 2 1

Design Exercise

Limitations of CTLE• Channels may not be properly modeled with one

poleGain [dB]

Frequency (log)

Additional zero

Additional pole

Limitations of CTLE

– Applicable to only ISIs due to linear frequency-dependent loss

– Other causes for ISI are;• Impedance mismatching• Cross-talk• Parasitic poles and zeros (ex: package parasitics)

Limitations of CTLE• High-frequency Noise boosting

Gain [dB]

White noise

Time-Domain Analysis– Frequency-Domain Analysis

• Freq. Response of Input x Freq. Response of Channel= Freq. Response of Output

– Time-Domain Analysis

x Equalizer

- Equalization: Force pre- and post-cursors to zero

FIR Filter

IIR (Infinite Impulse Response) for CTLE

FIR (Finite Impulse Response)

Tap and Delay

FIR Filter

- Difficult to implement Rx FIR filter

Tx FIR filter

Because the precise amount of delay (clock period) is not known in Rx

FIR Filter- Any CTLE filter can be converted into a discrete-time domain filter

- IIR (Infinite Impulse Response)

- Hard to implement Rx FIR filter because the precise amount of delay (clock period) is not available in Rx

Tx FIR filter

FIR (Finite Impulse Response)

Tap and Delay

Tx FIR

Frequency-Domain Analysis

Circuit implementation• Tx FIR can be easily implemented with current-mode drivers(For 2-tap Tx FIR)

– D1=D0 Vout,diff = +/- 100 x (C0 - C1)/4– D1≠D0 Vout,diff = +/- 100 x (C0 + C1)/4 – By setting C1/C0, Tx FIR is achieved

D1- D1+

C1

Positive channel

Negative channel 100Ω

VSS

D0+ D0-

C0

50Ω 50Ω

VDD

Main cursor 1st post-cursor

Pre-/De-Emphasis– Tx FIR is also called Feed-Forward Equalizer (FFE) or

Pre-/De-Emphasis • Pre-emphasis: to enhance high-frequency components• De-emphasis: to reduce low-frequency components

NormalWaveform

De-emphasisWaveform

Pre-emphasisWaveform

Nominalswing

Nominal swing

Nominalswing