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2003 2003 SWTWSWTW
High Throughput High Throughput Challenges for 300mm Challenges for 300mm
Wafer TestingWafer Testing
Clark Y.H. Liu PSCNobuhiro Kawamata FFIA
Ken Taoka TEL
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2003 2003 SWTWSWTW
Agenda
• Overview– Test Equipment Introduction
• 300mm Prober Challenges – Thermal and Probing Issue– SACC Cart
• TRE Probe Card challenges– Electrical Performance– Mechanical Performance
• Summary• Acknowledgement
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2003 2003 SWTWSWTW
Overview
DRAM mass productions are shifting toward 300mm. Reducing testing cost is the major concern of Test Engineering. PSC, FFI and TEL have cooperated to implement for 300 mm DRAM test.
Tester Resource Extension (TRE) probe card has doubled the tester parallel testing capacity to 128DUT/station testing.
In our paper, we will give an overview of the project to implement 128DUT wafer test at PSC.
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2003 2003 SWTWSWTW
Testing Equipment Introduction (1)
Advantest Tester T-5375
FFI Probe CardPH100 / 128DUT
TEL ProberP-12Xln
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2003 2003 SWTWSWTW
Testing Equipment Introduction (2)
TesterTesterDR : 2048 Pins / 64DCTU / Station I/O : 1280 Pins / 256PPS / Station
ProberProberPin to pad XY +/- 2um Pin to pad Z +/- 5umSACC CART
Probe cardProbe card128DUT TRE Probe InterfaceNumber of Probe > 6000PinsXY Positioning Accuracy < 20umProbe Head : PH100
TRE probe Interface has doubled parallel testing capacity from 64DUT to 128DUT/station testing.
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2003 2003 SWTWSWTW
Problem : Thermal Z-Deflection of Probe Card
Effect: Long Per-heat Time and Unstable Probe Mark
PCBTSS
WSSRing Ring
88ºC Chuck Temperature
~55ºC
88ºC-23ºC = Large thermal expansion
55ºC-23ºC =Small thermal expansion
NET DEFLECTION
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2003 2003 SWTWSWTW
Throughput Improvement & Stable Contact (1)
Z Contact Height (um)
Pre-heat Original Curve
Pre-heat Improved Curve
0 5 10 15 20 25 30 40 50 60 70 80 90 100 120Pre-Heat Time (min.)
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2003 2003 SWTWSWTW
Throughput Improvement & Stable Contact (2)
Effort 1 : New WSSEffort 2 : New P/C Card Holder ConceptEffort 3 : P/C Card Holder ControllingEffort 4 : New Pre-heat MethodEffort 5 : Throughput Improvement Sequence on ProberEffort 6 : N-Chip Alignment (Smart Soak)
Conclusion:• Pre-heat time improved • Idle time reduced• Probe mark more stable• Re-create contact height by each index based on tip position
Card Height changen chip
Alignmentn chip
Alignmentn chip
Alignment
Chuck follow the tip heightZ Height
Time
< Needle tip height changes by event >
Testing Testing
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2003 2003 SWTWSWTW
SACC Cart Safe Operation
• Safe for operator (Bigger, heavier, longer distance )• Safe for heavy, expensive probe card• Improved throughput including floor operation• Remove low usage option from each stage• C.O.O down
SACC CART
Operate few SACC CARTs for entire test floor
Safely Secured – Uses Minimum Operator Space Contributes to using a floor space efficiently
Remove SACC unit from each proberloaded to CART
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2003 2003 SWTWSWTW
128 DUT Probe Interface Electrical Performance Driver Tr/Tf Input- 66 MHz, x2 Sharing
VIH
VIL
50Ω
PD n a
b
c
1
2
1
2
1
2
1
Tester Test Head PCB, Interposer Probe Head
Branched Trace Length Less Than 10 mmIn Probe Head
d2
2.0 2.5 3.0 3.5 4.0 4.51.5 5.0
1
2
3
0
4
time, nsec
DU
T2, V
DU
T_R
EF, V
No-Shared x2 Sharing
1.0 ns
1.08 ns
20%
80%
Simulation
Measured at Spring
Measured Waveform
1.09 ns
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2003 2003 SWTWSWTW
128 DUT Probe Interface Mechanical Performance Scrub Positioning
-15
-10
-5
0
5
10
15
-60000 -40000 -20000 0 20000 40000 60000
X Position (um)
X-E
rror
-15
-10
-5
0
5
10
15
-60000 -40000 -20000 0 20000 40000 60000
Y Position (um)
Y-E
rror
X-Error (um)<+/-5um
Y-Error (um)<+/-8um
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2003 2003 SWTWSWTW
FFI High Performance Probe Interface• Touchdown, Parallelism Optimization• Test Methodology Consultation• Hardware/Software Solution• Onsite Implementation/Integration Support
TCOO Efficiency
DUT Isolation Techniques
Test Program Optimization
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2003 2003 SWTWSWTW
Summary (1)
PSC TRE Project1) Manpower: PSC 6 Engineers, FFI 5 Engineers,
TEL 40 Engineers2) Cost: >$US 2.85 Million3) Time: ~15 Months
PSC TRE Project effective 1) Throughput : 120DUT > 1.6 X 64DUT2) Save more Test Equipment, Manpower, Space
Cost
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2003 2003 SWTWSWTW
Summary (2)
Future Challenge:
1) Device / Pad / Pitch Shrink
2) More Accuracy Contact
3) New Material Development
4) Cleaning Technology
5) High Speed or High Parallelism Testing
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2003 2003 SWTWSWTW
Summary (3)
FFI, as Solution Provider, contributed this project providing:High Performance High Parallelism Probe InterfaceTest Methodology and TCOO Reduction ConsultationEffective Implementation/Integration Service
TELMaintain Pin To Pad (XY and Z) Contact Accuracy with High Parallelism Under All Thermal ConditionsProvides Total Solution for Test Cell and Operations (Operator, Probe Card, Test Result)Co Development Work With Customers to Encompass All Applications and Roadmap Requirements
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2003 2003 SWTWSWTW
Acknowledgement : Special ThanksPSC
Stephen Chen / Jason Shih / Y. S. Chang / David Tseng / Lang Ku / Sammy Wu / Jim Chen / Arod Chiang. / H. W. Peng / F. H. Hsih / Jordan Lin
FFIMark Brandemuehl / Nick Sporke / Randy Lee / Chuck Millar / Ken Matsubayashi / SPROX Taiwan Team / Rod Martens / Stefan Zschiegner
TEL / HermesCat Inoue / Y. Tanaka / Shiba / Ochi / Terada / EricNagasaka / Yamagata / Amemiya / Suzuki / Kuji / Kawaguchi Kakehi / Kagami / Kamijo / Sakagawa / M. TanakaIto / Kasai / Hyakudomi / Kitatora / Tomioka / Iida Steven / Patrick / Wen