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Higher Density PoP Semiconductor Packaging Solution: Bridging the Infrastructure Gap Between Wire-Bond and TSV Interconnect Vern Solberg Charles Woychik, Wael Zohni and Ilyas Mohammed Invensas Corporation, San Jose, California USA
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Page 1: Higher Density PoP Semiconductor Packaging Solution · Higher Density PoP Semiconductor Packaging Solution: Bridging the Infrastructure Gap Between Wire-Bond and TSV Interconnect

Higher Density PoP Semiconductor Packaging Solution:

Bridging the Infrastructure Gap Between Wire-Bond and TSV Interconnect

Vern Solberg

Charles Woychik, Wael Zohni and Ilyas Mohammed Invensas Corporation, San Jose, California USA

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2

So Who is Invensas?

• Formation: Founded in 2011

• Goal: Develop and commercialize breakthrough semiconductor

interconnect solutions and IP in Mobile, Storage and Consumer

Electronics.

• Core Focus: “Interconnectology”: advanced interconnect,

semiconductor packaging, memory circuitry, modules and 3D TSV

architecture.

• Company: 50+ Employees (1/3 PhD).

• Headquarters: San Jose, CA.

• Current IP portfolio: ~1000 patents and applications.

Providing innovative interconnection solutions

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3

Current Technology Focus

Increasing semiconductor package density and

performance

Reducing overall package assembly and electrical

test cost

o Furnish scalable

performance with

lower power

o Simplify package

assembly

methodology

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4

Current Technology Focus cont.

DFD- a very thin dual face down DRAM package. Package offers superior electrical properties and improve signal integrity at higher frequency.

QFD- a very thin four face down DRAM package. Significantly smaller than the SODIMM in a socket. The QFD package can be soldered directly onto the PC motherboard.

BVA- designed to offer a higher performance Package-on-Package (PoP) by implementing ultra-high IO bond-via-array interface between upper and lower package sections.

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5

• Introduction- market drivers for mobile computing

• Future requirements

• Existing 3D CPU-Memory package solutions

• Wide I/O roadmap review

• Improving Package-on-Package density

• Bond Via Array (BVA) package development

• BVA assembly process

• Environmental test results

• Summary and conclusions

Topics of Discussion

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6

Introduction

• The challenge for today's mobile devices is that they all

need to support more advanced graphics processing.

• To support this factor the industry requires an exponential

increase in processor-to-memory bandwidth.

• This presentation will introduce an innovative 3D

semiconductor package technology designed to resolve

these challenges:

• Bond-Via-Array (BVA™) package, an ultra high-IO

Package-on-Package (PoP) solution that significantly

increases bandwidth to better enable current and future

smartphone and tablet features

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7

Mobile Computing Trends

This all-in-one trend in mobile computing requires

greater computing performance at low power!

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8

Samsung Galaxy S 4G

Samsung KB100L00WM-A453 4Gb (512 MB) of mobile DRAM which contains a 1 GHz Intrinsity Processor package-on-package

ST Ericsson's THOR M5730 HSPA and Thin Modem

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Trends cont.

• New generations of thin notebook PCs such as the MacBook Air and UltraBook variations (Dell XPS, Acer Aspire and the Azus ZenBook) are changing the way memory is used in portable electronics

1.7 GHz Intel Core i5 4 GB DDR3 SDRAM 128 or 256 GB SSD Intel HD 3000 Graphics

Example source: Apple Computer

Common attributes:

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10

Enabling Technologies

• Multi-core processors:

• Significantly increased the need for multiple memory

channels, greater channel bandwidth and more total

memory

• Low power processors:

Directly responsible for explosion in mobile computing

(50% of memory power used for driving the processor-

memory IO)

• Cloud computing:

• The dramatic improvement in wireless bandwidth has

enabled computer driving power reduction and utilization

efficiencies

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Processor-Memory Package Challenge

Source: Samsung

Mobile systems require 2x increase in bandwidth every two years!

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Evolving Processor-Memory Archetecture

CPU + DIMM CPU + Multiple Memory Pkgs

CPU + PoP Memory Stack

CPU + TSV Memory Stack

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13

Multiple Die Packaging

• To achieve greater PCB area utilization for mobile electronic

manufacturing companies initially integrated multiple

semiconductor die elements within a single package outline.

Implementing die-stack

packaging can enable

increased product

functionality and greater

performance potential,

however... Intel

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14

The down side of die stacking…

• Known good die (KGD)?

• In process damage (die cracking)?

• Test complexity (logic and memory)?

• Assembly process complexity

Except for memory applications, the die stack assembly

yields are often below acceptable levels, especially for

more complex logic and processor applications.

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Existing Processor-Memory PoP / PiP Solutions

Source: New Venture Research

Package-on-Package Package-in-Package Through Mold Via PoP

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Background and Standards for PoP

• Package-on-Package Technology provides an efficient

solution for system level packaging because each section

can be fully tested before joining.

Pretested memory

section

Pretested logic

section

The logic die element is most often packaged as a solo

unit before joining because it generally requires more

specialized electrical test methodology.

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17

JEDEC PoP Design Standards

• The JEDEC Publication 95 - 4.22 Package-on-Package

design guide standard specifically defines a multiple die

configuration that has at least two micro-electronic

packages assembled in a vertical stack.

Example source: JEDEC JC-11

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High Density PoP Interface Challenge… • The current PoP interconnect technologies have attempted

to improve package interface density using:

• Smaller sized solder balls

• Solder filled laser drilled vias in the mold cap

• Adopting higher density PCB interposers

• Even though higher density multi-layer circuit routing has

had some success, the current PoP format cannot achieve

required bandwidth aspect ratios for the new generation

semiconductors

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Standard PoP Ball Diameter Variations

PoP

TMV PoP Example source: JEDEC JC-11

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Upper and Lower Package Interface

2 Row Matrix 3 Row Matrix

Example: Maximum I/O for 14mm x 14mm package outline

2 Row Matrix 3 Row Matrix

0.50mm pitch, 200 I/O 0.50mm pitch, 288 I/O

0.40mm pitch, 256 I/O 0.40mm pitch, 372 I/O

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21

PoP Issues and Concerns

• Although the PoP assembly methodology has become

mainstream, a number of issues continue to trouble users-

☐ How to accommodate greater I/O semiconductors?

☐ How can we enhance package performance?

☐ How do we maintain lower power operation?

☐ How to minimize package warp during SMT assembly?

☐ How can we maximize existing infrastructure capability?

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Addressing Need for Wider I/O Bandwidth

• Product developers are looking to the semiconductor

package assembly specialist for a packaging process that

can enable maximum efficiency for future generations of

high-density PoP.

• The challenge is to develop a packaging technology

designed to accommodate greater I/O while minimizing the

PoP package footprint.

• To achieve these goals the industry is asked to consider

adopting more innovative package solutions

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23

Bridging the Gap for Wider I/O

The goal of BVA PoP is to offer TSV capabilities for PoP applications

utilizing conventional PoP infrastructure and materials.

2010 2011 2012 2013 2014 2015 2016?

Mobile DRAM LPDDR LPDDR2 LPDDR3 Emerging

Wide IO Wide IO

Packaging PoP PoP PoP PoP BVA PoP TSV

Mobile processor to memory

interconnect 168 168 240 240

IO ranging from 200 to 1000+

1250

Clock Speed (MHz)

400 533 800 High IO offers high bandwidth at low

speed 200

Power 2X 1X 0.8X Enables

intermediate power reductions

0.5X

# of Channels Single Single Dual Dual Quad+ Quad+

Bandwidth (GBps)

1.6 4.2 8.5 12.8 >12.8 >12.8

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Bond Via Array: HDI Interface Solution for PoP

•To overcome the limiting aspects of the current POP

assembly methods an alternative substrate

interconnect solution has evolved.

•The molded ‘bond via array’ (BVA™) is a wire-bond

based package stacking interconnect technology

developed to enable much finer contact spacing

between lower and upper PoP sections.

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25

Bond Via Array (BVA) Test Package Development

• The Package-on-Package ‘Test Vehicle’ initially designed

for this development program has a 14mm x 14mm outline

and provides more than four hundred 240um pitch

interconnects between the lower and upper package

sections

The interconnect process developed for the BVA

utilizes copper bond-wire that can furnish an array configured contact pitch as close as 200µm

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Bond Wire to Solder Bump Interface • The main features of the BVA package assembly is that the

Pd plated Cu wire-bond contacts are encased and

supported in the mold compound that encapsulates the

lower package semiconductor.

• The Cu wire extends from the top surface of the lower

substrate to matching contact locations on the bottom

surface of the upper package.

The reduced BVA contact pitch will easily accommodate a greater number of interconnects in the PoP perimeter stacking arrangement.

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BVA Molded Cu Wire Process Development

• The BVA TV development focused on the integration of processes and materials used to produce 50µm (2 mil) diameter solid copper wire interconnections having a >8:1 aspect ratio.

• The substrate outline for both lower and upper sections of the PoP test vehicle was 14mm x 14mm.

• The lower substrate of the BVA test vehicle design was based on the current industry capabilities having 0.50mm pitch solder balls for PCB interface.

• The Cu wire BVA contacts are wire-bonded onto the top surface of the lower section in a two-row pattern with 240µm pitch.

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BVA Wire Termination Process…

• Various approaches to bonding and forming the copper wire

on the bottom package substrate were evaluated.

• It was determined that a free-ended Pd coated Cu wire

provided a finer contact pitch in both X and Y directions.

Wire%Bond%Process—1/3%

!

Standard K&S ICONN Bonder

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29

BVA Wire-Bond Development Challenge

Objective: To develop an HVM BVA wire-bond process that is comparable to the standard Cu wire-bonding process, by Feb 2013

Goals: Must accomplish the following key metrics • XYZ consistency within +/-15 um (3 sigma) • WPS: Between 8-9 wires per second • Capillary Tool-Life: Same as standard wire-bond • MTBA/MTBF: Same as standard wire-bond

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BVA Wire Bond and Form Demonstration

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BVA Contact (I/O) Density Potential

BVA with 0.24mm pitch can offer up to 1000 I/O

using the same amount of area currently required

for the 0.5mm FBGA pitch PoP.

≤ 1mm

2 3 4 5 6

0.50 200 288 - - -

0.40 248 360 - - -

0.30 336 492 640 - -

0.25 408 600 784 960 -

0.20 512 756 992 1220 1440

Pitch

(m

m)

No. of IO rows

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32

Wire-Bond Process Refinement

• A daisy chain test vehicle substrate was designed and fabricated that featured bond pads at 240µm pitch

• This is a significantly smaller contact pitch than currently applied to FBGA based PoP products

Two row, 400µm high

free-ended Cu wire

BVA contacts at

240µm pitch.

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33

Die Attach and Underfill • The bumped flip-chip package is mounted and reflow

soldered to the land patterns on the B-T interposer

• Assembly is cleaned, underfill applied and cured prior to

transfer mold process

0.52mm Cu wire

Contact height

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34

BVA Mold Process Development

• Both upper and lower BVA package sections are encased in a

commercial mold compound.

Upper Package Section

Lower Package Section

The upper package section is molded with a flat top

surface

The lower package section is molded with the

parimeter areas recessed to expose the tips of the

wire contacts

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35

BVA Base Package Molding Process

• The process adapts a mold-chase

design that forms a recess at the

package perimeter that is slightly

deeper than the formed Cu wires.

• When the mold is clamped to the

substrate, the Cu wires are

pushed through the mold-chase

film.

When the mold tool is opened the mold-chase film is

pulled away from the package exposing the

protruding wire tip contacts above the mold surface.

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Addressing the BVA Process Challenges

• The primary challenges identified and solved during the

development of the molded Cu wire technology included:

• How to terminate the wire tip at a prescribed height and

X-Y position repeatedly with acceptable tolerances.

• How to cleanly expose a solder-compatible wire contact

above the mold cap.

• How to reflow the top package solder balls to the

protruding BVA contact features with acceptable yield

and reliability

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37

Exposing the wire tip above the mold cap- • A number of methods were explored to address the second

challenge, which is exposing the end of the wire through the

molding compound for soldering to the upper PoP package.

These included:

• Surface grinding, laser ablation, sand blasting or wet

blasting the entire top surface of the molded package.

• Coating the wire tip with a protective coating before

molding then rinsing the coating off to expose the wire tip

area.

• Laser ablation to form a semi-spherical cavity around

every BVA wire tip.

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38

Mold Bleed Removal

• A wet etch process was successful in removing the slight

mold bleed around the protruding BVA wires

• The strip is submerged in H2SO4 (96%, 95C, 1min)

• Only the mold surface is exposed to wet etch process to

protect the interposers surface

10-15um of mold residue is removed; the quality of wire

plating and the overall strip is not affected by this process.

Before After

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39

Protruding Cu Wire Variation

• The amount of wire that

was exposed after

molding was measured

on specimens built using

seven process variations.

• The end protrusion of Cu

wire was controlled to an

average value of 110µm

with a standard deviation

of 9µm.

Ave. = 110µm Std. Dev. = 9µm

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40

BVA Package Joining

• The upper and lower package sections are joined using a

flux-dip and place and solder reflow process

• A matching solder bumped contact pattern is provided on

the bottom surface of the upper (memory) section

The close contact spacing enables the shortest possible

routing path between the over-molded processor on the

lower section to the DRAM memory encased in the upper

section

DFD™ Packaged

SDRAM

BVA™ Packaged

Processor die

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41

Pre-Joined BVA PoP Assembly

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42

BVA Cu Wire to Solder Ball Interface

• The stacked BVA PoP units are heated to 240°C in an in-

line convection furnace to reflow the solder and provide a

uniform solder interface between the solder bump and BVA

Cu contact tip

Solder bumped upper

package section

BVA prepared lower

package section

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43

BVA Interface Verification

Solder joint to upper

package section

BVA contact on lower

package section

Solder ball contacts

on bottom of the lower

package section

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44

Board Level Assembly Process Flow Variations

Print Solder paste on PCB Land Patterns

Place lower (logic) package

Flux dip/ Place Upper package

Reflow solder onto PCB, clean X-ray inspection

Apply underfill,

Electrical test and inspection

Process ‘A’

Simultaneous BVA section

joining and PCB mounting

Underfill applied to both lower and upper sections

Print Solder paste on PCB Land Patterns

Place pre-joined package

Reflow solder onto PCB

Clean/ e-test X-ray Inspection,

underfill

Process ‘B’

Place and reflow solder pre-

joined BVA sections on PCB

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45

BVA Test Vehicle

• The BVA test vehicle outline is 14mm x 14mm with a total of

416 top-to-bottom package connections.

• The daisy chain connection pattern links only the package

sections and substrate platform together.

• Current BVA test vehicles do not include connections to

test the silicon die elements within the package sections.

• The test vehicles have been subjected to a broad range of

physical testing at the Invensas Laboratories in San Jose

California.

• The test parameters selected are in compliance with their

intended use environment.

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BVA Package Environmental Test Plan • Moisture Test J-STD-020C

• 125°C / 24hrs, 30°C/60% RH / 192hrs + 3X Pb free

reflow cycles

• High Temp Storage Test JESD22-A103D

• 150°C / 1000hrs

• Unbiased Autoclave Test JESD22-A102D

• 121°C / 100% RH / 2 atm

• Drop Test JESD22-B111

• 30 drops, 1500G, 0.5msec of half sine pulse

(mounted onto PCB)

• Temp. Cycle Test

• - 40°C to +125°C, 1000 cycles (mounted onto PCB)

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47

On Board BVA PoP Solder Interface Testing

• Drop testing has been conducted

on the joined BVA PoP test

vehicles mounted onto a FR-4

circuit board test platform per

JEDEC standard JESD22-B111.

• Underfill was applied between

the upper and lower package

sections and between the lower

package section and test PCB

platform.

Example source: Yoshida Seiki

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48

BVA Environmental Test Results

Test

Moisture Sensitivity

Level 3

High temp. Storage

Unbiased Autoclave

Drop Test

Temp cycle (board lvl,)

Standard

IPC/JEDEC J-Std-020C

JESD22- A103D Cond B

JESD22-

A102D Cond D

JESD22- B111

JESD22- A104D Cond G

Test Condition

125°C/24 hrs 30°C@60%RH/

192 hrs+ 3X Pb free reflow

150°C/

1000 hrs

121°C@100%RH, 2atm/168 hrs

>30 drops,1500Gs

0.5 msec of half sine pulse

-40°C to +125°C

1000 cycles

Sample Size

22 logic + 22 memory

Packages

22 joined BVA off PC board

22 joined BVA off PC board

20 joined BVA on PC board w/underfill

45 joined BVA On PC board w/underfill

Eval. Method

C-SAM inspec @ T0 and post

MSL3

E-test after 168, 500 and 1000hrs

E-test after 96

And 168hrs

In-situ Monitoring

In-situ E-test up to 1000 cycles

Result

100% Pass

100% pass

100% pass

Pass

(128 drops)

100% pass

128 Drops

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49

Summary and Conclusions

• Increasing demand for product miniaturization and high-

performance computing continue to call for higher density

devices and modules.

• The mobile electronics markets continue to see significant

growth.

• Developers of UltraBook, smart phones and tablet

products are now adopting multi-core processors that

need greater memory bandwidth.

• To meet these market trends, manufacturers are expecting

faster process capability and greater memory bandwidth to

be packed into less space with reduced power.

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50

Existing package assembly infrastructure…

• Process capability for wire-bond and molding are commonly

found in packaging assembly factories but, the molded,

open-end BVA contact process is unique.

• Primary differences are the copper wire formation and the

film-assisted molding techniques.

• In regard to board level (SMT) assembly, most EMS

suppliers using commonly found SMT package placement

equipment will have the necessary capability.

• The top and bottom package can be pre-joined before

board mounting or sequentially stacked in place and

simultaneously reflow soldered onto the product board.

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51

Acknowledgements-

• The authors wish to thank the key members of the Invensas engineering and testing laboratories in San Jose, California;

• Ellis Chau

• Rajesh Katkar

• Rey Co

Page 52: Higher Density PoP Semiconductor Packaging Solution · Higher Density PoP Semiconductor Packaging Solution: Bridging the Infrastructure Gap Between Wire-Bond and TSV Interconnect

Invensas Corporation, San Jose, California USA

Invensas.com

Thank You


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