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Taking into Account Obsolescence in the EMCPerformance of Integrated Circuits and Systems

Richard PerdriauProfessor

Measurement and Modelling Standards in EMC of Integrated Circuits: an Application to Obsolescence Issues in ICs and

Systems

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ESEO-EMC – Angers, Francerichard.perdriau@eseo.fr

http://eseo-emc.fr/people/richard-perdriau

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

IEEE EMC HK Chapter Technical SeminarMay 2, 2013

Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Global methodology for obsolescence management

IV Case studies

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IV. Case studies

V. Conclusion

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

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Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Global methodology for obsolescence management

IV Case studies

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IV. Case studies

V. Conclusion

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

EMC vs. obsolescence (1)

Increase in the life span of transportation systems• Automotive industry: more than one decade• Aircraft industry: several decades (B737: 1967-)• Aircraft industry: several decades (B737: 1967-)• LS of semiconductors < LS of equipment/systems

Need for maintenance of electronic systems• Several supply sources for electronic devices• Changes in technological and manufacturing processes

Expensive and demanding qualification processesAircraft industry: certification procedures

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• Aircraft industry: certification procedures

Critical role of EMC in safety• Responsible for several hazardous issues (cruise control)

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

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EMC vs. obsolescence (2)

• What happens from an EM point of view if a component within a system (IC on a PCB, PCB in a piece of equipment, piece of equipment in a system) is replaced by another one with the same functionalities, but with differences in fabrication?differences in fabrication?

Manufacturer 1(obsolete IC)

R.I.P.

Emission/immunity with IC manufacturer 1

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(obsolete IC)

Manufacturer 2 Emission/immunity with IC manufacturer 2

?

Keyword: prediction

The need for modelling: anticipating vs. coping with

With modelling

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Without modelling

E. Sicard

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Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Global methodology for obsolescence management

IV Case studies

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IV. Case studies

V. Conclusion

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

SEISME: introduction

SEISME = Simulation de l'Emission et de l'Immunitédes Systèmes et Modules Electroniques

• Simulation of the Emission and Immunity of Electronic Systems• Simulation of the Emission and Immunity of Electronic Systems and Modules

Funded by the Ministry of Industry• "Aerospace Valley" competitiveness cluster• Midi-Pyrénées region (main city: Toulouse)

Main contributors: automotive and aeronautical industry

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industry

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

Introductory material borrowed from:C. Marot, E. Sicard, "EMC standards at IC level - Status of IEC and Technical

Goals of the SEISME Project", APEMC 2012, May 21-24, 2012, Singapore

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SEISME: contextEMC validation by measurement

Current state

Obsolescence: A change of component on a PCB due to obsolescence. The life span of electronic systems has become much longer than the one of semiconductor devices.

Modification

Future state

Computational EMC validation

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Multi-source: Within the whole production phase, an equipment/system manufacturer may change one or some of its component/subsystem suppliers for industrial and/or financial reasons.

Evolution: Within the whole life span of a system, it may be necessary to improve its functioning and/or its performance.

Re-use: Within the production phase, a piece of equipment may be re-used in another system, with minor specification and/or design changes.

SEISME: objectives

Develop virtual prototyping• Define tools, models, testing and computation methods for the

EMC analysis of a component or equipment change within its lifeEMC analysis of a component or equipment change within its lifespan

Improve virtual testing• Reduce the number of EMC requalification tests of a piece of

equipment and/or a system• Cut out the duration and cost of these tests

Propose modelling standards

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• Create a unified project within the IEC (International Electrotechnical Commission)

• This project should gather standard proposals of models andextraction methods for components, PCBs and equipment

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

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SEISME: approaches

Generic approach for obsolescence management

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SEISME: approaches

Black-box modelling• Define the EMC models of a piece of equipment without any

knowledge of individual device models and PCB routingknowledge of individual device models and PCB routing• Measurement-based modelling

White-box modelling• Define an EMC model by assembling lower-level models

(devices, PCB)• "Bottom-up" approach• Compatible with simulation procedures

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SEISME: workpackages (1)

WP0: management and disseminationWP1

M t f th l ti f di t d i t t d d i• Management of the evolution of discrete and integrated devicesfor the EMC validation and qualification of an electronic board

WP2• Analysis of a change of electronic board for the EMC validation

and qualification of a piece of electronic equipment

WP3• Management of the evolution of power modules for the EMC

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• Management of the evolution of power modules for the EMCvalidation and qualification of a piece of electronic equipment

WP4• Analysis of a change of electronic equipment for the EMC

validation and qualification of a whole system

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

SEISME: workpackages (2)

WP5• Development of extraction and modelling methods for emission

and immunityand immunity

Main targets• WP1 and WP3: automotive manufacturers (single-board systems)• WP2 and WP4: avionics and aircraft manufacturers (multi-board

systems)• WP5: transverse (suited to all WPs)

Model boundaries

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• WP1 and WP3: component package• WP2: backplane connector• WP4: equipment connector

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Large businesses

AIRBUS, EADS IW, GERACCONTINENTAL, MEAS, RENAULT, VALEO

SEISME: partners

CST, SERMA, STUDELECNEXIO EPEA platform

Small and medium-sized businesses

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ESEO, IMS, IRSEEM, ONERA, SATIE, INSA Toulouse

Academic research

Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Global methodology for obsolescence management

IV Case studies

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IV. Case studies

V. Conclusion

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Reminder: the ICEM-CE model

The ICEM-CE model for conducted emission

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PDN : passive distribution network – IA : internal activity – IBC : inter-block coupling

Reminder: the ICEM-RE model

The ICEM-RE model for radiated emissionUse of a network of electric and/or magnetic dipoles to

reproduce the 6 components of the EM fieldreproduce the 6 components of the EM field

y

z

r

l

θ

y

z

rθ

a

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x

y

φ

(a) (b)

xφ

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Reminder: the ICIM-CI model

The ICIM-CI model for conducted immunity

IB : immunity behaviour

DI

IB : immunity behaviour

DI : disturbance inputsDO : disturbance outputsDL : disturbance loadsOO : observable outputs

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Hierarchical modelling: from IC to PCB and equipment (1)

Printed Circuit Board (EBEM, EBIM)

Passive PDN

Integrated Circuit (ICEM, ICIM)

IA PDN

Equipment

Equipment (EQEM, EQIM)

DI

Distribution Network

IB Immunity behavioral

PDN

IEC 62433Σ,Π

IA Internal activity

PDN Board

Equipment

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Other integrated circuit

Other printed circuit board

C. Marot, E. Sicard, "EMC standards at IC level - Status of IEC and Technical Goals of the SEISME Project", APEMC 2012, May 21-24, 2012, Singapore

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Hierarchical modelling: from IC to PCB and equipment (2)

EBEM-CE/EBIM-CI (Electronic Board Emission/Immunity Model - Conducted)

• Gathers ICEM-CE/ICIM-CI models equivalent models of passive

DI

• Gathers ICEM-CE/ICIM-CI models, equivalent models of passivedevices, PCB trace models and connector models

• Bottom-up approach• Objective: use of circuit-level simulators (SPICE-based)

EQEM-CE/EQIM-CI (Equipment Emission/Immunity Model - Conducted)

• Gathers EBEM-CE/EBIM-CI models and cable harness (or other

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(interconnection) models

• Bottom-up approach

ExxM-Rx/ExxM-RI (Equipment Emission/ImmunityModel - Radiated): TBD

Reminder: abstraction levels

Black-box or white-box modelling?

• Uses S- or Z-parameters• ☺ Preserves confidentiality• ☺Well suited to equipment

• Must be related to physics• Less confidential

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manufacturers• ☺ Simpler to extract• Can be transformed into a behavioural SPICE netlist• Does not lead to any simple interpretation of observed phenomena

• ☺ Allows a better understanding of physical phenomena• ☺ Makes it easier to identify possible technological parameters• ☺ Provides clues for the prediction of technology-related trends

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Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Global methodology for obsolescence management

IV Case studies

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IV. Case studies

V. Conclusion

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

Case study: obsolescence of serial memories (1)

Serial memories are good candidates for obsolescence• Ubiquitous in consumer electronics (configuration storage)• Many different technologies (EEPROM Flash FRAM)• Many different technologies (EEPROM, Flash, FRAM)• Many different manufacturers• Same package (SO8), pinout and interface (SPI)• Same protocol: almost all memories are interchangeable

Main interrogations• Do all technologies have comparable EMC performance?• Within a given technology do all memories from all manufacturers

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Within a given technology, do all memories from all manufacturersshow comparable EMC performance?

• Are memories sensitive to EMI in all operating modes?• How does a change of manufacturer impact the EMC behaviour of a

whole electronic board?• Is it possible to predict the behaviour of upcoming technologies?

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Case study: obsolescence of serial memories (2)

Development of specific boards for memory testing

USB to SPI interface

RF injection path

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Specific DPI board

The whole following work by M. Amellal (Ph.D student at ESEO), submitted for publication.

Case study: obsolescence of serial memories (3)

First step: PDN extraction (S-parameters)• Two 512-kbit EEPROMs from different manufacturers (AT, MCHP)

Vdd

AT25512Z11 parameter of the VDD pin of the AT25512 EEPROM

Measurement (red) and first-order model (blue)

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MOS capacitance

25LC512

Series resistance

Z11 parameter of the VDD pin of the 25LC512 EEPROM

Measurement (red) and first-order model (blue)Passive 

capacitance

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Case study: obsolescence of serial memories (4.1)

Second step: DPI test• Test 1: disturbed write, undisturbed read• Test 2: disturbance between write and read

Write  Read 

Write  Read • Test 3: undisturbed write, disturbed read• Difference: up to 15 dB Write  Read 

15 dB

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Case study: obsolescence of serial memories (4.2)

Second step: DPI test• Differences among memory technologies• EEPROM (25LC512), Flash (A25L010), FRAM (FM25W256)• Immunity: EEPROM > Flash > FRAM

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Case study: obsolescence of serial memories (5)

Third step: technological analyses

AT25512

Simple/double bonding Different silicon thicknesses Different surfaces and layouts

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25LC512

Cooperation with M. Medina (SERMA Technologies, Bordeaux, France), submitted for joint publication.

Case study: obsolescence of serial memories (6)

Fourth step: ICIM-CI modelling for immunity prediction• Use the model to predict immunity with an additional 100 pF cap.• The whole board is modelled including parasitics• Good prediction with respect to measurement uncertainties (VNA)

Unconstrainedsimulation

Amplifier limit

S-parameter block

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Comparison between measurement and modelling for the AT25512 EEPROM in

disturbed write testingModelling of the whole PCB and DPI test setup

using the ICIM-CI model of the memory

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Case study: obsolescence of serial memories (7)

Significant differences among interchangeable memories

• Differences in immunity among storage technologies• Differences in immunity among storage technologies• Up to 15 dB difference in immunity between two EEPROMs (maybe

more for other manufacturers?)

Possible explanations• MOS capacitance = difference in channel length and on-chip

capacitance• EMC countermeasures: on-chip capacitance, on-chip resistance,

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double bonding

How can we predict this effect on the whole PCB?• Use the ICIM-CI model

Case study: obsolescence of microcontrollers (1)

Enhancing the performance of an embedded system often requires an upgrade of its microcontroller

• ARM architectures are ubiquitous in embedded systems• ARM architectures are ubiquitous in embedded systems• Some ARM microcontrollers are pin-to-pin compatible• Case study: replace an ARM7TDMI (ATMEL AT91SAM7256) with a

Cortex-M3 (ATMEL AT91SAM3S4B) with different architectures andmanufacturing technologies

Main interrogations• Are newer technologies more or less immune to EMI?

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• Is there a relation between S-parameters and immunity to EMI forvery complex systems?

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Case study: obsolescence of microcontrollers (2)

First step: PDN extraction (S-parameters)

Z11 parameter of the VDDIN pin of the SAM7S µC

Measurement (red) and first-order model (blue)

First-order PDN model of the VDDIN pin of the SAM7S µC

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Z11 parameter of the VDDIN pin of the SAM3S µC

Measurement (red) and first-order model (blue)

First-order PDN model of the VDDIN pin of the SAM3S µC

Note: the Flash block is powered by VDDIN

Case study: obsolescence of microcontrollers (3)

Second step: DPI test• Different results depending on the injection pin• SAM7 more sensitive than SAM3 on VDDIN, opposite for VDDIO• No clear relation between S- or Z-parameters and immunity• Immunity drop between 600 and 700 MHz (SAM3) to be explained• Note: unrecoverable errors (bootloader reload) found at 1.25 GHz

(SAM7) and 1.1 GHz (SAM3)

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DPI test on the VDDIN pin DPI test on the VDDIO pin

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Outline

I. Introduction and rationaleI. Introduction and rationale

II. The SEISME collaborative project

III. Practical examples

IV Advanced measurement and modeling methods

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IV. Advanced measurement and modeling methods

V. Conclusion

IEEE EMC HK Chapter Technical Seminar - May 2, 2013 - Richard PERDRIAU

Conclusion

Collaborative project gathering industry and academia

Hierarchical modelling methodHierarchical modelling method• IC-level (ICEM/ICIM), board-level (EBEM/EBIM) and equipment-

level (EQEM/EQIM) modelling• Bottom-up approach

Prediction of the effects of obsolescence on EMC• "White-box" approach: identification of variable parameters• Substantial differences in immunity (more than 15 dB) for the

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• Substantial differences in immunity (more than 15 dB) for thesame functionality

• Necessity to take into account obsolescence in EMC of complexsystems (automotive, aircraft)

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Conclusion

Thank you for your kind attention.Any questions?

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