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Asynchronous {Pipelines, dataflow}

Honors Discussion #5

EECS 150 Spring 2010Chris W. Fletcher

1UCB EECS150 Spring 2010, Honors #5

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Today

HSRA commentary

Clocking

Synchronizers Dataflow in asynchronous systems

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Big Picture

Last week: Synchronous pipelines

& data transactions

This week: Asynchronous pipelines& data transactions

Next week: {Synchronous, Asynchronous} FIFOs

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Clocking Basics 1

A clock signal

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Clocking Basics 2

A clock signal

Setup time

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tsetup

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Clocking Basics 3

A clock signal

Setup time

Hold time

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tsetup thold

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Clocking Basics 4

A clock signal

Setup time

Hold time clkQ

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tsetup thold

tclkQ

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Clocking Basics 5

Quiz: Can tsetup or thold to be negative?

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thold tsetup

tclkQ

tsetup < 0: D can change after the clock edge

and the new D will be recognized thold < 0: D can change before the clock edge

and the old D will be recognized

What about clk

Q?

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Metastability 1

What happens when tsetup or thold are violated?

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tsetup

metastable resolution

outin

Activ

e

Active

???

Output unknown

(somewhere between 0 and 1)

until resolution occurs

at which point out could

be either 0 or 1!

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Metastability 2

When can tsetup or thold be violated?

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One Clock

Design doesnt meet timing

(You have bigger problems)

tsetupLogic

Two Clocks: different frequencies

Will almost always cause violations

Thought Q: Exceptions to this? tsetup tclkQ tclkQ

???

Two Clocks: phase offset

May or may not cause violations tsetup

tsetup

tclkQ

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Metastability 3

Resolution must occur within tr

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tr = tp tclkQ-tcl - tsu

tsetup

tp

tclkQtcltr

Good news:chance to leave metastability increases exponentially with time

Bad news:

synchronization failure

means circuit failure

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Synchronizers 1

First flip-flop absorbs metastability

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Clock A

Clock B

Input

Clock Domain A Clock Domain B

Level Synchronizer

Output

1 2 3

Second flip-flop protects downstream logic

tr = tp tclkQ- tsu

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Synchronizers 2

How can we do better? Increase tr

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Clock A

Clock B

Input

Clock Domain A Clock Domain B

Reliable Synchronizer

Output

1 2 3

2+ Stage Shift Register

tr = Nx(tp tclkQ- tsu)

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Synchronizers 3

Another reliable synchronizer

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tr = Nxtp tclkQ- tsu

Clock A

Clock B

Input

Reliable Synchronizer

Output

1 2 3

Clock Domain BClock Domain A

Clock

Divider

(by N)

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Synchronizers 4

Synchronizer cost

Area (but not much)

Cycle Delay

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Where does this matter? Handshaking

Case Study:

Asynchronous FIFOs

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Asynchronous Pipelines 1

Recall the FIFO interface that we call Ready/Valid

Valid

Ready

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This worked in a single clock domain

Why?

Ready

Valid

Clock

1+ 1+ 1 0+

Transfers @ edge, both parties

see change at the same time

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Asynchronous Pipelines 2

What happens in two clock domains?

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Valid

Ready

Clock A Clock B

Data

First: we must avoid metastability. Ideas?

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Asynchronous Pipelines 3

Step #1: Add synchronizers (prevents metastability)

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Valid

Clock A Clock B

Clock A Clock B

Clock BClock A

Ready

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Asynchronous Pipelines 4

Step #1: Add synchronizers (prevents metastability)

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Valid

Clock A Clock B

Clock A Clock B

Clock BClock A

Ready

Data

Data

Step #2: Add a hold register (does this help here?)

Aside: Why not push data through parallel synchronizers?

This still doesnt work!

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Asynchronous Pipelines 5

Problem: It takes multiple cycles for a message

from the receiver to reach the sender

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Solution Add buffering to the receiver

Add almost full like in lecture

Why do we care? What happens when

the receiver says stop?

(i.e. DataInReady = 0) Ready

Valid

Clock

Synchronizer delayW

ewant

Weget

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Asynchronous Pipelines 6

Almost full gives sender time to stop

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Valid

Clock A Clock B

Clock A Clock B

Clock BClock A

ReadyData

Data

Data

Data

Data

Same idea as what you saw in lecture

What is the receiver starting to look a lot like?

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Homework

Thought problem

Based on what you have seen in lecture & today:

Draw a block diagram for a synchronous FIFO

(More) reading will be posted

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Acknowledgements & Contributors

Slides developed by Chris Fletcher (2/2010).

This work is based on ideas and discussions with:

Ilia Lebedev, Greg Gibeling, John Wawrzynek, Krste Asanovic,

and other fellow Spring 2009 CS294-48 students

This work has been used by the following courses: UC Berkeley CS150 (Spring 2010): Components and Design Techniques for Digital Systems

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