How far can we push Si CMOS? What lies beyond?

1

EE311/Future Devices1araswattanford University

How far can we push Si CMOS?What lies beyond?

Prof. Krishna Saraswat

Department of Electrical EngineeringStanford UniversityStanford, CA 94305

[email protected]


Bulk-Si Performance TrendsBulk-Si Performance Trends

0.1

1

10

1985 1990 1995 2000 2005 2010 2015

1.0

0.1

10

Rel

ativ

e Pe

rform

ance

1985 1990 1995 2000 2005 2010 2015

Conventional Bulk CMOS

StructuresStructures

NovelNovelDeviceDevice

IEDM BenchmarkIEDM BenchmarkTechnologiesTechnologies

ITRSPredictions

(Bulk)

130nm130nm 80nm80nm 45nm45nm 22nm22nm

90nm90nm 32nm32nm 18nm18nm 9nm9nmPhysical Gate Length Physical Gate Length Technology NodeTechnology Node

Maintaining historical CMOS performance trend requires newsemiconductor material and structures by 2008-2010…

Earlier if current bulk-Si data do not improve significantly

MOSFET in Bulk Si

2


Extending CMOSExtending CMOS• Novel transistor structures and materials

integration can extend commensurate CMOSscaling beyond planar bulk-Si solutions:– Improved Electrostatics and Contacts

• Double-gate or surround-gate• Schottky source/drain

– Improved Materials Properties• High mobility materials (e.g. strained Si/SiGe/Ge, etc.)

• Extended CMOS functionality via newIntegration Technologies

• 3-D Integration (Billions of transistors on a chip)• Exploration of new frontier devices

– Alternatives compatible with silicon


0.001

0.01

0.1

2000 2010 2020

micron

1

10

100

nm

45 nm

65 nm

32 nm

22 nm

16 nm

11 nm

8 nm

Generation

LGATE

Evolutionary

CMOS Exotic Revolutionary

CMOS

Nanotechnology Eras

ReasonablyFamiliar

NanotubesNanowires

ReallyDifferent

Source: Mark Bohr, Intel

3


Partially Depleted SOI

Evolution of MOSFET StructuresBulk

• Device design translates well betweenbulk and PD SOI

• e.g. short channel effect control bydoping/halo (same as bulk)

• Reduced junction capacitances• Dynamic floating body effect - parasitic

bipolar

S DG

S DG

Ref: Philip Wong, IEDM Short Course, 1999


Ultra-Thin Body Single Gate SOI

Ultra-Thin Body DoubleGate SOI

Partially Depleted SOI

Advantages of Ultra-Thin Body SOI• Depleted channel ⇒ no conduction

path is far from the gate• Short channel effects controlled by

geometry• Steeper subthreshold slope• Lower or no channel doping

- Higher mobility- Reduced dopant fluctuation

Evolution of MOSFET Structures

GateGate

Silicon Substrate

Source Drain

TBOX

Si

SiO2

SOI

Source Drain

Gate 1Gate 1 Vg

Tox

SOI

Gate 2Gate 2

Si

Ref: Philip Wong, IEDM Short Course, 1999

4


New Structures and Materials forNanoscale MOSFETs

Problem 1: Poor Electrostatics ⇒ increased Ioff

Problem 2: Poor Channel Transport ⇒ decreased Ion

Problem 3: S/D Parasitic resistance ⇒ decreased Ion

Problem 4. Gate leakage increased

Problem 5. Gate depletion ⇒ increased EOT

CURRENT BULK MOSFET4

1

23 4

5

High IONLow IOFF

Bottom Gate

Top Gate

SchottkySource

SchottkyDrain

High µchannel

High-Kdielectric

FUTURE MOSFET

Solution: Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage

Solution - High Mobility Channel - High mobility/injection velocity - High drive current and low intrinsic delay

Solution - Metal Schottky S/D - Reduced extrinsic resistance

Solution - High-K dielectrics - Reduced gate leakage

Solution - Metal gate - High drive current


Non PlanarNon Planar MOSFETs

UC Berkeley

Gate

Source Drain

Intel

Tri Gate FET

SourceSource DrainDrain

GateGate

SiO2

Channel

Double Gate FinFETVertical FET

Stanford, AT&T

5


For substrate Gefraction x < 30%• NMOS Idsat enhanced ~ 1.5X and• PMOS Idsat enhanced only ~ 1.15X

Strained Si channelwith high mobility

Strained Si gate oxide

Si Substrate

Relaxed Si1-xGex

n+ poly LTOspacer

n+ n+

Si1-xGex Graded layer

0.80

1.0

1.2

1.4

1.6

1.8

2.0

0.0 0.10 0.20 0.30 0.40

Mobility enhancement ratio

Substrate Ge fraction, x

VDS

= 10 mV

300 K

Measured, J. Welser, et al.,

IEDM 1994.

Calculated for strained Si

MOS inversion layer

S. Takagi, et al., J. Appl. Phys. 80, 1996.Mob

ility

Enh

ance

men

t Fac

tor

Substrate Ge Content (%)

0 10 20 30 40 50

Mo

bility

En

ha

nce

me

nt F

acto

r

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6 Calculation by Oberhuber et al.

Rim, et al.

Currie and Leitz, et al.

Mob

ility

Enh

ance

men

t Fac

tor

NMOS

PMOS

Mobility Enhancements in Strained-Si MOSFETs

Gibbons Group, Stanford


S. Thompson, et al. IEEE EDL, April 2004

Simplified hole valance band structure for longitudinalin-plane direction. (a) Unstrained and (b) strained-Si.Hole mobility for uniaxial strained-Si

introduced by Si1-xGex in the source/drain.

(Si3N4)

Enhanced Hole mobility for Uniaxial Strained-Si

Si

6


CMOS Performance Boost WithHigh Mobility Channel

MOSFET Source InjectionMOSFET Source Injection

Mobility (µ) at source edge is related to thebackscattering coefficient (R)

Higher Mobility devices will have higher source-drain current and a lower gate delay

Natori, Lundstrom

( ) injTDD

DDgate

D

DDLOAD

vVV

VL

I

VC

!"

!=

Drive Current & Gate Delay:Drive Current & Gate Delay:

νinj ∝ µε(x)

EF EF-qVDener

gy

position

I+RI+

!

Isat = qNS

Sourcevinj "

1# R

1+ R

$

% &

'

( )


Why Germanium MOS Transistors?Why Germanium MOS Transistors?

Electronic Properties:Electronic Properties:• More symmetric and higher

carrier mobilities (low-field)⇒ More efficient source

injection(due to lighter m*)

⇒ ↓ CMOS gate delay

• Smaller energy bandgap⇒ Survives VDD scaling⇒ ↓ R with ↓ barrier height

• Lower temperatureprocessing⇒ 3-D compatible

(Sze, Phys. of Semicond. Devs. 2nd Ed., p.46, 1981)

Ge

Si

7


Picking the Right High-µ Material

Why Ge?• More symmetric and higher carrier mobilities• Easier integration on Si• Lower temperature processing

17.714.812.41611.8Dielectricconstant

0.170.361.4240.661.12Bandgap (eV)

8505004001900430Hole mobility

7700040000920039001600Electronmobility

InSbInAsGaAsGeSiMaterial ⇒Property ⇓


Problems With GeProblems With Ge•• Problem #1: Problem #1: Ge Surface Ge Surface PassivationPassivation

Native oxide passivation on Ge surface is not stable

Solution: Solution: High-High-kk dielectrics

•• Problem #2:Problem #2: Ge wafer as a substrate?Ge substrate not easy to handle and not easily available

Solution: Solution: Heterogeneous integration of Ge on Si

•• Problem #3:Problem #3: Ge low bandgap Ge low bandgap ⇒⇒ higher leakage?higher leakage?

Solution: Solution: Innovative device structures to reduce leakageInnovative device structures to reduce leakage

8


Heteroepitaxial Growth of Ge on Si

With H2 anneal dislocations are confined to the Si/Geinterface leaving defect free top Ge layers.

Crystalline Ge

Defects

Si

Rrms :2.5nm

400°C Growth + 825°C H2 Anneal

H2

Ge after H2 anneal

Ge

Si

As Grown at 400°C No H2 Anneal

Z = 50nm/div,X= 2µm/div

Rrms : 25 nm

Ge as deposited

Si

AFM

TEM


Ge on Si Film Quality

With Multiple Hydrogen Annealing and Growthdislocations are confined to the Si/Ge interface leavingdefect free smooth top Ge layers.

Threading Dislocation Density measured by opticalmicroscopy reduced to ~1 x 106 cm-2

TEM shows threading Dislocation Density ~ 1.5x107cm-2

TEM

Optical Micrograph

9


GeOI by Rapid Melt Growth

Low-temperatureoxide micro-crucible

Si substrate

InsulatorSeedingregion

Defect necking

LPE

Ge

Heat

James Plummer (Stanford)

Silicon nitrideGe

• Expitaxial regrowth is faster than random nucleation• Ge melt front propagates a long distance ( > 50µm) without being

interrupted by unseeded nucleation.• (Almost) perfect single crystal Ge recrystallized layers obtained.


EOT=21nm EOT=15.8nm

NMOS PMOS

GeON

Ge

SiO2

Poly-Ge

GeOxNy/LTO Stack+ Poly-Ge gate

• Minimum hysteresis and frequency dispersion• Excellent candidate for field isolation

10


Field Isolation

GeON

Ge

SiO2

Al

C/Cox at 1MHz for different size moscaps

8.00E-01

8.50E-01

9.00E-01

9.50E-01

1.00E+00

1.05E+00

-40 -30 -20 -10 0 10 20

V

C/C

oxsmall

large

C/Cox at 1Mhz for different size moscaps

8.60E-01

8.80E-01

9.00E-01

9.20E-01

9.40E-01

9.60E-01

9.80E-01

1.00E+00

1.02E+00

-30 -25 -20 -15 -10 -5 0 5 10 15

V

large,a=100Kum2

small,50Kum2

C/Cox

105 µ2

5x104 µ2

V

V

GeON growth(RTP) ~8nm• RTO at 600ºC for 10sec• RTN at 600ºC for 4min

LPCVD SiO2 deposition ~500nm Metal deposition (Al~100nm) FGA anneal 300ºC

Excellent Isolation achieved


Ge Passivation Ge Passivation with ZrOwith ZrO22

Pt

ZrO2

Ge30Å

HR-XTEMHR-XTEM

⇒ 1st demonstration of hi-κ on Ge⇒ EOTZrO2 ≈ 5-7 Å & EOTHfO2 ≈ 7-9 Å⇒ Minimum hysteresis and frequency dispersion

C-VC-V

11


Leakage for High-k Gate Dielectrics on Ge

GeOxNy leakage comparable to SiO2

High-K dielectrics reduce leakage by several orders of magnitude ZrO2 without interlayer gives the best results


High Mobility PMOSFETs with High-kGate Dielectric on Bulk Ge

Passivation of Ge with GeOxNy, ZrO2 and HfO2 Field isolation by GeOxNy + CVD SiO2 1st demo of Ge MOSFETs with metal gate and hi-κ Subsequent work at Toshiba, MIT, IBM, UT Austin, IMEC, Singapore

Chui, et. al., IEDM 2002 & IEDM 2003Nayfeh, et. Al., IEEE EDL, May 2005.

4 nm

HfO2

Ge

GeOxNy

Mobility

Pt

ZrO2

Ge30Å

TEM + CV ⇒ EOT ~5-7 Å

X-TEM

0.2 0.3 0.4 0.5 0.60

100

200

300

400

Si hi-! pFET

25 µm Ge hi-! pFET 30 µm Ge hi-! pFET 100 µm Ge hi-! pFET

Si Universal Mobility

Effective Field (MV/cm)

Eff

ecti

ve M

ob

ilit

y (

cm

2/V

-s)

12


PMOS in Rapid Melt Growth

150nm

Source DrainGate

Seedingwindow

Tri-gate pMOSFET using LTO/Ge oxynitride gatedielectric Ge fin height: 200 nm I-V Characteristics of GeOI pMOSFET

L=1.5 μm, EOT=17.5 nm

James Plummer (Stanford)

• Excellent candidate for 3D integration


Epitaxial Growth of Vertical NanowiresEpitaxial Growth of Vertical Nanowires

Yiying Wu et al., Chem. Eur. J., 2002, 8, 1261

Si nanowires grow epitaxially on a (111) Si planeSimilar results for Ge nanowires

<111> oriented Si NWs on (111) Si

Au

Nanoparticle

GeContaining

Vapor

Ge Nanowire

Si containingvapor

Sinanowire

(111) surface

[111]

13


Ge Nanowire FET with High K gate dielectricGe Nanowire FET with High K gate dielectric

Ref: Wang, Wang, Javey, Tu, Dai, Kim, McIntyre, Krishnamohan, and Saraswat, Appl Phys. Lett, 22 Sept. 2003

• 10-20 nm single crystal Ge wires• CVD temperature: 275 °C• Initial fabricated transistor shows

great promise µp ~ 500• 3D integrable technology

Ge NW MOSFET

ALD HfO2 Coating of Ge NW

sourcegate

drain

dielectric

semiconductor

~20nmmetal

~10nm

Channel

Key Challenge: Controlled growth

Source

Drain

SiO2

Top view SEM


Transport:• Zero E-field by symmetry of DG structure• Reduced scattering due to perpendicularE-field

• Natural fan-out (lower Rparasitic )

Technology integration:• Easier integration with high-k materials• Fully utilizes excellent transport propertiesof materials like Ge, SiGe, strained Si etc.

Electrostatics:• Excellent control of short channel effectsdue to DG structure

• Excellent sub-threshold slope• Very low DIBL and Vth roll-off

High performance devices:• High mobility channels leading to veryhigh drive currents

• Very high switching speeds• Very high cut-off frequencies• Lower power dissipation

Center Channel Double/Surround Gate FET

Zero E-fieldE-field

Chargedensity

Conventional DG Depletion-Mode DGDepletion regions

Channels at the surface Channel in the center

OFF

ON

S

S S

S D

DD

DG

G

G

G G

G

G

G

Schred: 1-D Poisson-Schrodinger simulations

Krishnamohan and Saraswat, IEDM 2003

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How far can we push Si CMOS? What lies beyond?

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