hspice simulation of nand and inverter

8/9/2019 hspice simulation of nand and inverter

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ASSIGNMENT 1

EE6325

Nidhi Gundigara

UTD ID 2021235294

Date of u!"i ion# 03$03$2015

Answer1



I ha%e de igned &M'S in%erter (a)out u ing 0*13u" &M'S te+hno(og),"ini"u"-.0*13u"/

a/ or o!taining in%erter i ing for neutra( e I did the D& ana() i * The +he"ati+for the D& ana() i fo((o ing* D& ana() i a done in hi+h in a e t fro" 0

to 1*2

or deter"ining . $ n the ara"etri+ ana() i a done in hi+h ain+re"ented fro" 1 to 10 in te of 1 and out a (otted*

7) ara"etri+ ana() i +an !e deter"ined !et een 3 and 4*



or "ore a++urate %a(ue of ara"etri+ ana() i a done in hi+h ain+re"ented fro" 3 to 4 in te of 0*1

Ta ing .3*8 and n . 280n" .280 3*88 . 1086n" i*e . 1*09u

or the ne di"en ion in % out (ot i a !e(o



Layout of 1x inverter: The (a)out a ed D:& - S and ;E< e=tra+tion adone

!/ layout of 4x inverter using multi nger technique : The (a)outa ed D:& - S and ;E< e=tra+tion a done



Layout of driver cell (1x-4x) : The (a)out a ed D:& - S and ;E<e=tra+tion a done

Layout of load cell(1x-1x) : The (a)out a ed D:& - S and ;E<e=tra+tion a done



+/ or deter"ining t >- and t -> for 1= in%erter ;E< e=tra+tion a done for 1=in%erter dri%er and (oad +e((* And fo((o ing h i+e ?(e a u ed

or fanout of 0 the (oad i +o""ented in fo((o ing ?(e* To ?nd fanout of 2 and 4un+o""ent the (ine ith (oad +onne+tion*



$transistor model.include "/home/cad/kits/IBM_CMRF8SF-LM ! /IBM_# %/cmr&8s&/'!.(. . LM/)S#IC*/models/model ! .li+_inc".include test.s,.include dri er.s,.include load.s,

.o,tion ,ost runl l

dd dd0 1nd0 !.('dd! dd!0 1nd0 !.('

'in in 1nd0 #2LS* !.( , ,s ,s !.34 ns 5ns

.tran .!ns ( ns s6ee, &anout ! !

$measurin1 rise time and &all time.measure tran trise tri1 7out( al .!(' rise ! tar1 7out(

al !. 8' rise !.measure tran t&all tri1 7out( al !. 8' &all ! tar1 7out(al .!(' &all !

$measurin1 t,hl and t,lh.measure tran t,hl tri1 7out! al .9' rise ! tar1 7out( al .9'&all !.measure tran t,lh tri1 7out! al .9' &all ! tar1 7out( al .9'rise !

:! in out! dd0 1nd0 dri er:( out! out( dd!0 1nd0 test: out( out dd0 1nd0 load m &anout

.end

Results

Fanout Tphl Tplh0 15.93ps 13.09ps2 31.00ps 25.96ps4 45.24ps 38.29ps

d/ or fanout of 4 e i(( ee !eta

the h i+e ?(e i a fo(o ing

$transistor model



.include "/home/cad/kits/IBM_CMRF8SF-LM ! /IBM_# %/cmr&8s&/'!.(. . LM/)S#IC*/models/model ! .li+_inc".include test.s,.include dri er.s,.include load.s,

.o,tion ,ost runl l

dd dd0 1nd0 !.('dd! dd!0 1nd0 !.('

'in in 1nd0 #2LS* !.( , ,s ,s !.34 ns 5ns

$.tran .!ns ( ns s6ee, &anout ! !.tran . ns ( ns s6ee, +eta .! ! !

.measure tran trise tri1 7out( al .!(' rise ! tar1 7out(al !. 8' rise !.measure tran t&all tri1 7out( al !. 8' &all ! tar1 7out(

al .!(' &all !

.measure tran t,hl tri1 7out! al .9' rise ! tar1 7out( al .9'&all !.measure tran t,lh tri1 7out! al .9' &all ! tar1 7out( al .9'rise !

.measure tran t_a 1 ,aram ;7t,hl < t,lh /(;

.measure tran char1e I=>*? I7 dd! FR@M to ! ns

.measure ener1A ,aram ;char1e !.(;

.measure * # ,aram ;ener1A t_a 1;

:! in out! dd0 1nd0 dri er:( out! out( dd!0 1nd0 test: out( out dd0 1nd0 load:5 out( out5 dd0 1nd0 load: out( out dd0 1nd0 load:9 out( out9 dd0 1nd0 load

.end

esults

The ta!(e !e(o gi%e %a(ue of ED; for di@erent %a(ue of !eta* e +an ee that a!eta in+rea e ,i*e* in%erter !e+o"e "ore tronger/ the ED; de+rea e and ta)+on tant for higher %a(ue of !eta

7eta ED;0*1 115*4eB251*1 12*6eB252*1 9*4eB253*1 8*5eB25



4*1 C*CeB255*1 C*6eB256*1 C*4eB25C*1 C*1eB258*1 C*4eB259*1 C*CeB25

0 1 2 3 4 5 6 C 8 9 100*00E 00

5*00EB24

1*00EB23

1*50EB23

!"#A $%& "'

The "t0 ?(e ho ing ara"eter %a(ue *





3 in ut NAND gate +he"ati+* e i(( u e idth of in%erter !ut for NM'S a (engthi in+rea ing 3 ti"e e i(( ha%e to in+rea e idth a( o 3 ti"e to ee $( ratioa"e of that of 1= in%erter* or ;M'S idth i(( !e a"e a 1= in%erter ;M'S!e+au e on() 1 tran i tor i there for or t +a e*

S+he"ati+ for NAND gate





a/ Nano i" a u ed for generating the out ut ?(e*

2 ?(e are needed for nano i"

1/nand* ?(e i a fo((o

>R =SIS>@R C R S

.inc /home/cad/ lsi/models/hs,ice/cmos .!8um.model

.o,tion ,ost !

.tem, (4

.,aram , dd !.(

....M@SF*>sM> out net ( 1nd0 n&et L .!(2 D .852

< . !3(# S .! 39# # (.552 #S !.((2M>9 net ( B net8 1nd0 n&et L .!(2 D .852< .! 39# S .! 39# # !.((2 #S !.((2M> net8 C 1nd0 1nd0 n&et L .!(2 D .852< .! 39# S .(44(# # !.((2 #S (. 52M> out C dd0 dd0 ,&et L .!(2 D !. 32< .( 4!# S . 34# # !.542 #S (.852M>( dd0 B out dd0 ,&et L .!(2 D !. 32< .( 4!# S .( 4!# # !.542 #S !.542M>! out dd0 dd0 ,&et L .!(2 D !. 32< .5!5(# S .( 4!# # (.352 #S !.542

C # CI>@R C R S

C! dd0 1nd0 (. 89 3*-!9C( 1nd0 .( 4!3*-!9C B 1nd0 . 8 *-!9C5 C 1nd0 5.(3539*-!9C out 1nd0 5.3! 9*-!9C9 a C3 1nd0 8.49888*-!4C4 net8 1nd0 .( 9!*-!4C8 net ( 1nd0 (.9 (9*-!4

StimulusE nalAsisE etc.

''dd 'dd , dd'?= ?= .

In,ut ,attern &or $ ! !



?enerated +A ",erl ,+it(,6l.,l aE?= ns . ! !"

'a ?= #DL ns . ns ns . ns , dd ! . ns , dd ! .!ns ! ns ! . ns , dd

In,ut ,attern &or B $ !! ?enerated +A ",erl ,+it(,6l.,l +E?= ns . !!"

'+ B ?= #DL ns . ns ns ! ns ! . ns , dd ! ns , dd

In,ut ,attern &or C $ !! ?enerated +A ",erl ,+it(,6l.,l +E?= ns . !!"

'c C ?= #DL ns . ns ns ! ns ! . ns , dd ! ns , dd.>R =S . (ns 5 ns

.*=

2/nand*+fg ?(e i a fo((o,rint_node_ B C out,rint_node_i 'ddre,ort_node_,o6r 'dd

:e u(t

'ut ut a%efor"



!/U ing >S;I&E i"u(ation or t +a e t >- and t -> a%erage o er di i ation forfanout of 0 and 4 i "ea ured* The fo((o ing +ode "ea ure the ara"eter forfanout of 0* or fanout of 4 un+o""ent the 4 (oad *

:e u(t

anout T h( T (h A%erage o erdi i ation

0 33*0C 35*55 2*C2u4 59*95 25*35 C*52u

Answer +



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hspice simulation of nand and inverter

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