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38 IEEE CIRCUITS AND SYSTEMS MAGAZINE 1531-636X /11/$26.002011 IEEE THIRD QUARTER 2011

Feature

Digital Ob ject Ident ifier 10.1109/MCAS.2 011.942068

Nanoscale FinFET Based

SRAM Cell Design: Analysisof Performance Metric,Process Variation, UnderlappedFinFET and Temperature Effect

Balwinder Raj,A.K. Saxena,

and S. Dasgupta

Abstract

In this paper the analysis of SNM, RNM, WNM and static pow-er variation with width of access, load and driver have been

carried out for nanoscale FinFET based SRAM cell. FinFET basedSRAM design has been proposed as an alternative solution to the

bulk devices. It can be inferred from the results that with increase inthe width of driver FinFET, the high SNM reduces and low SNM increases.

This is due the fact that the leakage current is considerably reduced due toincreased control of the FinFET device structure, resulting relatively in high I on /

Ioff ratio. Further, the effect of process variation on the SRAM cell performancewas analyzed using Monte Carlo simulation on HSPICE. The Monte Carlo simulation

results for RNM and WNM to quantify the effect of process variation arising due to varia-tion in FinFETs widths. The simulation was carried out for 1000 values, assuming 3 s equal

to 10% of the mean value. Two structures of the FinFET viz. the standard PTM model and anunderlapped FinFET have been also used for the simulations. It was identified that while the rela-

tive levels of the noise margins were lower for the underlapped case, the standard deviation wasconsiderably lower too. In this work we also analyze the effect of temperature on noise margins and

static power for FinFET based SRAM cell. FinFET is suitable for future nanoscale memory circuits designdue to its reduced Short Channel Effects (SCE) and leakage current.

Date of pub lication: 2 5 Augus t 2011


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THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 39

I. Introductionccording to International Technology Roadmap forSemiconductors (ITRS) [1] by the year 2014, 94%of chip area will be occupied by the memory. Ag-

gressive scaling in memory can occur in two manners.One is the cell miniaturization, which can be achieved

by device modeling. Other being the peripherals and in-terconnect scaling. Device scaling to nanoscale regimebrings many problems which are sensitive to processvariation. In recent times, it has been proposed to re-place bulk transistors in SRAM with novel structuressuch as DG-SOI or FinFET structure [2, 3]. Such a pro-posal can be justified from the fact that these devicesare easily scalable without showing SCEs. Further, theleakage current in typically less in FinFET as can be ob-served from the previous chapters. FinFET seems to bea promising candidate to be applied in the next genera-

tion SRAM technology [4, 5] due to its superior scalabil-ity for a given gate insulator thickness, higher channelmobility, absence of random dopant fluctuation effectswithout compromising its performance.

Read stability is often used as the measure of the ro-bustness of an SRAM cell against flipping during readoperation. The hold stability is measured by fitting thelargest square into the Voltage Transfer Characteristic(VTC) of the cross coupled inverters within the SRAMcell at the time the wordline of the cell is disabled. Theread stability and hold stability of SRAM cells is of signif-icant importance in FinFET based SRAM design. Conse-quently, an accurate and efficient estimation of the Fin-FET based SRAM cell stability is necessary in the designphase to ensure the correct functioning of the SRAM aswell as to achieve good yield of the cache system. TheStatic Noise Margin (SNM) has been widely adopted asa measure of the stability of SRAM cells [6, 7] . Maintain-ing sufficient Read Noise Margin (RNM) is always themain challenge of the scaling of SRAM technology [8, 9].It has been reported that variations in Write Noise Mar-gin (WNM) also have a profound impact on SRAMs sta-bility during write operation for partially depleted SOI

technology [10, 11]. So far, the read and write margins(RM and WM) have been optimized by arranging thegate width of MOSFETs. However, this method will notbe sufficient for the scaled CMOS technology in the nearfuture, where process-induced random variation in thedevice performance will become serious. Then, it willbe very difficult to manage the trade-off between RMand WM and ensure both the RM and WM only by thegate-width arrangement. In this case, some novel circuitapproaches to enhance both RM and WM are helpful toovercome this difficulty [12].

The performance of SRAM subsystem is determinedprimarily by the delay involved in driving large loads onthe bitline and the wordline. Due to the large size of theon chip SRAMs in microprocessors designed in nano-meter nodes, leakage current is the major contributorto the total power dissipation in SRAMs. The exponen-

tial increase in leakage current results in large stand-by power. Increased transistor leakage and parametervariation present challenges for scaling of conventionalsix-transistor (6-T) SRAM cells [7, 13]. The SRAM arrayparametric standby leakage contributors include wellisolation leakage [14, 15], subthreshold device leakage[16] and gate-oxide tunneling current [17, 18]. The majorconcern in future SRAMs is the leakage power consump-tion. Due to the reduced threshold voltage in futuretechnologies, leakage power is increasing rapidly. Dif-ferent SRAM cell designs have been proposed to target

leakage control [1921]. To overcome these difficulties,optimization of the device structure is extremely impor-tant for low-power and robust SRAM cell design in sub-30 nm FinFET technologies.

FinFET based SRAMs immunity to mismatch in-duced by process variation becomes quite imperative.Although there are some reports on the impact of pa-rameter fluctuations in FinFETs by direct measurement[8, 22], the sensitivity of FinFET SRAMs stability toprocess variation and methods to enhance such stabil-ity have not yet been systematically addressed to thebest of our knowledge. A FinFET uses an intrinsic body.It greatly suppresses the device-performance variabil-ity caused by the fluctuation in the number of dopantions, while a planar-bulk MOSFET requires a heavilydoped channel which causes serious process variabil-ity. It is preferable to extend the 6-transistor SRAM abil-ity by effectively taking advantage of the FinFET-basedtechnology together with the novel circuit technique.Increased process variation in short channel transis-tors is reducing the robustness of bulk Fin based SRAM.FinFET based SRAM design has been proposed as an al-ternative solution to the bulk devices. This also results

in reduced stability of SRAM cell. FinFET is suitablefor future nanoscale memory circuits design due to itsreduced Short Channel Effects (SCE) and leakage cur-rent. In this chapter, the analysis of Static Noise Margin(SNM), Read Noise Margin (RNM), Write Noise Margin(WNM) and static power with variation of width of ac-cess, load and driver transistor have been carried outfor the stability of FinFET based SRAM cell. HSPICEsimulation results have been presented for the SNM,RNM and WNM. Robust FinFET based SRAM design at32 nm technology should ensure minimum sensitivity to

Balwinder Raj (balwinder raj@ gmail.com), A.K. Saxena and S. Dasgup ta are with the Semiconductor Devices and VLSI Technology (SDVT) Group, Depar tment of Electronics and Computer Engineering , Indian Instit ute of Technology, Roorkee 247 667, India.

A


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40 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

process variations along with proper functionality andlow leakage power. In this paper, we also analyze theeffect of process variation and power consumption ofFinFET based SRAM cell. Monte Carlo analysis was car-ried out to gauge the sensitivity of FinFET based SRAMcell to process variations. In this chapter, we also at-

tempt to design a robust FinFET based 6-T SRAM cell us-ing Predictive Technology Model (PTM) [23] and studyits performance in the presence of process variations.We analyze the variation in Static Noise margin (SNM),Read Noise Margin (RNM), Write Noise Margin (WNM),and power with change in driver, load and access tran-sistor widths. In order to limit static power dissipationin large caches, lower supply voltage can be used [24,25]. However, a low supply voltage coupled with largetransistor variability compromises cell stability mea-sured as Static Noise Margin (SNM) [26]. Although sev-

eral attempts have been made to analyze the impact ofprocess variations on SRAM [8, 27], optimization of thecell has not been done for 32 nm technology.

This paper is organized as follows: In Section II; MOS-FET based SRAM cell design problems are discussed.In Section III; FinFET based SRAM design. In Section IVperformance metrics of FinFET based SRAM are ana-lyzed. In Section V; process variation effect on FinFETbased SRAM are discussed. In Section VI; underlappedFinFET device is explained. Section VII; describes effectof temperature on FinFET. Results are discussed in sec-tion VIII and conclusion is provided in Section IX.

II. MOSFET Based SRAM Cell Design ProblemsMOSFET structure scaling into the sub-50 nm regime re-quires heavy channel doping to control Short ChannelEffects (SCE) and heavy super-halo implants to controlsub-surface leakage currents. Heavy doping degradesmobility due to impurity scattering and a high trans-verse electric field in the on state worsens sub-thresh-old swing and increases parasitic junction capacitance.Thus, for a given off-state leakage current specification,on-state drive current is degraded. Off-state leakage cur-

rent is enhanced due to band-to band tunneling betweenthe body and drain. Threshold voltage (V th ) variability

caused by random dopant fluctuations is another con-cern for nanoscale bulk MOSFETs. With increasing varia-tions, it becomes difficult to guarantee near-minimum-sized SRAM cell stability for large arrays in embeddedlow-power applications. Increasing transistor size, onthe other hand, is counterproductive to the fundamental

reason for scaling in the first place to increase density.Access time is dependent on wire delays and columnheight. To speed up arrays, segmentation is commonlyemployed. With further reductions in bit-line height, theoverhead area of sense amplifiers becomes substantial.

In a bulk MOSFET based SRAM array, exponentialincrease in leakage current results in large standbypower. Furthermore, process variations result in mis-match in the strength of different devices in an SRAMcell. Such a mismatch can result in parametric failures,thereby degrading the design yield. Due to large leakage

current and increased parametric variation, designinglow-power and robust SRAMs is a major challenge in na-noscale technologies. Due to enhanced short channeleffect (SCE), scaling single gate bulk CMOS devices be-yond sub-50nm node is becoming increasingly difficult.Ultrathin body double-gate MOSFET (DGFET) devicesare suitable in sub-50nm technologies due to their high-er immunity to SCE, better scalability and increased oncurrent compared to single gate devices. Furthermore,DGFET has negligible junction capacitance which sig-nificantly reduces the circuit delay. Moreover, body inDGFET devices is lightly doped and threshold voltage1 Vth 2 is principally controlled using metal gate workfunction. The lightly doped body eliminates V th varia-tions due to random dopant fluctuation (RDF).

III. FinFET Based SRAM Cell DesignFinFETs have emerged as the most suitable candidate forDGFET structure as shown in figure 1 [28]. Proper opti-mization of the FinFET devices is necessary for reducingleakage and improving stability in FinFET based SRAM.The supply voltage (V D ), Fin height (H fin ) and thresholdvoltage (V th ) optimization can be used for reducing leak-

age in FinFET SRAMs by increasing Fin-height whichallows reduction in V D. [26]. However, reduction in V D has a strong negative impact on the cell stability underparametric variations. We require a device optimizationtechnique for FinFETs to reduce standby leakage and im-prove stability in an SRAM cell.

FinFET based SRAM cells are used to implementmemories that require short access times, low powerdissipation and tolerance to environmental condi-tions. FinFET based SRAM cells are most popular dueto lowest static power dissipation among the various

circuit configurations and compatibility with currentlogic processes. In addition, FinFET cell offers superiorFigure 1. Double gate FinFET.

FG

LG

BG

Tsi DrainSource


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C. Write Noise Margin (WNM)Write Noise Margin (WNM) is the maximum bitline (BL)voltage that is able to flip the state of the FinFET basedSRAM cell while bitline bar (BL) voltage is kept high[31]. Higher the WNM, greater is the stability. Use of aweaker pull up (pFinFET) and a stronger access FinFET

helps the node storing 1 to discharge faster, thus fa-cilitating a quicker write of 0. The write margin can bemeasured as the maximum BL voltage that is able to flipthe cell state while BL is kept high. Hence, the write mar-gin improves with a strong access and a weak pull upFinFET at the cost of cell area and the cell read margin.

D. Power and Delay Power dissipation of the FinFET SRAM cell assesses theutility of the cell in portable devices. The fundamentaladvantage of the FinFET based SRAM is in its low ac-

cess time and power dissipation due to low SCEs andleakage current in FinFET device. While a strong driv-ing current reduces the access time, it also increasesthe power dissipation in the SRAM cell. In SRAM, thepropagation delay depends on the column height andwire delays. Thus segmentation is employed to reducethe delay. Since the power-delay-product is constantfor a device, increasing one decreases the other andvice-versa. Upsizing the FinFET device in SRAM cell de-creases the delay at the cost of slightly increased pow-er dissipation. However to reduce power dissipation,leakage currents need to be minimized which warrantan increase in the channel length or higher transistorthreshold voltages. Larger channel length results inhigher delay and there exists a trade-off between thesetwo performance indices.

V. Process Variation Effect on FinFET DeviceWith scaling, process imperfections result in significantvariation in FinFET device characteristics. Furthermore,process variations result in mismatch in the strength ofdifferent FinFET devices in an SRAM cell. Such a mismatchcan result in parametric failures, thereby degrading the

design yield. Due to increased parametric variation,

designing low-power and robust FinFET based SRAM cellis a major challenge in nanoscale technologies.

Process variations comprise of FinFET parameters(Channel length (L eff ), Threshold voltage (V th ) etc.) whichare no longer deterministic and die-to-die and within-dievariations may be random or correlated. Die-to-die fluc-

tuations (from lot to lot and wafer to wafer) result fromfactors such as processing temperature and equipmentproperties. Conversely within-die, variations result fromfactors such as nondeterministic placement of dopantatoms and channel length variation across a single die.The reason behind the observed random distribution isdue to the limited resolution of the photolithographicprocess which causes W/L variations in FinFET device.The variations in W and L are not correlated because Wis determined in the field oxide step while L is definedin the poly and source/drain diffusion steps. In case of

random variations, the design parameters are totally un-correlated. As for instance, variations in FinFET lengthare unrelated to V th variations.

With the scaling of technology, process imperfectionis becoming a major concern in maintaining the reliabil-ity of an SRAM cell. The major sources of parameter vari-ations in FinFET are T fin and L eff. In FinFET based SRAM,these parameters include Fin width (W fin ), Fin thickness(T fin ) and threshold voltage (V th ). FinFET based SRAMsare built using minimum size FinFET device to minimizearea, making it highly vulnerable to process variations[28]. Memory designs are optimized for 6 s variations.SRAM failure can occur due to an increase in accesstime, failure to write a bit into the cell, accidental writinginto memory during read or loss of stored bit in standbymode. In scaled technologies, an optimal design strategyof FinFET based SRAM should consider minimization ofarea and access times in conjunction with reducing thefailure probabilities due to variations. Table 1 shows theparameters used in the simulations.

VI. Underlapped FinFET DeviceThe Predictive Technolog Model (PTM) used in our study

models the FinFET device as a self-aligned Double Gate(DG) MOSFET, but without the fin extension regions. Thismodel is satisfactory to understand the characteristics ofthe FinFET device and to appreciate its merits. A typicalunder lapped FinFET device structure is shown in figure3. However, technology constraints prevent thin fins andabrupt junctions from being fabricated [33]. Thus, thedouble gate structure given in the PTM model [23] needsto be modified for FinFET to cater for the fin extensionregions that result due to technological limitations.

The introduction of the fin extension regions in

FinFET device leads to parasitic resistances (due toconstriction/expansion of the current path, electric

Table 1.Parameters used in simulation.

Parameters ValuesLeff 32 nmTfin 8.6 nmtox 1.4 nmChannel Doping IntrinsicSource/Drain Doping 1026 m2 3Vt0,n 0.29 VVt0,p 2 0.25 V


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field lines and ohmic nature ofthe extension, respectively) andparasitic capacitances (due toelectrodes in close proximity)[34]. The underlapped FinFETstructure with fin extension re-

gions, however, has lesser GateInduced Drain Lowering (GIDL)due to physical separation of thegate and drain region which pre-vents the gate from straggling thedrain. As discussed before in Fin-FET device, the channel is largelyundoped (fully depleted) to avoidmobility degradation and V th vari-ation due to doping fluctuations.The extension regions of FinFET

if left undoped offer a large re-sistance to the drain current, se-verely restricting their utility forlow power applications with low voltage supplies. Thecurrent driving capability of the FinFET is expected tobe severely degraded as a result of this. Gulzar A. Katha-wala et al [35] showed that the current in fact drops non-linearly with fin extension length. The resistivity of theextension region is decreased in the fabrication processitself by silicidation process in which a layer of titaniumdoped Si is implanted to increase the conductivity of theextension region in FinFET.

Inspite of the aforesaid reasons, the FinFET effec-tively reduces leakages as compared to the overlappeddevice (PTM), follows a direct process flow from theCMOS technology and hence it is easy to fabricate with-out major overhead costs. The introduction of the fin ex-tension also makes the voltage just outside the channelon the source side, higher than ground. This effectivelyreduces the effect of the gate in inverting the channeland thus, the drive current is further reduced.

A. Various Parameters of Underlapped FinFET

The parameters as mentioned in the figure 3 are: L eff Gate Length, T fin Thickness of the fin layer, H fin Heightof the fin, t poly Thickness of the polysilicon layer pres-ent over the gate oxide, t ox Thickness of the oxide film,Lext Length of the fin extension region between thegate-source or the gate-drain region, W g Width of thesource/drain regions, W S / D Length of the source/draincontact regions.

B. Monte Carlo Analysisof FinFET Process Variations

The reason behind the observed random distribution ofFinFET device parameters is due to the limited resolution

of the photolithographic process which causes W/L varia-tions in MOS transistors. The variations in W and L are notcorrelated because W is determined in the field oxide stepwhile L is defined in the poly and source/drain diffusionsteps. In FinFET based SRAM, the process parametersvariation include FinFET width (W fin ), fin thickness (T fin )and threshold voltage (V th ). These variations affect thenoise margins, power consumption and delay. Memorydesigns are optimized for 6 s variations [28]. To assess theimpact of process parameters on FinFET SRAM, we car-ried out Monte Carlo simulations on HSPICE for 1000 sam-ple values assuming 3 s equal to 10% of the mean value.

C. Effect of Temperature on FinFETs PerformanceIncreased packing density has led to power dissipationto become a critical bottleneck in the design of nanoelec-tronics. The local temperature rise can result in circuitmalfunction and can also impact performance, powerand reliability. For every 10 8 C increase in temperature,a FinFETs drive current decreases approximately by

4% and interconnect (Elmore) delay increases approxi-mately by 5% [16]. Power density (power dissipation perunit area) of a CMOS chip is given by 5 CVD2f, where C isthe node capacitance per unit area and is based on theaverage switching activity of the signal, V D is the supplyvoltage and f is the clock frequency. With increase in tem-perature, the leakage current increases exponentially,(a difference of 30 8 C will affect the leakage by 30%) andhence, the power dissipation increases substantially inFinFET device. This, in-turn, further increases the tem-perature and the cycle continues until thermal runaway

occurs. Hence, temperature is one of the most importantperformances metric in future VLSI circuit designs.

Figure 3. A typical underlapped FinFET device.

Leff

Hfintpoly

Lext

Tfintox

S o ur c

e

P ol y

G a t e

Dr ai n

Wg


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VII. Results and DiscussionFigure 4 shows the variation of butterfly curve for load

FinFET M2 with variation of its width. It can be seenthat the high Static Noise Margin (SNM) reduces andlow SNM increases with decrease in the width of loadFinFET M2. Thus, as width of the load FinFET reduces,so does the driving capability of the load device. Thisimplies that Q reaches to V OH at a much higher voltage,thus, resulting in a decrease in high SNM. It is furtherobserved that as the widths of the pull-up device de-creases, the switching threshold also tends to reduce.Since the driving capability of M2 reduces with the re-duction in width, therefore, it requires lesser amount ofvoltage at BL for the purpose of switching threshold.The variation of Static Noise Margin (SNM) for driverFinFET M1 with variation of its width is shown in figure5. It can be inferred from the figure that with increase inthe width of driver FinFET M1, the high SNM reduces andlow SNM increases. This is due the fact that the leakagecurrent is considerably reduced due to increased con-trol of the FinFET device structure, resulting relativelyin high I on / Ioff ratio. In the case of RNM, the stability ofthe cell is most seriously compromised as the node con-

taining 0 is pulled up to a voltage determined by therelative sizing of driver and access FinFETs.

Figure 6 show the variation of WNM and RNM of a cellwith the width of the load FinFET. A stronger pFinFETgives a higher RNM as it is difficult to pull down the 1node. This is so because with an increase in the width ofthe pFinFET, its resistance decreases and hence the poten-tial drop. With an increase in width of the access FinFET,the drop across it decreases, making it difficult to pull upthe node 0, thus resulting in an increase in RNM. FurtherWNM decreases with an increase in the width of load Fin-FET. As the width increases, its current driving capabil-ity also increases. It makes the node Q vary more closelywith V D as compared to the BL and hence, there is a de-crease in WNM. For an increase of 70 nm of width of loadFinFET, there is a 32% fall in WNM for 30 nm technology.

Variations of WNM and RNM with the driver FinFETare shown in Figure 7. During write cycle, the write fail-ure is said to occur if the bitline is unable to write 0 inthe node 1. Write Noise Margin denotes the voltage thatmust be added to the node 1 during the write cycle forwrite failure to occur. In this case, the nodal voltage isdetermined by the access and the load FinFETs which

Figure 4. SNM variations with width of Ioad.

800

700

600

500

400

300

200

100

00 100 200 300 400 500 600 700 800

V R

( m V )

VL (mV)

WP

Figure 6. WNM and RNM variation with width of loadFinFET.

50

55

60

65

70

75

8085

150 160 170 180 190 200 220210Width of Load FinFET (mm)

W N M ( m V )

20

2422

26

283032

3436

R N M ( m V )

WNMRNM

WAccess = 64 nmWDrive = 128 nm

Figure 7. WNM and RNM variation with width of driverFinFET.

50

55

60

65

70

75

8085

100 110 120 130 140 150 160Width of Driver Transistor (nm)

W N M ( m V )

18

23

28

33

38

43

R N M ( m V )

WNMRNM

WAccess = 64 nmWLoad = 192 nm

800

600

400

200

00 200 400 600 800

V R

VL

W DD

Figure 5. SNM variations with width of driver.


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forms a potential divider. A stronger load FinFET and/or a weaker access FinFET make it difficult for the datato be flipped at the node storing 1 initially and henceWNM goes down. The RNM increases with width of driv-er FinFET. Larger the width of the driver FinFET, easilyit can pull down the node voltage at Q which results inincreased RNM. Figures 8.a and b show the variation ofstatic power with varying width of driver FinFET and loadFinFET, respectively. It can be seen from the figure thatthe static power dissipation increases with an increase inwidth of both driver as well as load FinFET. As the widthincreases so does the total current flow to the deviceresulting in largest power dissipation. Figures 9.a and bshow the Monte Carlo simulation results for RNM andWNM to quantify the effect of process variation arisingdue to variation in FinFETs widths. The simulation wascarried out for 1000 values, assuming 3 s equal to 10%

of the mean value. Tables 2.a and b show the mean andstandard deviation values for RNM and WNM variation.

In our proposed FinFET model, we have assumed theentire fin extension regions doped with a concentrationof 10 26 m 2 3. The silicide implants could be modeled withundoped extension regions after exploring the currentdistribution using device simulators, but we have ne-glected these implants. The source/drain regions havebeen assumed to be doped with a density of 10 26 m 2 3.Figure 10 shows the on and off drain current with vary-ing values of L ext . It was attempted to optimize the L ext for

the best I ON / IOFF ratio with I ON measured for V G5

0.8 V.However, as the graph shows the trend was found to

be monotonously decreasing. Also it has been shownthat symmetrical extension regions offer the best per-formance. The L ext was arbitrarily assumed to be 64 nmon each side for all the simulations. It has been realizedthat for the underlapped FinFET, because of the seriesresistance at the source side, the net voltage availableto invert the channel is now lesser. Thus, it is expectedthat the drain current has been decreased for the samegate voltage compared to the normal PTM based FinFET.

The underlapped FinFET model obtained after theinsertion of the parasitics into the PTM model is shown

Figure 8. Static Power variation with width of (a) load and(b) driver FinFET.

5354

55

56

57

58

59

115 120 125 130 135 140Width of Driver FinFET (nm)

P o w e r

( n W )

53

54

55

56

57

58

59

170 175 180 185 190 195 200 205 210Width of Load FinFET (nm)

(a)

(b)

P o w e r

( n W )



Figure 9. Variations and distribution of (a) RNM and(b) WNM.

350

300

250

200

150

100

50

022 24 26 28

RNM (mV)

N u m

b e r o f

O c c u r r e n c e

30 32 34 36

500

450

400

350

300

250

200

150

100

50

065 70 75 80

WNM (mV)

(a)

(b)

N u m

b e r o f

O c c u r r e n c e

85 90 95 100

Nominal W Access = 64 nmNominal W Driver = 128 nmNominal W Load = 192 nm

Gaussion Model for Load VariationMonte Carlo for Load VariationGaussion Model for Driver VariationMonte Carlo for Driver VariationGaussion Model for Access VariationMonte Carlo for Access Variation


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figure 11. The parasitic capacitances have been lumpedto the gate. Two fictitious terminals have been added atthe gate and the source side. The parasitic series resis-tances have been added between these terminals andthe actual source/drain terminals of the original model.

In this way, the net voltage at the source/drain of theoriginal model is reduced because of the resistive dropacross the series parasitic resistances. Table 3 summa-ries the parameters of the underlapped FinFET deviceused for the simulations.

In our simulations, it was observed that the SNMwas relatively insensitive to variations in widths ofdriver and load FinF ETs for both the PTM model andthe modified underlapped. Figures 12.a and b showthe Monte Carlo results for RNM of PTM based Fin-FET and underlapped FinFET respectively. It is evi-dent that both the designs are most susceptible tovariations in width of access FinFET as the graphsshow greatest variation around the nominal value.The mean value of RNM for the PTM FinFET modelbased SRAM is however higher than that of the under-lapped FinFET model for all the cases. This is primar-ily due to the fact that because of the introduction

Figure 10. Variation of I ON and I OFF with Fin extensionlength (L ext ).

W = 256 nm

Ioff (nA) Ion (A) Ion /Ioff

706050403020

100

5 10 15 20 25 30Fin Extension Length L ext (nm)

D r a

i n C u r r e n t

( n A )

Figure 11. Underlapped FinFET derived from PTM model.

Drain PTM Model SourceFictitiousSource

FictitiousDrain

Back Gate

Front Gate

ParasiticResistances

ParasiticResistances

ParasiticCapacitances




Table 3.Parameters for the underlapped FinFET device.

Parameters ValuesLeff 32 nmLext 64 nm

Tfin 8.6 nmtox 1.4 nmNS/D 1026 m

2 3

Nchannel Intrinsic (Si)Wg < (2tpoly 1 Tfin 1 2tox) 76 nmtpoly 32 nm

Table 2.a.Mean and standard deviation of RNM Monte Carlo analysis.

Load Driver Access All W

Mean (mV) 28.8394 28.8461 28.7201 29.0572

StandardDeviation (mV) 1.2505 1.3389 2.5833 3.2620

Table 2.b.Mean and standard deviation of WNM Monte Carlo analysis.

Driver Load Access All W

Mean (mV) 82.6377 82.6057 82.8486 66.7410

StandardDeviation (mV) 2.3682 2.9959 5.3513 5.9785


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of the series resistance, the voltage after the channelto the source region gradually goes to zero owing tothe ohmic drop across the extension region. Thus incase of RNM, the voltage at the storing 0 logic is notzero but infact has some nonzero value. This voltageoffsets the RNM as lesser noise voltage would be able

to flip the state of the cell during read cycle now. Con-sequently the RNM decreases.

Table 4 summarizes the mean and standard deviationof RNM for the Monte Carlo simulations with varyingwidths of driver, load and access FinFETs. An importantobservation that can be made is that the sigma valueis lesser for the variation corresponding to FinFET hav-ing larger nominal value of width. This presents a newdesign challenge as a new tradeoff has been identified.This line of reasoning is seconded by the fact that thedeviation is maximum for the access variation which

infact has the least width amongst the three FinFETs.Another interesting observation is that the deviation forthe underlapped FinFET case is lesser in all the threecases. This is attributed to the fact that the relative im-pact of FinFET width variation has been toned downwith the introduction of the series resistance due to thefin extension regions. The relative change in drain cur-rent is now lesser and hence the relative impact on themetric is also lesser.

Similarly Figures 13.a and b show the results of pro-cess variations for WNM with the FinFET widths. It isobserved that while RNM was more sensitive to driverFinFET width variation, WNM is more sensitive to loadFinFET width variation. However as expected WNM ismost sensitive to variation in access width because ofits minimum size. The WNM is found to decrease in theunderlapped device. This is because of the resistivedrop across the load FinFET such that the effective volt-age value for logic 1 is less than 0.8V. This is equivalentto scaling of V D which results in decrease of WNM. Thesigma and the mean values of the WNM are compiled inTable 5.

In case of FinFET based SRAM array, most of the

cells are in idle state for a large portion of operationperiod. Hence static power consumption contributesto majority of the power dissipation. Figure 14 showsthe dependence of static power with temperature foroverlapped and underlapped FinFET based SRAM cellrespectively. Since subthreshold current is the domi-nant source of leakage for FinFETs and it increasesexponentially with temperature, the static power alsoincreases exponentially.

As the temperature increases, the leakage current in-creases exponentially and causes reduction in the I on /

Ioff ratio. This decreases the sub threshold slope andhence the voltage swing. As a result, the SNM and RNM

Table 4.Mean and standard deviation values of RNM with variationin FinFET widths.

Driver Load AccessRNM with PTMModel (mV)

Mean 28.8461 28.8394 28.7201Std. Dev. 1.3389 1.2505 2.5833

RNM withUnderlappedModel (mV)

MeanStd. Dev.

25.11671.0674

25.07070.0605

25.0461.1123

Figure 12. Monte Carlo results for variation of RNM withload, driver and access FinFET widths for (a) PTM model(b) Underlapped model (with Fin extension regions).

350

300

250

200

150

100

50

022 24 26 28

RNM (mV)

N u m

b e r o f

O c c u r r e n c e

30 32 34 36

800

700

600

500

400

300

200

100

0

22 23 24 25RNM (mV)

(a)

(b)

N u m

b e r o f

O c c u r r e n c e

26 27 28




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of the FinFET SRAM cell decrease. As the voltage swingdecreases, it becomes easier to flip the voltage at the

nodes. Hence the amount of voltage required to causewrite failure increases resulting in increase in WNM of

the cell. Figure 15 shows the variation of SNM, RNM andWNM with increase in on-chip temperature for the PTMmodel of FinFET device.

VIII. ConclusionIn this paper, we have analyzed different tradeoffs in-volved in the design of FinFET based SRAM and opti-

mized the performance of the cell for robustness. Theanalysis of SNM, RNM, WNM and static power variationwith width of access, load and driver have been carriedout. Further, the effect of process variation on the SRAMcell performance was analyzed using Monte Carlo simu-lation on HSPICE. The performance of a 6T FinFET basedSRAM cell was analyzed using HSPICE CAD tool. Twostructures of the FinFET viz. the standard PTM modeland an underlapped FinFET have been used for the sim-ulations. It was identified that while the relative levels ofthe noise margins were lower for the underlapped case,

the standard deviation was considerably lower too. Itwas also found that smaller FinFET widths give rise to

Table 5.Mean and standard deviation value of WNM with variation in

FinFET widths.

Driver Load AccessWNM PTMModel (mV)

Mean 82.6377 82.6057 82.8486Std. Dev. 2.3682 2.9959 5.3513

WNMUnderlappedModel (mV)

MeanStd. Dev.

35.37191.1045

35.36481.6279

35.47852.7287

Figure 13. Monte Carlo results for variation of WNM withload, driver and access FinFETs widths for (a) PTM model(b) Underlapped model (with Fin extension regions).

350400450500

300250200150100

50065 70 75 80

WNM (mV)

N u m

b e r o f

O c c u r r e n c e

85 90 95 100

400

350

300

250

200

150

100

50

028 30 32 34 36

WNM (mV)

(a)

(b)

N u m

b e r o f

O c c u r r e n c e

38 40 42 44



Figure 14. Effect of Temperature Variation on Static Pow-er for PTM FinFET model and Underlapped FinFET modelSRAM.

12

10

8

6

4

2

0

P o w e r

( n W )

20 40 60 80 100Temperature ( C)

Underlapped FinFET SRAMOverlapped FinFET SRAM

WLoad = 192 nmWDriver = 168 nmWAccess = 64 nm

Figure 15. Effect of temperature variation on static noisemargin, read noise margin and write noise margin for PTMFinFET model.

Temperature ( C)

N o i s e

M a r g i n

( m V )

WLoad = 192 nmWDriver = 168 nmWAccess = 64 nm

W oa = 192 nmWDriver = 168 nmW ccess = 4 nm

160

140120

100

80

60

40

20

020 30 40 50 60 70 80 90

WNM (mV) SNM (mV) RNM (mV)


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larger deviations than larger ones. Thus in future FinFETSRAM based on minimum FinFET width, would be proneto process variations. The temperature dependence ofnoise margins and static power was also observed forFinFET based SRAM. While SNM and RNM decreasedwith increasing temperature, WNM increased. Since the

stability of the FinFET based SRAM cell in the idle stateis the most important metric, temperature effects haveto be accounted for in design of memory circuits.

Balwinder Raj born in Pathankot acity in Punjab, India on 30th November1980. He did B. Tech. in Electronics & In-strumentation Engineering from AdeshInstitute of engineering and Technology,Faridkot, Punjab, M. Tech in Microelec-tronics from Panjab University, Chan-

digarh and Ph.D in Semiconductor Devices and VLSITechnology (SDVT) from Department of Electronics andComputer Engineering, Indian Institute of Technology,Roorkee (IITR), India in 2004, 2006 and 2009 respec-tively. For further research work, European Commis-sion awarded him Erasmus Mundus Mobility of liferesearch fellowship for postdoc work at University ofRome, Tor Vergata, Italy in 2010. He is working as Assis-tant Professor at University of Engineering and Technol-ogy, Guna, M.P. His areas of interest in research are Clas-sical/Non-Classical Nanoscale Device Modeling, FinFETbased Memory design, Low Power VLSI Design, DigitalVLSI Design, and Circuits for future VLSI Technology.He has authored/co-authored more than 20 researchpapers in peer reviewed international journals and con-ferences. He is a Member of IEEE, Life member of IndianMicroelectronics Society (IMS), Chandigarh, India andassociate member of Institute of Nanotechnology, UK.His biography published in Marquiss Whos Who in En-gineering Field, USA awarded by Marquis, 2009. He hasalso been member of technical committees of variousnational/international conferences. Dr. Raj is Editorialboard member of Journal of Computers (JCP), Academy

Publisher. He is also a reviewer for IEEE Transaction onVLSI Systems, IEEE Transaction on Circuits and Systems-I,

IEEE Electron Devices Letter and Journal of SemiconductorTechnology and Science .

A.K. Saxena born on July 1st, 1950at Rampur (UP, India). Dr. Saxena ob-tained M.Sc. from Agra University in1969 with third rank in undivided AgraUniversity, M.Sc.(Tech.). from Depart-ment of Electronics and Electrical

Engg., B.I.T.S. in 1971 with first rank,M.Engg. and Ph.D. from Department of Electronics and

Electrical Engg., UMIST/Sheffield University (UK) in1975 and 1978, respectively as one of the two Govern-ment of India National Scholars. Served CEERI, a sisterlaboratory of CSIR from 197274 working on semicon-ductor device technology and then served Universityof Roorkee (Now IIT-Roorkee) as Reader from 197888.

Since 1988, he is a Professor in Solid State Electronicsand VLSI Technology. He has also spent a year with Stan-dard Telecommunication Laboratory (London) work-ing on III -V compound characterization under pressure.Dr. Saxena is a member of Overseas Advisory Boardof IEICE Transactions of Electronics of Japan since1992. He is also a Fellow, Honorary Editor and Mem-ber Editorial Board of IETE, one of the three Fellowsin semiconductors from India of Institute of Physics(London) and Chartered Physicist of Institute of Phys-ics (London), Fellow of IET (Formaly IEE) UK, Fellow

of IETE, IE, IMS and SMIEE. The discovery of a level inGaAlAs is christened as Saxenas Deep Donor by Phil-ips Research Laboratory, Eindhoven (Netherlands).He is also a winner of INSA Young Scientist, RoorkeeUniversity Khosla Award Gold Medal, Kothari Scien-tific Research Institute Award, S. K. Mitra MemorialAwards (twice) of IETE and Bharat Excellence Award.He is also a member of Research Board of Advisors ofABI (USA). He has also been honored with the title ofMan of the Year by ABI (USA) and IBC (UK). He is a lsoan expert member on many National Committees andreferee for international journals/conferences. Dr. Sax-ena has visited several countries viz., UK, USA, Japan,Australia, Romania and Thailand. He has also been aRoyal Society (London) INSA visiting fellow and SERC(UK) senior visiting fellow at University of Surrey (UK).He was also awarded visiting fellowship by Universityof Michigan (USA). He has published about 175 re-search papers in international journals and conferenceproceedings with very high citation index of about 775so far. He has also been Investigator-in-charge of sev-eral projects from DST, INSA, CSIR, UGC, etc. He alsoreceived financial assistance from NTT (Japan), IMT

(Romania), DST, INSA, AICTE, DOE, UP Govt., Ministryof Education & Social Welfare and UOR/IIT for attend-ing conferences abroad. Some of his research workhas been included in books published from USA andGermany. His biography has been published in a largenumbers of publications from U.K., U.S.A., Malaysiaand India. Dr. Saxena has supervised many Ph.D./M.E./M.Tech./M.Phil. theses in the area of VLSI design, metal-semiconductor ohmic and non-ohmic contacts, bandstructure and deep energy levels of GaAs, GaAlAs, GaP,InP, etc and quantum wells under pressure. He has also

written AICTE sponsored nine volumes on the relatedsubjects for working professionals.


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S. Dasgupta is presently Assistant Pro-fessor, in the Department of Electron-ics and Computer Engineering at IndianInstitute of Technology, Roorkee. Hereceived his PhD degree from BanarasHindu University, India in 2000. During

his PhD work, he carried out researchin the area of effects of ionizing radiation on MOSFET.Subsequently he was member of faculty of Departmentof Electronics and Instrumentation at Indian School ofMines, Dhanbad. In 2006, he became Assistant Profes-sor in the Department of Electronics and Computer En-gineering at Indian Institute of Technology, Roorkee. Hehas authored/co-authored more than 90 research papersin peer reviewed international journals and conferences .He is member IEEE, EDS, ISTE and associate member ofInstitute of Nanotechnology, UK. He has been a technical

committee member International Conference on Micro-to-Nano, 2006; he is also been nominated as Marquiss WhosWho in Science in Engineering, USA awarded by Marquis,2006, 2007 and 2008 and has been acting as an expertmember of The Global Open University, The Netherlands.His areas of interest are Nanoelectronics, NanoscaleMOSFET modelling and simulation, Design and develop-ment of low power novel devices, Digital VLSI Design.Dr. Dasgupta also acted as a reviewer for IEEE Transactionson Nanotechnology, Superlattice and Microstructures, Inter- national Journal of Electronics, Semiconductor Science andTechnology, Nanotechnology and IEEE Transactions on VLSI

Systems . He has also been member of technical commit-tees of various international conferences.

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