HW/SW co-simulation within the MODUS toolset

MODUS Project FP7- SME – 2011- 286583, Eclipse Conference Toulouse, May 6th 2013 Page 1

MODUS Project FP7- 286583

Methodology and Supporting Toolset Advancing Embedded Systems Quality

Eclipse ConferenceToulouse, May 6th 2013

HW/SW co-simulation within the MODUS toolsetHW/SW co-simulation within the MODUS toolset


An independant SME founded in 1999, performing research and engineering in radio navigation and applications

Activities include but not restrained to:Radio navigation technical studiesAirport applicationsCritical transportations…

Implied in several national and

European projects.

M3Systems: Leading SME in radionavigationM3Systems: Leading SME in radionavigation


SummarySummary

MODUS project and toolset

Principle and objectives

HW/SW co-simulation workflow

HW/SW co-simulation environment

HW/SW co-simulation demonstration


SummarySummary







MODUS project and toolsetMODUS project and toolset

MODUS aims to help SMEs to substantially improve their positioning in the embedded-systems development market

MODUS is a set of open and customizable methodologies including: Model verification by guiding the selection of existing open-source model verification engines Interfacing with standard simulation platforms for HW/SW co-simulation Software performance-tuning optimization through automated design transformations Customizable source-code generation towards respecting coding standards and conventions

MODUS does not aim to be competitive with the vendors of CASE tools that are presently used in embedded software engineering, but to bring the technology to SMEs.


SummarySummary






Rely on an efficient and fast way to perform the steps of the iterationThe actual implementation of the methodology usually relies on design, simulation, and analysis, of software models of systems i.e.

Virtual Platforms


Principle and objectivesPrinciple and objectives

Embedded systems design complexity is growing exponentially with more integrated applications and feature



Y-Chart approach

Rely on an efficient and fast way to perform the steps of the iterationThe actual implementation of the approach usually relies on design, simulation, and

analysis, of software models of the system i.e. Virtual Platforms

Architecture Application

System

Analysis

Changes in architecture

Changes in application

Mapping

Clear separation between architecture

and application

Iterative


MODUS approach


“Executable”System

Co-simulation



Mapping

Architecture Application

Model of the architecture

Model of the application

Virtual Platform

Software binary

High level modelling of architecture

Generation of Virtual Platform


SummarySummary







Virtual Platforms


MODUS full HW/SW co-simulation workflow:

Define the hardware architecture Model the architecture using UML Generate the SystemC virtual platform Complete and configure the virtual platform Generate the executable virtual platform Integrate the SW Binaries in the platform Co-simulate the executable system Change the architecture if needed Re-iterate

HW/SW co-simulation workflowHW/SW co-simulation workflow

GeneratedVirtual

Platform

SWBinary

“Executable”System

Co-simulation

Model of the architecture

Virtual Platform

ExecutableVirtual

Platform

Embedded system

Embedded system

HW

Embedded system

SW



Architecture modelling

Virtual Platform generation

Virtual Platform completion and configuration

Virtual Platform compilation

Mapping

MODUSsoftware

design flow



Architecture modelling using UML Marte

Structure composite diagram with restrictions on constructs A system is modelled as a set of components interconnected through ports to a bus.

Class stereotyped with a subset of MARTE HwLogical stereotypes and some of their properties

HwProcessor , HwBus (latency), HwRAM (latency, size), HwIO, HwDevice, HwEndPoint



Virtual Platform generationSystemC : C++ library for systems modelling, which includes a simulation kernel.

Modules, ports, channels, processes, events, specific datatypes…

TLM2.0 : Extension to SystemC with the purpose to abstract communications with high level transactions. Suited for the modelling of memory-mapped bus systems.

Generic payload, sockets… supporting two coding styles : Loosely Timed and Approximately Timed.

ModuleModule

Channel

Port Port

Interface

Process Process

TargetInitiator

Initiator socket

Target socket

Interconnect

Target socket

Initiator socket

Socket binding



Virtual Platform generation

Generation of a Loosely-Timed virtual platformModules are generated as skeletons to be completed by MODUS users (except Bus and Memories (SRAM), as well as a set of probes).

MemoryProcessor

simple_initiator_socket

Bus

I/O Device

simple_target_socket

Probes


SummarySummary







Virtual Platforms



Built over the Eclipse framework as a set of specific plug-ins

Eclipse plug-ins

HW/SW co-simulation environmentHW/SW co-simulation environment

Generation engine

Acceleo

Completion and configuration

Eclipse

Graphical UML modeller

MDT Papyrus

UML MARTE model

Generated SystemC virtual

platform

Configured SystemC virtual

platform

Compilation with external tools:

Eclipse CDTVisual Studio

…


SummarySummary







Virtual Platforms


Virtual platform demonstrationVirtual platform demonstration

Completely generated modules Memory PLBBus

Generated modules, but completed and configured by the user

MicroBlazeUART Acquisition and trackingPositining

“Data transfer” software compiled using Xilinx tools and loaded into the virtual platform memory


Than you for your attention!Than you for your attention!

Yann Leclerc

R&D Engineer – M3 Systems

Tel: +33 5 62 23 10 84

Fax: +33 5 62 23 10 81 email: [email protected]

Chafic Jaber, PhD

Research Engineer – M3 SystemsTel: +33 5 62 23 10

Fax: +33 5 62 23 10 81 email: [email protected]

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HW/SW co-simulation within the MODUS toolset

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