HW/SW SystemC Co-Simulation SoC Validation

PlatformThomas Schuster

Outline

1.Introduction TU Braunschweig/IDA

2.Study Objectives & Organization3.Virtual Platform Infrastructure4.Development of TLM 2.0 Simulation Models5.Proof-of-concept VP

1. TECHNISCHE UNIVERSITÄTBRAUNSCHWEIG

14.000 Students 3.000 University staff 1.600 Scientists 5 Departments 40 Degree Programs

Founded in 1745(oldest university of technology in Germany)

School of Carl-Friedrich Gauß

IDA Institute of Computer and Communication Network Engineering

Institute of Computer and Communication Network Engineeringdirector: Prof. Rolf Ernst

communication networks

Prof. Admela Jukan

cryptography

Prof. Wael Adi

computer aided

embedded system design

Prof. RolfErnst

•ca. 60 employees (21 univ. funded)•ca. 2.2 Mio. € 3rd party funding in 2006•part of department of EE&IT

•ca. 60 employees (21 univ. funded)•ca. 2.2 Mio. € 3rd party funding in 2006•part of department of EE&IT

embedded computers for space

applications

Prof. Harald Michalik

staffsystem

administrationsecretariat accountingelectronic

labmechanical

lab

VLSI systems design

Prof. Mladen Berekovic

sponsored by Intel

People involved

IDA:Prof. Dr. Harald Michalik Study ManagementProf. Dr. Mladen Berekovic Chief Technical Scientist

Thomas Schuster Study EngineerDennis Bode Study EngineerBjoern Osterloh Study Engineer

ESA Supervisors:Dr. Luca FossatiDr. Laurent Hili

2. Project Objectives

• High-Level modeling of key IPs in TLM 2.0• Functional validation and timing

accuracy analysis• Power Modeling

• Definition of a design flow for VP modeling• Selection of appropriate infrastructure • Development of a proof-of-concept Virtual Platform• Demonstration of a design space exploration

www.vlsilab.org

Study Organization

today

Jan 2010

July 2011

Virtual Platform / Advantages

A Virtual Platform is an abstract hardware model that is simulated by software.

Productivity Availability

Accessibility Consistency

Software development can start before hardware prototypes are

available.

VPs can easily be duplicatedand packaged allowing multiple developers to work in parallel.

Unlike physical hardware VPs provide observability and controllability for the entiresystem.

VPs can be co-simulated/emulated. Gradual

refinement from high abstraction to RTL eases verification.

3. Selection of VP InfrastructureRequirements:

• Open Source (GPL, L-GPL)• Support for TLM 2.0 (LT and AT)• Concept for development of:

- memory mapped devices- complex bus models

• Vendor tool independence

System shall be developed around TRAP (Transaction level Automatic Processor generator)http://code.google.com/p/trap-gen/

Survey on Tools & Techniques VPI Originated by License Pros Cons

Coware Virtual Platform

Coware Inc. Com+ runtime

Sophisticated, Processor Designer,in-house expertise

expensive

Carbon SoC Designer Carbon Design Systems Com+ runtime

Sophisticated,Model Compiler

expensive

OVP Imperas semi-com TLM 2.0 compliant,large open component lib, widespread

simulator not open-source

SOCLIB ANR project(ST, Thales, …)

GPL Widespread, large community

no TLM 2.0

UNISIM HiPEAC projectINRIA

BSD Existing component library no TLM 2.0contrib. slow down

ReSP ESA projectPolitecnico di Milano

GPL Existing components (LEON), ESA affiliation

no TLM 2.0contrib. low

GreenSocs GreenSocs Ltd. GPL TLM 2.0, TU-BS expertise -

Open Tools for TLM 2.0 are hard to find.

is closest to requirements

Mission:• Provision of vendor-independent infrastructure• Open platform for joint IP development

Infrastructure (selected):

GreenBus - Foundation for Bus Modeling with TLM 2.0(incl. AMBA impl. almost ready-to-use)

GreenReg - Framework for Register & Device ModelingGreenControl - Control and Configuration Interfaces (CCI)GreenScript - Methods and Tools for Use-Case capture

… and much more, see: www.greensocs.com

GreenSocs System Overview

Source: Mark Burton, GreenSocs

4. Modeling of SystemC IP

No. IP

1 AMBA AHB

2 Aeroflex Gaisler GRLIB MCTRL Memory Controller

3 A memory model working with IP 2

4 A Harvard L1 cache

5 A SPARCv8 MMU or equivalent

6 Aeroflex Gaisler GPTIMER General Purpose Timer

7 Aeroflex Gaisler IRQMP Interrupt Controller

Models will be implemented in LT and AT flavor of TLM 2.0

Transaction Level Modeling

Function calls through dedicated interfaces model synchronization of concurrent threads of execution.

Accu

racy

Sim

ulati

on P

erfo

rman

ce

TLM 2.0 Loosely Timed (LT) – blocking communication, temporal decoupling

TLM 2.0 Approximately Timed (AT)– non-blocking communication 2 Phase AT (begin request, end response) 4 Phase AT (begin/end request, begin/end response) n Phase AT

Cycle Accurate SystemC or RTL simulation

GreenRegGreenReg

Device Modeling with GreenReg

Protocol(Socket)Protocol(Socket)

Example Slave Module

Register SetRegister Set User ModelUser Model

RegfileRegfilecallbackscallbacks

behaviortimingpower

behaviortimingpower

regregreg

regregreg

• Registers can be automatically hooked on sockets• Registers provide Pre/Post Read/Write callbacks to behavior

Verification of IP Models

test vectorstest vectorstest vectorstest vectors

TLM Stimuli/MonitorTLM Stimuli/Monitor

TLM Design Under Test

TLM Design Under Test RTL

Design Under TestRTL

Design Under Test

AMBAAMBAAMBAAMBA

TLM/RTL AdapterTLM/RTL Adapter

Reference Simulation (TLM/RTL) Full TLM Simulation

Models will be evaluated with respect to simulation performance & accuracy.

5. Proof-of-Concept VP

AeroflexGPTimerAeroflexGPTimerAeroflex

GPTimerAeroflexGPTimerAeroflex

GPTimerAeroflexGPTimer BridgeBridge BridgeBridge

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

LEON3LEON3

CacheCache

MMUMMU

MEMMEM MemMemAeroflexGPTimerAeroflexGPTimer

AeroflexGPTimerAeroflexGPTimerAeroflex

GPTimerAeroflexGPTimerAeroflex

GPTimerAeroflexGPTimerAeroflex

GPTimerAeroflexGPTimer

AeroflexIRQMP

AeroflexIRQMPMEMMEM

Aeroflex

MCTRL

Aeroflex

MCTRL

Status/Ctrl RegsStatus/

Ctrl Regs

MEMMEM

CANCAN SpaceWireSpaceWire SoC WireSoC Wire

AMBAAMBAAMBAAMBA

AMBAAMBA

Multi-Processor system stimulating all IPs generated in the course of the project.

Segmented AHB2x4 LEONprocessors

Platform Software Architecture

Open Source Software Architecture:

A set of MiBench applications will be executed on top of RTEMS:

OS

Compiler

Real-Time Executive for Multi-processor Systems

GNU Compiler CollectionEmbedded C library+

HW/SW SystemC Co-Simulation Platform

Thank you for your attention!