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HY425 Lecture 15: DRAM Technology - University of Cretehy425/2012f/lectures/lecture15...DRAM basics...

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DRAM basics Advanced DRAM technology Virtual memory HY425 Lecture 15: DRAM Technology Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS December 2, 2011 Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 1 / 34 DRAM basics Advanced DRAM technology Virtual memory DRAM Fundamentals Random-access memory using one transistor-capacitor pair per bit Capacitors leak, needs refresh Composed of one or more memory arrays Organized in rows and columns Need sense amplifiers to compensate for voltage swing Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 3 / 34
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Page 1: HY425 Lecture 15: DRAM Technology - University of Cretehy425/2012f/lectures/lecture15...DRAM basics Advanced DRAM technology Virtual memory HY425 Lecture 15: DRAM Technology Dimitrios

DRAM basicsAdvanced DRAM technology

Virtual memory

HY425 Lecture 15: DRAM Technology

Dimitrios S. Nikolopoulos

University of Crete and FORTH-ICS

December 2, 2011

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 1 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

DRAM

Fundamentals

I Random-access memory using one transistor-capacitorpair per bit

I Capacitors leak, needs refreshI Composed of one or more memory arrays

I Organized in rows and columnsI Need sense amplifiers to compensate for voltage swing

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 3 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

DRAM cell

Memory array

Sense amplifiers

Column decoder

Data in/out buffers

Row

dec

oder

…columns…

…ro

ws…

bit line

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 4 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

DRAM

Fundamentals

I Each DRAM memory array outputs one bitI DRAMS use multiple memory arrays to output multiple bits

at a timeI ×N indicates DRAM with N memory arraysI ×16, ×32 DRAMS typical today

I Each collection of ×N arrays forms a DRAM bankI Banks can be read/written independently

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 5 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

×4 DRAM

Memory array

Sense amplifiers

Column decoder

Data in/out buffers

Row

dec

oder

bit line Memory array

Sense amplifiers

Column decoder

Data in/out buffers

Row

dec

oder

bit line Memory array

Sense amplifiers

Column decoder

Data in/out buffers

Row

dec

oder

bit line Memory array

Sense amplifiers

Column decoder

Data in/out buffers

Row

dec

oder

bit line

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 6 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Interleaved DRAM

DRAM memory bandwidth

I Limited bandwidth from one DRAM bankI Increase bandwidth by delivering data from multiple banks

I Processor DRAM interconnect (e.g. bus) with higher clockfrequency than any one DRAM

I Bus control switches between multiple DRAM banks toachieve high data rate

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 7 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

DIMMs and Ranks

Memory array Memory array Memory array Memory array

Ι/Ο

ΜUX

One DRAM, eight internal banks, shared I/O link

one bank, x4 array

One DIMM, with one DRAM rank

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 8 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Modern DRAM organization

Hierarchy of DRAM memories

I A system has multiple DIMMsI Each DIMM has multiple DRAM devices in one or more

ranksI Each DRAM device has multiple banksI Each bank has multiple memory arraysI Concurrency in ranks and banks increases memory

bandwidth

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 9 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Processor–DRAM interconnect

I BusesI Address/command linesI Data lines (wide, >= 64 bits in leading processors)I Chip select lines

I Recent systems adopt increasingly more scalablesolutions

I Point-to-point, crossbar interconnectsI Hypertransport, Intel CSI/QuickPath

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 10 / 34

DRAM basicsAdvanced DRAM technology

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Processor–DRAM bus organization

Mem

ory

cont

rolle

r Address/command bus

Data bus

Chip select 1

Address/command bus

Data bus

Chip select 2

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 11 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Memory controller

Controller operation

I Device executing processor memory requestsI Separate off-processor chip in earlier systemsI Integrated on-chip with the processor in modern systemsI Bus, point-to-point, crossbar interconnect with processor

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 12 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Lifetime of a memory access

Steps in memory access

1. Processor orders and queues memory requests2. Request sent to memory controller3. Controller queues and orders requests4. For request in head of queue, controller waits until

requested DRAM ready5. Controller breaks address bits into rank, bank, bank row,

bank column fields6. Controller sends chip-select signal to select rank7. Selected bank at selected rank precharged to activate

selected row

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 13 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Lifetime of a memory access

Steps in memory access

8. Activate row in DRAMs of selected bank in selected rankI Use RAS (row-address strobe signal)

9. Send entire row to sense amplifiersI Sense amps may already have a valid row

10. Select desired column using CAS (column-address strobe)

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 14 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Asynchronous DRAM timing

row address

column address

valid data out

row address

column address

valid data out

RAS

CAS

Address

Data

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 16 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Fast Page Mode

I Allow row to remain available (open) for multiple columnaccesses

I Holds row data in sense amplifiers for longer periodI Memory controller holds RAS signal while changing CAS

signalI Sense amplifiers function as ”cache” for DRAM rowsI Multiple CAS signals can access multiple words in same

rowI Exploits spatial locality via successive accesses to same

row

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 17 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

FPM DRAM timing

row address

column address

valid data out

column address

column address

valid data out

RAS

CAS

Address

Data

Overlap Overlap

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 18 / 34

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DRAM basicsAdvanced DRAM technology

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EDO DRAM

I Adds latches to FPM DRAM to permit rapid CASdeassertion

I Accelerates precharging for outputI Latches allow also row in output to remain valid longerI 10%–15% shorter access time than FPM

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 19 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

EDO DRAM timing

row address

column address

valid data out

column address

column address

valid data out

RAS

CAS

Address

Data

Overlap

column address

valid data out

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 20 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Burst mode EDO DRAM timing

row address

column address

valid data out

valid data out

RAS

CAS

Address

Data valid data out

valid data out

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 21 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Synchronous DRAM

I Asynchrony in DRAM due to RAS and CAS signals arrivingat any time

I Synchronous DRAM uses clock to deliver requests atregular intervals

I More predictable DRAM timingI Less skew, faster turnaround on requestsI Synchronous DRAMs support burst mode accessesI Initial performance similar to BEDO DRAMI Clock scaling enabled higher performance later

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 22 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Rambus DRAM (RDRAM)

I Fully multiplexed, narrow bus replaces, control, data,address bus

I 8-bit bus at 250 MHz, delivers 500 MB/sI Split request-response protocol resembling network

protocols

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 23 / 34

DRAM basicsAdvanced DRAM technology

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Concurrent Rambus DRAM

I Split bus into address, command and data segmentsI 1-byte data segment, 1-bit address segment, 1-bit control

segmentI Later extended to 2 bytes data, 5 bits address, 3 bits controlI Frequency also increased to 500 MHz

I Perform simultaneous command, address, data transmiton bus

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 24 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Modern DRAM designs

I Double Data Rate (DDR) SDRAMI Double data transfer rate by transferring at both clock edgesI Otherwise almost identical to single data rate DRAM

I Virtual Channel Memory SDRAMI Adds a real cache (SRAM) to buffer large data blocksI Increased read/write latency on miss

I Fully Buffered DIMMI Channel speed improving at the expense of channel

capacityI Memory controllers on DIMMSI Replace shared bus with point-to-point connections

between controllers and DRAMsI Higher storage capacity without sacrificing bandwidth

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 25 / 34

DRAM basicsAdvanced DRAM technology

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Virtual Memory 101

Why VM?

I Share a physical address space among many processesI Providing protection between processesI Handle efficiently processes with sparse address spacesI Load physical memory on-demandI Load programs anywhere in physical memory (relocation)I Run programs too large to fit in physical memory

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DRAM basicsAdvanced DRAM technology

Virtual memory

Virtual Memory 101

VM terminology

I Page or segment correspond to blockI Pages are fixed-size, segments are variable-size blocks

I CPU produces virtual addresses translated to physicaladdresses

VM versus caches

I Replacement controlled by operating system versushardware

I Memory miss penalty huge compared to cache misspenalty

I Makes replacement decision extremely important

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 28 / 34

DRAM basicsAdvanced DRAM technology

Virtual memory

Cache vs. VM parameter comparison

Parameter First-level cache Virtual memoryBlock (page) size 16–128 bytes 4096–65,536 bytesHit time 1–3 clock cycles 50–150 clock cyclesMiss penalty 8–150 clock cycles 1,000,000–10,000,000 clock cycles(Access time) (6–130 clock cycles) (800,000–8,000,000 clock cycles)(Transfer time) (2–20 clock cycles) (200,000–2,000,000 clock cycles)Miss rate 0.1–10% 0.00001–0.001%Address mapping 25–45 bit physical address 32–64 bit virtual address to 25–45 bit

to 14–20 bit cache address physical address

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DRAM basicsAdvanced DRAM technology

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Design choices

Block placement

I Miss penalty huge compared to cacheI OS designer opts for lower miss rateI Fully associative placement

I Exception: page coloringI Page consecutive VM in consecutive physical frames pages

to avoid cache conflictsI Requires knowledge of cache organization and cache

mapping scheme

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 30 / 34

DRAM basicsAdvanced DRAM technology

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Design choicesFinding the block in memory

I Page tables or segment tables or segmented pagingI Common optimizations: inverted page tables, multi-level

page tablesI TLB for fast address translation

Selecting block for replacement

I Approximations of LRU with one or more use andreference bits

Write policy

I Always write-back due to disk latency

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 31 / 34

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DRAM basicsAdvanced DRAM technology

Virtual memory

Alpha 21264 TLB exampleaddress space ID

virtual page number

page offset

<35> <13> <8>

<8>

ASN

<4>

Prot

<1>

V

<35>

Tag

<31>

physical address

1 2

128:1 mux

3

31/28 MS bits of PA

<31/28>

13 LS bits of PA

<13>

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 32 / 34

DRAM basicsAdvanced DRAM technology

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Alpha TLB in detail

Design choices

I Virtually addressed TLBI Uses address space identifier (PID)I Avoids flushes on context switches

I No use or reference bitI System periodically clears permission bits (read, write)I Recorded reads, writes serve as reference/use bitsI No need to write to TLB during normal memory accesses

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DRAM basicsAdvanced DRAM technology

Virtual memory

Selecting page size

Trade-off’s

I Larger page size means smaller page tablesI Larger page size can enable a larger virtually-indexed,

physically-tagged L1 cacheI Transferring large pages from disk can be more efficient

(latency lags bandwidth)I Less TLB entries, more memory mapped in the TLBI Smaller page size means less memory waste due to

internal fragmentation

Dimitrios S. Nikolopoulos HY425 Lecture 15: DRAM Technology 34 / 34


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