~ame, Lastname, Student Number: 23.01.2017

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Karadeniz Technical University II Teknik OniversitesiFaculty of Engineering II Muhendislik FakultesiDepartment of Computer Engineering /I Bilgisayar Muhendlsliqi BalOmu

BiL 1007 Resit Exam II Butunlerne Stnavi1. Design an asynchronous frequency divider circuit to divide input frequency by 5 using positive edge triggered D flip flops and

necessary gates. 1/ Giri~ isaret frekansmi 5'e bi:ilmek i~in asenkron bir frekans bi:ihJcudevresini yOkselen kenar tetiklemeli D flipfloplar ve gerekli kaptlart kullanarak tasarlaytruz.1- \

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2. Compute the maximum clock frequency of a 5-bit asynchronous counter with positive edge triggered D flip flops which have 4ns propagation delay from clock edge to output. 1/ Saat kenanndan ~Ikl~a4 ns yayilrna gecikmesi olan pozitif kenar tetiklemeliD flip floplar ile yapilrms 5-bit'lik bir asenkron sayicrrun en yOksek cahsrna frekansrru hesaplayrmz.

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3. Design a digital circuit to delay a 1-bit input signal by 2 ms using positive edge triggered D flip flops assumingthere is a 3 kHz clock signal available. II 1-bitlik giri~ lsaretinl 2 ms geciktirmek i~in bir sayrsal devreyi ylikselen kenartetiklemeli D flip floplar kullanarak 3 kHz'lik bir saat isaretinin bulundu varsayrrm ile tasarlayiruz.

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4. Manufacturers use Static RAM cells for cache memory of microprocessors even though Dynamic RAM cells cost less andconsumes lower power. Explain the reason in one sentence? /I Dinamik RAM hucreleri daha dusuk maliyetli olmasi ve dahadusuk gue;;tOketmesine karsruk Oreticiler mlkroislernci on belleqinde Statik RAM hucrelerl kullanmaktadrr, Bunun gerekc;:esinibircOmle ile acrklaymiz.

5. Suggest a method to speed-up address decoding process which determines memory access time? /I Bellek erlsirn suresinibelirleyen adres kod e;;ozOmusOrecinin hrztandmlabflrnesl ie;;inbir e;;ozOmonerlnlz?

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