IAY 0600

Digitaalsüsteemide disain

Course Overview

Alexander Sudnitson

Tallinn University of Technology

2

Administrative

Aleksander Sudnitsõn

Arvutitehnika instituut, dotsentIT-309alsu@cc.ttu.eewww.pld.ttu.ee/~alsu

IAY0600 Digitaalsüsteemide disain (erikursus)

IAY0600 Digitaalsüsteemide disain (PRAKTIKUM)

IAY0120 ARVUTITEHNIKA PROJEKT

3

Administrative

Loengute õppetöö keel: inglise

Loengud:

neljapäeviti 14.00 - 15.30

Praktikum: IT-307 Dimitri Mihhajlov

16.00 - 17.30

esemine regulaarne praktikum toimub 18.02.2010 (pärast registreerimist)

4

Hindamine

Teoreetiliste teadmiste osakaal eksamil on 40% hindest ja projekteerimisülesannete tulemuste demonstratsioon koos lahenduste seletuskirjaga annab 60% eksamihindest.

“LEARNING BY DOING”

5

Õppeaine sisu lühikirjeldus

Digitaalsüsteemide projekteermis-metoodika VHDL ja prgrammeeritava loogika (FPGA) abil.

Realiseerimine väliprogrammeeritaval loogikal (FPGA).

Digitaalseadmete kiire prototüüpimine.

Asünkroonsete süsteemide põhialused (süsteemne vaade).

6

Õppekirjandus

Iga tudeng saab komplekti slaide enne loengut.

K. L. Short, VHDL for Engineers, Pearson Education, Inc., 2009.Sparso J. and Furber S. Principles of Asynchronous Circuit Design: a Systems Perspective. Boston: Kluwer, 2001.P.P. Chu, FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008.J. O. Hamblen, T.S. Hall, and M. D. Furman, Rapid Prototyping of Digital Systems, Springer, 2007.

IAY 0600

Digitaaltehnika erikursus

VHDL/PLD Design Methodology

Alexander Sudnitson

Tallinn University of Technology

8

Digital System

A discrete system is a system in which signals have a finite number of discrete values.(This contrasts with analog systems, in which signals have values from an infinite set).

Any finite number of discrete values can be represented by a vector of signals with just two values. Such a signal, which takes only two values, is called a digital signal (or binary, or logic), and any device that processes digital signals is called a digital device.

DiscreteSystem

Inputs Outputs

9

Design process

The design process consists of obtaining an implementation that satisfies the specification of a system.

Specification

(behaviour)

Analysis (verification) Synthesis

Implementation

(structure)

The analysis of a system has an objective the determination of its specification from an implementation. The synthesis consists of obtaining an implementation that satisfies the specification of a system

10

Different design views

Systems can be described from different points of view:

Behavior: what does it do?

Structure: what is it composed of?

Functional properties: how do I interface to it?

Physical properties: how fast is it?

11

Design Representation

A structural representation is one that the black box as a set of components and their connections. It specifies the product’s implementation without explicit reference to its functionality. In some cases, the functionality could be derived from that of its interconnected components.

A behavioral or functional representation is one that looks at the design as a black box. A behavioral representation describes the functionality but not the implementation of a given design, defining the black box’s response to any combination of input values but without describing a way to design or build the black box using the given components.

Three different domains of description:

A physical representation is one that specifies the physical characteristics of the black box, providing the dimensions and locations of each component and connection contained in the structural description. The physical representation is used to describe the design after it has been manufactured, specifying its weight, size, heat dissipation, power consumption and the position of each input or output pin.

12

Modified Y Chart: levels of abstruction

Programmable cores, IPs, ASICs

Registers, Adders, Multipliers, etc.

Logic netlist, Schematic

Boolean equations

Dataflow

Processes

Algorithm Processor, Memory, Peripheral interface

View

Behavior Description

Structural Description

Logic

Register Transfer (RTL)

System

Architectural

13

Timing units at different levels

Registers, Adders, Multipliers, etc.

Logic netlist, Schematic

Programmable cores, IPs, ASICs

Boolean equations

Dataflow

Processes

Algorithm Processor, Memory, Peripheral interface

View

Behavior Description

Structural Description

Delay

Clock Cycle

Computation Step

Comuncation Transaction

Time Units

14

Modified Y Chart : this course area

Algorithm Processor, Memory, Peripheral interface

View

Behavior Description

Structural Description

Registers, Adders, Multipliers, etc.

Logic netlist, Schematic

Dataflow / RTL

Boolean equations

Synthesis

Analysis

15

Modified Y Chart: transformations

Algorithm Processor, Memory, Peripheral interface

View

Behavior Description

Structural Description

Registers, Adders, Multipliers, etc.

Logic netlist, Schematic

Dataflow

Boolean equotions

Algorithmic

Register-Transfer

Logic

Transformations

16

Chart supporting synthesis activity

View

Behavior Description

Structural Description

Algorithmic level of abstraction

Register-transfer level of abstraction

Logic level of abstraction

Behavioral synthesis

RTL synthesis

Logic synthesis

17

Example: HalfAdder

Sum

CarryHalfAdderA

B

Structure

Sum = ¬A&B A&¬B = A B

Carry = A & B

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Behavior

BCarry

&

A Sum

18

Example: HalfAdder Behavioral Description

entity HALFADDER isport(A, B: in bit; SUM, CARRY: out BIT); end HALFADDER;

Sum = ¬A&B A&¬B = A B

Carry = A & BHalfAdder

A

B

Sum

Carry

This is data flow behavioral description

architecture RTL of HALFADDER isbegin

SUM <= A xor B;CARRY <= A and B;

end RTL;

19

Design flow for VHDL/PLD design methodology

20

The half-adder UUT and its testbench