IAY 0600

Digital Systems Design

VHDL discussion Dataflow Style Combinational Design

Alexander Sudnitson

Tallinn University of Technology

2

Example: HalfAdder

Sum

CarryHalfAddera

b

Structure

Sum = ¬a&b a&¬b = a b

Carry = a & b

a b Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Behavior

bCarry

&

a Sum

3

Example: HalfAdder Behavioral Description

entity HALFADDER isport(a, b: in bit; Sum, Carry: out BIT); end HALFADDER;

Sum = ¬a&b a&¬b = a b

Carry = a & bHalfAdder

a

b

Sum

Carry

This is data flow behavioral description

architecture RTL of HALFADDER isbegin

Sum <= a xor b;Carry <= a and b;

end RTL;

4

Combinational systems

Combinational systems have no memory. A combinational system's outputs are a function of only its present input values.

No latches/FFs or closed feedback loop Combinational system description can be in dataflow,

behavioral, or structioral styles. Concurrent signal assignment signal is basic for dataflow

style combinational design.

We consider three kinds of concurrent signal assignment:Concurrent signal assignment statement using a Boolean expressionSelected signal assignment statementConditional signal assignment statement

5

Signal assignment in combinational design

Syntax for synthesizable signal assignment statement

Signal assignment statement with a closed feedback loop:a signal appears in both sides of a concurrent assignment statementFor example, q <= ((not q) and (not en)) or (d and en);

Syntactically correctForm a closed feedback loopShould be avoided

6

Simplified syntax for entity declaration

Syntax refers to the patern or structure of the word order in a prase.

Definitions are simplified for instructional purposes.

7

Notation used in syntax definitions

8

4-to-1 multiplexer using a Bool. expression

library ieee;use ieee.std_logic_1164.allentity mux4to1 is

port (c3, c2, c1, co: in std_logic;g_bar, b, a: in std_logic;y: out std_logic);

end mux4to1;architecture dataflow of mux4to1 isbeginy <= not g_bar and (

(not b and a and c0) or(not b and a and c1) or(b and not a and c2) or(b and a and c3));

end dataflow;

What is STD_LOGIC you ask?

9

STD_LOGIC type

Value Meaning

'U' Uninitialized

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’Weak (Weakly driven) 0.Models a pull down.

‘H’Weak (Weakly driven) 1. Models a pull up.

‘-’ Don't Care

10

BIT versus STD_LOGIC

BIT type can only have a value of ‘0’ or ‘1’ STD_LOGIC can have nine values

'U',‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’ Useful mainly for simulation ‘0’,’1’, and ‘Z’ are synthesizable

11

Selected signal assignment statement

Simplified syntax:

with select_expression selectsignal_name <=value_expr_1 when choice_1,value_expr_2 when choice_2,value_expr_3 when choice_3,. . .value_expr_n when choice_n;

The value of one and only one choice must equal the value of the select expression.

12

library ieee;use ieee.std_logic_1164.allentity mux4to1 is

port (c3, c2, c1, c0: in std_logic;g_bar, b, a: in std_logic;y: out std_logic);

end mux4to1;architecture selected of mux4to1 isbeginwith std_logic_vector' (g_bar, b, a) selecty <= c0 when "000", c1 when "001",

c2 when "010", c3 when "011"'0' when others; -- default

end selected;

Selected signal assignment statement (ex.)

Here we use an aggregate (g_bar, b, a) in a select expression

13

Type qualification. Choices’ completeness

y <= c0 when "000",

c1 when "001",

c2 when "010",

c3 when "011"

'0' when others;

The last clause (default assignment) uses the keyword others to assign the value of 0 to y for the 725 values of the select expression not explicitly listed. 9**3=729, 729-4=725

We must explicitly specify the aggregat's (g_bar, b, a) type. This is accomplished using a type qualification ('):std_logic_vector' (g_bar, b, a)

To describe combinational logic, the choices listed in a selected signal assignment must be all inclusive. That is, they must include every possible value of the select expression.

14

Conditional signal assignment statement

The result from evaluating a condition is type boolean.

type boolean is (false, true) ;

Example:

type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') ;

' Z ' (with position number 4) iz greater than ' 1 ' (with position number 3

The leftmost literal in an enumeration listing is in position 0. Each enumeration type definition defines an ascending range of position numbers.

15

Conditional signal assignment statement

library ieee ; use ieee.std_logic_1164.all ;entity mux4to1 is

port (c3, c2, c1, co: in std_logic;g_bar, b, a: in std_logic; y: out std_logic);

end mux4to1;architecture conditional of mux4to1 is

signal tmp : std_logic_vector (2 downto o);begin

tmp <= (g_bar, b, a);y <= c0 when tmp = "000" else

c1 when tmp = "001" elsec2 when tmp = "010" elsec3 when tmp = "011" else'0' ; -- default assignment

end conditional;

16

Avoiding implied latches

For example, let’s take previous description.If the conditional signal is written as:

y <= c0 when tmp = "000" elsec1 when tmp = "001" elsec2 when tmp = "010" elsec3 when tmp = "011" ;

the VHDL interpretation of this construct is that, for the 4 specified values of tmp, a new value should be assigned to y. This implies that for all other values of tmp the y should retain its previous value.As a result, the synthesizer generates a latch at the output of the combinational logic to store the value of y.

The last value_expression must not have an associated when condition clause (default assignment).

17

Synthesised mux logic with undesired latch