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IBM Microelectronics
SLIP 2005 April 2, 2005 © 2005 IBM Corporation
Bounding the Impact of Transient Power Supply Noise in Static Timing Analysis Over a Realistic Activity Space
David HathawayApril 2, 2005
IBM Microelectronics
© 2005 IBM Corporation2 SLIP 2005 April 2, 2005
Outline
Background and problem description
Prior work
This work
– Modeling realizable patterns of activity
– Determining peak voltage variation
– Determining bounding timing conditions
– Applications to design planning
Remaining issues
IBM Microelectronics
© 2005 IBM Corporation3 SLIP 2005 April 2, 2005
Power supply networks as System-Level Interconnect
Power supply networks do communicate information
– Power demand in one place affects voltages in others
Northeast blackout
August 14, 2003
IBM Microelectronics
© 2005 IBM Corporation4 SLIP 2005 April 2, 2005
Problem addressed
Determine maximum impact of transient power supply noise on chip timing
VDD
Board / Package
Current waveformObject
switching
Voltage waveform
Delay variation
IBM Microelectronics
© 2005 IBM Corporation5 SLIP 2005 April 2, 2005
Why is this becoming more important?
Why Hot Chips Are no Longer “COOL” - Ray Bryant
Steam Iron5W/cm2
Power density is increasing (again)
IBM Microelectronics
© 2005 IBM Corporation6 SLIP 2005 April 2, 2005
Why is this becoming more important?
Delay sensitivity to supply voltage is increasing
– Due to voltage reductions needed to contain power density
Delay
Supply voltage
Rise & fall delays of
2-way AND
IBM Microelectronics
© 2005 IBM Corporation7 SLIP 2005 April 2, 2005
Power Supply Noise – Voltage Response
A trivial network model demonstrates key noise characteristics:
t = 0
VDD
ChipBoard / Package
What is the “circuit’s view” voltage response to the switching current signature illustrated above?
IBM Microelectronics
© 2005 IBM Corporation8 SLIP 2005 April 2, 2005
+
-v(t)
Static IR Drop
Voltage Response At Circuit Terminals
IBM Microelectronics
© 2005 IBM Corporation9 SLIP 2005 April 2, 2005
Delay dependence on voltage
Traditional models use a single supply voltage per gate
– Reality is more complicated
Drive (& hence delay) of gate G2 is a
function of Vdd & Gnd of both G1 and G2
Most power supply noise is differential (Vdd drops as Gnd
rises)
IBM Microelectronics
© 2005 IBM Corporation10 SLIP 2005 April 2, 2005
Why is it hard to find the worst timing impact?
Naïve approach
– Determine worst voltage at each node (max Gnd, min Vdd)
– Time circuit with these voltages
Problems
– Timing test compare early/late clock/data
– Worst slack (for setup test) when data is slow relative to clock
Max voltage dropMax delay
Max voltage drop gradientWorst slack
IBM Microelectronics
© 2005 IBM Corporation11 SLIP 2005 April 2, 2005
Outline
Background and problem description
Prior work
This work
– Modeling realizable patterns of activity
– Determining peak voltage variation
– Determining bounding timing conditions
– Applications to design planning
Summary
IBM Microelectronics
© 2005 IBM Corporation12 SLIP 2005 April 2, 2005
Use superposition to determine worst timing
Vectorless Analysis of Supply Noise Induced Delay Variation, S. Pant, D. Blaauw, et. al., U. Michigan, ICCAD 2003
– Bound current demand at each power network node
– Simulate current impulse applied at each power network node
– Model delay linearly with voltage
– Use delay model & power network response to model path delay as function of current at each node in each cycle
– Use linear optimizer to determine current profiles which give worst path delay
– Use spatial and temporal superposition of voltage waveforms
IBM Microelectronics
© 2005 IBM Corporation13 SLIP 2005 April 2, 2005
Spatial superpositioning
Compute voltage waveforms for different aggressors
Add selected waveforms with no time shifting
A
B
B
B
A
A
+ =
+ =
IBM Microelectronics
© 2005 IBM Corporation14 SLIP 2005 April 2, 2005
Temporal superpositioning
Compute voltage waveforms for one cycle of each aggressor (simulate until transients die out)
Add time shifted copies of waveform to get impact of operation over many cycles
Voltage drop
Current
Steady state
voltage drop
IBM Microelectronics
© 2005 IBM Corporation15 SLIP 2005 April 2, 2005
Use superposition to determine worst timing
0
1
2
n
0 1 n
A
B
J(i,j)
V(0,0)
V(n,n)
…
…
…
…
0
1
2
n
0 1 n
…
Find ∆Jij to maximize Dpath
∑
IBM Microelectronics
© 2005 IBM Corporation16 SLIP 2005 April 2, 2005
Limitations of prior work
Cannot easily restrict analysis to realizable activities
– Allows only linear constraints between current weights
Path-oriented analysis
– Subject to exponential path enumeration issues
Assumes constant voltage within cycle
– Loses high frequency variation
IBM Microelectronics
© 2005 IBM Corporation17 SLIP 2005 April 2, 2005
Constraints on realizable activities
Example – either banks 0 & 1 switch or bank 2 switches or bank 3 switches
p2
p1
0 1 2 3 Banks with worst effect differ for
paths p1 and p2
Cannot constraint total switching
– S(0) + S(1) > S(2) or S(3) alone
Cannot constrain relation between banks
– S(0), S(1) > S(2) for p1
– S(2) > S(0), S(1) for p1
Selection of worst banks is not a linear problem
IBM Microelectronics
© 2005 IBM Corporation18 SLIP 2005 April 2, 2005
Constraints on realizable activities
Example – clock dithering to limit noise from clock gating
Unconstrained
Dithered
IBM Microelectronics
© 2005 IBM Corporation19 SLIP 2005 April 2, 2005
Outline
Background and problem description
Prior work
This work
– Modeling realizable patterns of activity
– Determining peak voltage variation
– Determining bounding timing conditions
– Applications to design planning
Summary
IBM Microelectronics
© 2005 IBM Corporation20 SLIP 2005 April 2, 2005
Overview of our approach
Identify “objects of interest” (OOIs)
– Large or high power cores of SOC
– Regions of random logic
Simulate voltage drops due to each OOI
Determine allowable patterns / sequences of activity for OOIs
– Modeled as BDDs
Determine max / min v(t) for each node
Use min / max v to screen, find critical subnetwork
Use block-based statistical timing with OOI activities as variables to refine timing
Determine worst slack for each timing test within allowable sequences
Reanalyze paths with nonlinear delay dependencies to validate / refine slacks
IBM Microelectronics
© 2005 IBM Corporation21 SLIP 2005 April 2, 2005
Simulating OOI currents
Use fast linear power grid simulator
– Uses fixed time step, explicit matrix inversion
• Initial overhead
– Allows very fast simulation of many waveforms
– Changing OOI currents, location of application is very fast
– Changing power grid (or adding decoupling caps) is slower
IBM Microelectronics
© 2005 IBM Corporation22 SLIP 2005 April 2, 2005
Modeling allowable conditions
Determine set of conditions which must be met
– Model as Boolean functions of OOI activity in different cycles
– Examples
• No more than k of n memory banks switch in one cycle
• Clock cannot have X cycles off followed by Y cycles on
Represent AND of all conditions as BDD
– One BDD for all chip constraints
– Variables are activity of OOIs in particular cycles
– Subsequent steps depend linearly on BDD size
– … so aggressively reorder for minimum size
x2
0 1
x3
x10 1
F
0 1
0 1
IBM Microelectronics
© 2005 IBM Corporation23 SLIP 2005 April 2, 2005
Finding extreme voltages DFS traversal of constraint BDD
– One traversal per node, per alignment in cycle
– Assign weights to BDD variables based on voltage of node at alignment time due to OOI switching in a particular cycle
– Determine extreme (min/max) value at each node
T 2T 3T
T 2T 3T
T 2T 3T
Va(t)
Va(t+T)
Vb(t)
…
IBM Microelectronics
© 2005 IBM Corporation24 SLIP 2005 April 2, 2005
Finding extreme voltages
For each node / alignment
– ∆Vi = delta voltage when OOIi is active
– Min value Vmin(n) at BDD node n with variable l(n), children c0(n), c1(n):
– Vmin(0)=+infinity, Vmin(1)=Vnom
– Vmin of root is min realizable voltage
– Similar form for max voltage
1-)(l
1))(1l(c)l(min
1-)(l
1))(0l(cmin
) min(0,))(1(
,) min(0,))(0(
min = )(n
niin
n
nii
min
VVncV
VncV
nV
Variables skipped by
0 edge
Variables skipped by
1 edge
Contribution of this OOI switching
0 child value
1 child value
IBM Microelectronics
© 2005 IBM Corporation25 SLIP 2005 April 2, 2005
Finding extreme voltages
Example
1
2 2
3
0 1-infinity 1.5
V3 = +0.18
V2 = -0.25
V1 = -0.1
1.68
Node / offset 1
1.43 1.25
1.25
IBM Microelectronics
© 2005 IBM Corporation26 SLIP 2005 April 2, 2005
Finding extreme voltages
Example
1
2 2
3
0 1-infinity 1.5-infinity 1.5
V3 = +0.13
V2 = -0.15
V1 = -0.15
1.63
Node / offset 2
1.48 1.35
1.33
IBM Microelectronics
© 2005 IBM Corporation27 SLIP 2005 April 2, 2005
Application to timing
1. Use min (late) / max (early) voltages to filter errors
2. Apply block-based statistical timing to remaining regions
Delay / Arrival times / slacks are functions of OOI activity
Max / min propagated statistically
Sample waveform voltages at mean arrival time
Result is slack equation for each test Find worst slack by BDD traversal
annn RaXaXaXaa 122110
IBM Microelectronics
© 2005 IBM Corporation28 SLIP 2005 April 2, 2005
Block-based statistical timing
Deterministic
Statistical
a
b
c+
+ MAX
b
a
c+
+ MAX
IBM Microelectronics
© 2005 IBM Corporation29 SLIP 2005 April 2, 2005
Waveform sampling for delay calculation
1. Get arrival time t 3. Compute delay
2. Get V(t)
4. Get arrival time t 6. Compute delay
5. Get V(t)
. . .
IBM Microelectronics
© 2005 IBM Corporation30 SLIP 2005 April 2, 2005
Applications to Design Planning
Get OOI locations from floorplan
Determine extreme voltages
– Detailed paths not yet known, so can’t apply to timing
– Impose bounds on voltage
Modifications to fix errors
– Add decoupling caps
• Only useful for short transient limit violations
– Move OOIs
– Impose restrictions on allowed activity patterns
IBM Microelectronics
© 2005 IBM Corporation31 SLIP 2005 April 2, 2005
Updating voltage extremes
OOI current location
Power grid model build
OOI activity restriction
Power grid simulations
Decap changes
Object movement
Power grid changes
slow
medium
Activity constraint changes
fast
IBM Microelectronics
© 2005 IBM Corporation32 SLIP 2005 April 2, 2005
(Some) remaining issues
Current depends on voltage
– Ignored by superposition approach
Block-based statistical timing may not apply well
– Need to validate predicted worst activity patterns
– Fall-backs - use path-based approach
Picking the right set / granularity of OOIs
Determining activity constraints
– Need links to system-level modeling
IBM Microelectronics
© 2005 IBM Corporation33 SLIP 2005 April 2, 2005
Acknowledgements
Thanks to many people in IBM working on these issues, and in particular:
– Ivan Wemple
– Chandu Visweswariah
– Sani Nassif
– Doug Stout
– Kerim Kalafala