EXPERIMENT 1

Aim: Modelling Xilinx FIFO Generator IP Core

The FIFO Generator core is a fully verified first-in first-out memory queue for use in any

application requiring in-order storage and retrieval, enabling high-performance and area

optimized designs. The core provides an optimized solution for all FIFO configurations and

delivers maximum performance (up to 500 MHz) while utilizing minimum resources.

The Xilinx FIFO Generator core supports Native interface FIFOs and AXI4 Interface FIFOs.

Native interface FIFO Generators (FIFOs) are the original standard FIFO functions delivered by

the previous versions of the FIFO Generator (up to v6.2). AXI4 Interface FIFOs are derived from

the Native interface FIFO. Three AXI4 interface styles are available: AXI4-Stream, AXI4 and

AXI4-Lite.

Native Interface FIFOs

The Native interface FIFO can be customized to utilize block RAM, distributed RAM or built-in

FIFO FPGA resources available in some FPGA families to create high performance, area-

optimized FPGA designs.

Standard mode and First Word Fall Through are the two operating modes available for Native

interface FIFOs.

AXI4 Interface FIFOs

AXI4 interface FIFOs are derived from the Native interface FIFO, as shown in Figure 1-2. Three

AXI4 interface styles are available: AXI4-Stream, AXI4 and AXI4-Lite. In addition to

applications supported by the Native interface FIFO, AXI4 FIFOs can also be used in AXI4

System Bus and Point-to-Point high speed applications. AXI4 Interface FIFOs do not support

built-in FIFO and Shift Register FIFO configurations.

Features of FIFO

Common Features

Supports Native, AXI4-Stream, AXI4 and AXI4-Lite interfaces FIFO depths up to 4,194,304 words Independent or common clock domains VHDL example design and demonstration test bench demonstrating the IP core design flow, including how to instantiate and simulate it

Fully configurable using the Xilinx Vivado IP Catalog customizer or the ISE CORE Generator

Native FIFO Specific Features

FIFO data widths from 1 to 1024 bits Symmetric or Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1) Synchronous or asynchronous reset option Selectable memory type (block RAM, distributed RAM, shift register, or built-in FIFO) Option to operate in Standard or First-Word Fall-Through modes (FWFT) Full and Empty status flags, and Almost Full and Almost Empty flags for indicating one-word- left

Programmable Full and Empty status flags, set by user-defined constant(s) or dedicated input port(s)

Configurable handshake signals Embedded register option for block RAM and built-in FIFO configurations

AXI4 FIFO Features

FIFO data widths from 1 to 4096 bits Supports all three AXI4 interface protocols - AXI4, AXI4-Stream, and AXI4-Lite Symmetric aspect ratios Asynchronous active low reset Selectable configuration type (FIFO, Register Slice, or Pass through Wire) Selectable memory type (block RAM, or distributed RAM) Selectable application type (Data FIFO, Packet FIFO, or low latency FIFO) Operates in First-Word Fall-Through mode (FWFT) Configurable Interrupt signals Auto-calculation of FIFO width based on AXI signal selections and data and address widths Configurable programmable Full/Empty flags as sideband signals

Pin Description

Name Direction Description

DIN[N:0] Input Data Input: The input data bus used when writing the FIFO

DOUT[N:0] Output Data Output: The output data bus is driven when reading the FIFO.

CLK Input Clock: All signals on the write and read domains are synchronous to

this clock.

RST Input Reset: An asynchronous reset signal that initializes all internal

pointers and output registers.

RD_EN Input Read Enable: If the FIFO is not empty, asserting this signal causes

data to be read from the FIFO (output on DOUT).

WR_EN Input Write Enable: If the FIFO is not full, asserting this signal causes data

(on DIN) to be written to the FIFO.

EMPTY Output Empty Flag: When asserted, this signal indicates that the FIFO is

empty. Read requests are ignored when the FIFO is empty, initiating

a read while empty is not destructive to the FIFO.

FULL Output Full Flag: When asserted, this signal indicates that the FIFO is full.

Write requests are ignored when the FIFO is full, initiating a write

when the FIFO is full is not destructive to the contents of the FIFO

VHDL Code for Synthesis:

Main Program LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fifo_ip IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END fifo_ip; ARCHITECTURE fifo_ip_arch OF fifo_ip IS COMPONENT fifo PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; BEGIN U0 : fifo PORT MAP ( clk => clk, rst => rst, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty ); END fifo_ip_arch;

IP core component LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY fifo IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END fifo; ARCHITECTURE fifo_a OF fifo IS -- synthesis translate_off COMPONENT wrapped_fifo PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_3(behavioral) GENERIC MAP ( c_add_ngc_constraint => 0, c_application_type_axis => 0, c_application_type_rach => 0, c_application_type_rdch => 0, c_application_type_wach => 0, c_application_type_wdch => 0, c_application_type_wrch => 0, c_axi_addr_width => 32, c_axi_aruser_width => 1, c_axi_awuser_width => 1, c_axi_buser_width => 1, c_axi_data_width => 64, c_axi_id_width => 4, c_axi_ruser_width => 1,

c_axi_type => 0, c_axi_wuser_width => 1, c_axis_tdata_width => 64, c_axis_tdest_width => 4, c_axis_tid_width => 8, c_axis_tkeep_width => 4, c_axis_tstrb_width => 4, c_axis_tuser_width => 4, c_axis_type => 0, c_common_clock => 1, c_count_type => 0, c_data_count_width => 10, c_default_value => "BlankString", c_din_width => 18, c_din_width_axis => 1, c_din_width_rach => 32, c_din_width_rdch => 64, c_din_width_wach => 32, c_din_width_wdch => 64, c_din_width_wrch => 2, c_dout_rst_val => "0", c_dout_width => 18, c_enable_rlocs => 0, c_enable_rst_sync => 1, c_error_injection_type => 0, c_error_injection_type_axis => 0, c_error_injection_type_rach => 0, c_error_injection_type_rdch => 0, c_error_injection_type_wach => 0, c_error_injection_type_wdch => 0, c_error_injection_type_wrch => 0, c_family => "spartan3", c_full_flags_rst_val => 1, c_has_almost_empty => 0, c_has_almost_full => 0, c_has_axi_aruser => 0, c_has_axi_awuser => 0, c_has_axi_buser => 0, c_has_axi_rd_channel => 0, c_has_axi_ruser => 0, c_has_axi_wr_channel => 0, c_has_axi_wuser => 0, c_has_axis_tdata => 0, c_has_axis_tdest => 0, c_has_axis_tid => 0, c_has_axis_tkeep => 0, c_has_axis_tlast => 0, c_has_axis_tready => 1, c_has_axis_tstrb => 0, c_has_axis_tuser => 0, c_has_backup => 0, c_has_data_count => 0, c_has_data_counts_axis => 0,

c_has_data_counts_rach => 0, c_has_data_counts_rdch => 0, c_has_data_counts_wach => 0, c_has_data_counts_wdch => 0, c_has_data_counts_wrch => 0, c_has_int_clk => 0, c_has_master_ce => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_has_prog_flags_axis => 0, c_has_prog_flags_rach => 0, c_has_prog_flags_rdch => 0, c_has_prog_flags_wach => 0, c_has_prog_flags_wdch => 0, c_has_prog_flags_wrch => 0, c_has_rd_data_count => 0, c_has_rd_rst => 0, c_has_rst => 1, c_has_slave_ce => 0, c_has_srst => 0, c_has_underflow => 0, c_has_valid => 0, c_has_wr_ack => 0, c_has_wr_data_count => 0, c_has_wr_rst => 0, c_implementation_type => 0, c_implementation_type_axis => 1, c_implementation_type_rach => 1, c_implementation_type_rdch => 1, c_implementation_type_wach => 1, c_implementation_type_wdch => 1, c_implementation_type_wrch => 1, c_init_wr_pntr_val => 0, c_interface_type => 0, c_memory_type => 1, c_mif_file_name => "BlankString", c_msgon_val => 1, c_optimization_mode => 0, c_overflow_low => 0, c_preload_latency => 1, c_preload_regs => 0, c_prim_fifo_type => "1kx18", c_prog_empty_thresh_assert_val => 2, c_prog_empty_thresh_assert_val_axis => 1022, c_prog_empty_thresh_assert_val_rach => 1022, c_prog_empty_thresh_assert_val_rdch => 1022, c_prog_empty_thresh_assert_val_wach => 1022, c_prog_empty_thresh_assert_val_wdch => 1022, c_prog_empty_thresh_assert_val_wrch => 1022, c_prog_empty_thresh_negate_val => 3, c_prog_empty_type => 0, c_prog_empty_type_axis => 5, c_prog_empty_type_rach => 5,

c_prog_empty_type_rdch => 5, c_prog_empty_type_wach => 5, c_prog_empty_type_wdch => 5, c_prog_empty_type_wrch => 5, c_prog_full_thresh_assert_val => 1022, c_prog_full_thresh_assert_val_axis => 1023, c_prog_full_thresh_assert_val_rach => 1023, c_prog_full_thresh_assert_val_rdch => 1023, c_prog_full_thresh_assert_val_wach => 1023, c_prog_full_thresh_assert_val_wdch => 1023, c_prog_full_thresh_assert_val_wrch => 1023, c_prog_full_thresh_negate_val => 1021, c_prog_full_type => 0, c_prog_full_type_axis => 5, c_prog_full_type_rach => 5, c_prog_full_type_rdch => 5, c_prog_full_type_wach => 5, c_prog_full_type_wdch => 5, c_prog_full_type_wrch => 5, c_rach_type => 0, c_rd_data_count_width => 10, c_rd_depth => 1024, c_rd_freq => 1, c_rd_pntr_width => 10, c_rdch_type => 0, c_reg_slice_mode_axis => 0, c_reg_slice_mode_rach => 0, c_reg_slice_mode_rdch => 0, c_reg_slice_mode_wach => 0, c_reg_slice_mode_wdch => 0, c_reg_slice_mode_wrch => 0, c_underflow_low => 0, c_use_common_overflow => 0, c_use_common_underflow => 0, c_use_default_settings => 0, c_use_dout_rst => 1, c_use_ecc => 0, c_use_ecc_axis => 0, c_use_ecc_rach => 0, c_use_ecc_rdch => 0, c_use_ecc_wach => 0, c_use_ecc_wdch => 0, c_use_ecc_wrch => 0, c_use_embedded_reg => 0, c_use_fifo16_flags => 0, c_use_fwft_data_count => 0, c_valid_low => 0, c_wach_type => 0, c_wdch_type => 0, c_wr_ack_low => 0, c_wr_data_count_width => 10, c_wr_depth => 1024, c_wr_depth_axis => 1024,

c_wr_depth_rach => 16, c_wr_depth_rdch => 1024, c_wr_depth_wach => 16, c_wr_depth_wdch => 1024, c_wr_depth_wrch => 16, c_wr_freq => 1, c_wr_pntr_width => 10, c_wr_pntr_width_axis => 10, c_wr_pntr_width_rach => 4, c_wr_pntr_width_rdch => 10, c_wr_pntr_width_wach => 4, c_wr_pntr_width_wdch => 10, c_wr_pntr_width_wrch => 4, c_wr_response_latency => 1, c_wrch_type => 0 ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo PORT MAP ( clk => clk, rst => rst, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty ); -- synthesis translate_on END fifo_a;

Test Bench for FIFO Generator:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fifo_ip_test IS END fifo_ip_test; ARCHITECTURE behavior OF fifo_ip_test IS COMPONENT fifo_ip PORT( clk : IN std_logic; rst : IN std_logic; din : IN std_logic_vector(17 downto 0); wr_en : IN std_logic; rd_en : IN std_logic; dout : OUT std_logic_vector(17 downto 0); full : OUT std_logic; empty : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal din : std_logic_vector(17 downto 0) := (others => '0'); signal wr_en : std_logic := '1'; signal rd_en : std_logic := '1'; --Outputs signal dout : std_logic_vector(17 downto 0); signal full : std_logic; signal empty : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: fifo_ip PORT MAP ( clk => clk, rst => rst, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty ); din

RTL Schematic

Simulation Results:

EXPERIMENT 2

Aim: Modelling Xilinx RAM Based Shift Register IP Core

The Xilinx IP RAM-based Shift Register core provides a very efficient multi-bit wide shift

register for use in FIFO-like applications or as a delay line. Fixed-length shift registers and

variable-length shift registers can be created.

Features of RAM Based Shift Register Drop-in module for Virtex-7 and Kintex-7,Virtex-6, Virtex-5, Virtex-4, Spartan-6,

Spartan-3/XA, Spartan-3E/XA, Spartan-3A/3AN/3A DSP/XA FPGAs

Generates fast, compact, FIFO-style shift registers or delay lines using the SRL16/SRL32 mode of the slice LUTs

User options to create fixed-length or variable-length shift registers

Speed or resource optimization for variable length shift registers

Optional output register with clock enable and synchronous controls for variable length shift registers

For use with Xilinx CORE Generator and Xilinx System Generator for DSP 13.1

Pin Description

Name Direction Description

D [N:0] Input Parallel Data Input

A [M:0] Input Address Input (required on variable-length modules only)

CE Input Optional active high Clock Enable

CLK Input Rising-edge Clock Input

SSET Input Optional Synchronous Set. Forces outputs to a high state when driven

high

SCLR Input Optional Synchronous Clear. Forces outputs to a low state when

driven high

SINIT Input Synchronous Initialize. Forces outputs to a user-defined state when

driven high

Q [N:0] Output Parallel Data Output

VHDL Code for Synthesis:

Main program: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_shift is PORT ( d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); end ram_shift; architecture Behavioral of ram_shift is COMPONENT ram_shiftregister PORT ( d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; begin U0 : ram_shiftregister PORT MAP ( d => d, clk => clk, q => q ); end Behavioral;

IP core component LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY ram_shiftregister IS PORT ( d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END ram_shiftregister; ARCHITECTURE ram_shiftregister_a OF ram_shiftregister IS -- synthesis translate_off COMPONENT wrapped_ram_shiftregister

PORT ( d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_ram_shiftregister USE ENTITY XilinxCoreLib.c_shift_ram_v11_0(behavioral) GENERIC MAP ( c_addr_width => 4, c_ainit_val => "0000000000000000", c_default_data => "0000000000000000", c_depth => 16, c_has_a => 0, c_has_ce => 0, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_mem_init_file => "no_coe_file_loaded", c_opt_goal => 0, c_parser_type => 0, c_read_mif => 0, c_reg_last_bit => 1, c_shift_type => 0, c_sinit_val => "0000000000000000", c_sync_enable => 0, c_sync_priority => 1, c_verbosity => 0, c_width => 16, c_xdevicefamily => "spartan3a" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_ram_shiftregister PORT MAP ( d => d, clk => clk, q => q ); -- synthesis translate_on END ram_shiftregister_a;

Test Bench for RAM Based Shift Register:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ram_shift_test IS END ram_shift_test; ARCHITECTURE behavior OF ram_shift_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ram_shift PORT( d : IN std_logic_vector(15 downto 0); clk : IN std_logic; q : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs signal d : std_logic_vector(15 downto 0) := (others => '0'); signal clk : std_logic := '0'; --Outputs signal q : std_logic_vector(15 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ram_shift PORT MAP ( d => d, clk => clk, q => q ); clk

RTL Schematic:

Simulation Results:

EXPERIMENT 3

Aim: Modelling Xilinx Adder/Subtractor IP Core

The Xilinx IP Adder/Subtractor core provides LUT and single XtremeDSP slice add/sub implementations. The Adder/Subtractor module can create adders (A+B), Subtractor (AB), and dynamically configurable adder/Subtractor that operate on signed or unsigned data. The function

can be implemented in a single XtremeDSP slice or LUTs (but currently not a hybrid of both).

The module can be pipelined.

Features of Adder/Subtractor Drop-in module for Virtex-7 and Kintex-7,Virtex-6, Virtex-5, Virtex-4, Spartan-6, Spartan-3/XA, Spartan-3E/XA, Spartan-3A/3AN/3A DSP/XA FPGAs

Backwards compatible with version 9.1 Generates adder, subtractor and adder/subtractor functions Supports twos complement-signed and unsigned operations Supports fabric implementation inputs ranging from 1 to 256 bits wide Supports XtremeDSP slice implementations with inputs ranging from 1 to 36 or 48 bits wide Optional carry input and output Optional clock enable and synchronous clear Optional bypass (load) capability Option to set the B Value to a constant Optional pipelined operation For use with Xilinx CORE Generator software and Xilinx System Generator for DSP 13.1

Pin Description

Name Direction Description

A [N:0] Input A Input bus

B [M:0] Input B Input bus

ADD Input Controls the operation performed by an Adder/Subtractor

(High = Addition, Low = Subtraction)

C_IN Input Carry Input

C_OUT Output Carry Output

S[P:0] Output Output bus

BYPASS Input Bypass control signal loads B port onto S port

CE Input Active high Clock Enable

CLK Input Clock signal: rising edge

SCLR Input Synchronous Clear: forces outputs to a low state when driven high

SINIT Input Synchronous Initialization - forces outputs to a user defined state

when driven high

SSET Input Synchronous Set - forces outputs to a high state when driven high

VHDL Code for Synthesis:

Main Program: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY add_sub IS PORT ( a : IN STD_LOGIC_VECTOR(14 DOWNTO 0); b : IN STD_LOGIC_VECTOR(14 DOWNTO 0); clk : IN STD_LOGIC; c_in : IN STD_LOGIC; ce : IN STD_LOGIC; c_out : OUT STD_LOGIC; s : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) ); END add_sub; ARCHITECTURE add_sub_arch OF add_sub IS COMPONENT add_sub_core PORT ( a : IN STD_LOGIC_VECTOR(14 DOWNTO 0); b : IN STD_LOGIC_VECTOR(14 DOWNTO 0); clk : IN STD_LOGIC; c_in : IN STD_LOGIC; ce : IN STD_LOGIC; c_out : OUT STD_LOGIC; s : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) ); END COMPONENT; BEGIN U0 :add_sub_core PORT MAP ( a => a, b => b, clk => clk, c_in => c_in, ce => ce, c_out => c_out, s => s ); END add_sub_arch;

IP core component LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY add_sub_core IS PORT ( a : IN STD_LOGIC_VECTOR(14 DOWNTO 0); b : IN STD_LOGIC_VECTOR(14 DOWNTO 0); clk : IN STD_LOGIC; c_in : IN STD_LOGIC; ce : IN STD_LOGIC; c_out : OUT STD_LOGIC; s : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) ); END add_sub_core; ARCHITECTURE add_sub_a OF add_sub_core IS -- synthesis translate_off COMPONENT wrapped_add_sub PORT ( a : IN STD_LOGIC_VECTOR(14 DOWNTO 0); b : IN STD_LOGIC_VECTOR(14 DOWNTO 0); clk : IN STD_LOGIC; c_in : IN STD_LOGIC; ce : IN STD_LOGIC; c_out : OUT STD_LOGIC; s : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_add_sub USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral) GENERIC MAP ( c_a_type => 1, c_a_width => 15, c_add_mode => 0, c_ainit_val => "0", c_b_constant => 0, c_b_type => 1, c_b_value => "000000000000000", c_b_width => 15, c_borrow_low => 1, c_bypass_low => 0, c_ce_overrides_bypass => 1, c_ce_overrides_sclr => 0, c_has_bypass => 0, c_has_c_in => 1, c_has_c_out => 1,

c_has_ce => 1, c_has_sclr => 0, c_has_sinit => 0, c_has_sset => 0, c_implementation => 0, c_latency => 1, c_out_width => 15, c_sclr_overrides_sset => 0, c_sinit_val => "0", c_verbosity => 0, c_xdevicefamily => "spartan3a" ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_add_sub PORT MAP ( a => a, b => b, clk => clk, c_in => c_in, ce => ce, c_out => c_out, s => s ); -- synthesis translate_on END add_sub_a;

Test Bench for Adder/Subtractor:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY add_sub_test IS END add_sub_test; ARCHITECTURE behavior OF add_sub_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT add_sub PORT( a : IN std_logic_vector(14 downto 0); b : IN std_logic_vector(14 downto 0); clk : IN std_logic; c_in : IN std_logic; ce : IN std_logic; c_out : OUT std_logic; s : OUT std_logic_vector(14 downto 0) ); END COMPONENT; --Inputs signal a : std_logic_vector(14 downto 0) := (others => '0'); signal b : std_logic_vector(14 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal c_in : std_logic := '0'; signal ce : std_logic := '1'; --Outputs signal c_out : std_logic; signal s : std_logic_vector(14 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: add_sub PORT MAP ( a => a, b => b, clk => clk, c_in => c_in, ce => ce, c_out => c_out, s => s ); a

END;

RTL Schematic:

Simulation Results:

EXPERIMENT 4

Aim: Modelling a Generic Priority Encoder

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller

number of outputs. The output of a priority encoder is the binary representation of the original

number starting from zero of the most significant input bit. They are often used to control

interrupt requests by acting on the highest priority request. If two or more inputs are given at the

same time, the input having the highest priority will take precedence.

Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4

encoder made from six 4-to-2 priority encoders - four 4-to-2 encoders having the signal source

connected to their inputs, and the two remaining encoders take the output of the first four as

input. The priority encoder is an improvement on a simple encoder circuit, in terms of handling

all possible input configurations.

VHDL Code for Synthesis:

Main Program: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PRIORITY_ENCODER is port( d : in std_logic_vector(7 downto 0); output : out std_logic_vector(2 downto 0); valid : out std_logic);

end PRIORITY_ENCODER; architecture Func of PRIORITY_ENCODER is signal x : std_logic_vector(2 downto 0); begin x(0)

-- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY PRIORITY_ENCODER_TEST IS END PRIORITY_ENCODER_TEST; ARCHITECTURE behavior OF PRIORITY_ENCODER_TEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT PRIORITY_ENCODER PORT( d : IN std_logic_vector(7 downto 0); output : OUT std_logic_vector(2 downto 0); valid : OUT std_logic ); END COMPONENT; --Inputs signal d : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal output : std_logic_vector(2 downto 0); signal valid : std_logic; -- No clocks detected in port list. Replace below with -- appropriate port name --constant _period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: PRIORITY_ENCODER PORT MAP ( d => d, output => output, valid => valid ); d

Simulation Results:

RTL Schematic:

EXPERIMENT 5

Aim: Modelling a Moore FSM

The output of a Moore finite state machine (FSM) depends only on the state and not on its

inputs. This type of behaviour can be modeled using a single process with a case statement that

switches on the state value. An example of a state transition diagram for a Moore finite state

machine is shown in Fig. 12.16 and its corresponding behaviour model appears next.

VHDL Code for Synthesis:

Main Program: library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE_FSM is port (A, CLOCK: in STD_LOGIC; Z: out STD_LOGIC); end MOORE_FSM; architecture FSM_EXAMPLE of MOORE_FSM is type STATE_TYPE is (ST0, ST1, ST2, ST3); signal MOORE_STATE: STATE_TYPE; begin process (CLOCK) begin if (CLOCK = '0') then case MOORE_STATE is when ST0 => Z

if A = '1' then MOORE_STATE Z

COMPONENT MOORE_FSM PORT( A : IN std_logic; CLOCK : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal A : std_logic := '0'; signal CLOCK : std_logic := '0'; --Outputs signal Z : std_logic; -- Clock period definitions -- constant CLOCK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: MOORE_FSM PORT MAP ( A => A, CLOCK => CLOCK, Z => Z ); CLOCK

EXPERIMENT 6

Aim: Modelling a Mealy FSM

In a Mealy type finite state machine, the outputs not only depend on the state of the machine but

also on its inputs. This type of finite state machine can also be modeled in a similar style as the

Moore example case that is, using a single process. To show the variety of the language, a

different style is used to model a Mealy machine. In this case, we use two processes, one process

that models the synchronous aspect of the finite state machine and the second process models the

combinational part of the finite state machine.

In this type of finite state machine, it is important to put the input signals in the sensitivity list for

the combinational part process, since the outputs may directly depend on the inputs independent

of the clock. Such a condition does not occur in a Moore finite state machine since outputs

depend only on states and state changes occur synchronously.

VHDL Code for Synthesis:

Main Program: library IEEE; use IEEE.STD_LOGIC_1164.all; entity MEALY_FSM is port (A, CLOCK: in std_logic; Z: out STD_LOGIC); end MEALY_FSM; architecture YET_ANOTHER_EXAMPLE of MEALY_FSM is type MEALY_TYPE is (ST0, ST1, ST2, ST3); signal P_STATE, N_STATE: MEALY_TYPE; begin SEQ_PART: process (CLOCK) begin

-- Synchronous section: if (CLOCK = '0' and CLOCK'EVENT) then P_STATE if (A = '1') then Z

Test Bench for Mealy FSM: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY MEALY_FSM_TEST IS END MEALY_FSM_TEST; ARCHITECTURE behavior OF MEALY_FSM_TEST IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MEALY_FSM PORT( A : IN std_logic; CLOCK : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal A : std_logic := '0'; signal CLOCK : std_logic := '0'; --Outputs signal Z : std_logic; -- Clock period definitions --constant CLOCK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: MEALY_FSM PORT MAP ( A => A, CLOCK => CLOCK, Z => Z ); CLOCK

EXPERIMENT 7

Aim: Modelling a Clock Divider

A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an

input signal of a frequency, , and generates an output signal of a frequency:

where is an integer.

This is a clock divider code; max-count value can be set as per requirement.

For example for 1Hz frequency, set the max count to I/P frequency value viz. 1sec = 1Hz

To get time period of 1sec i.e. 1 Hz frequency, set max-count to 240000 as shown below:

1sec = 24000000 -- for i/p frequency of 24 MHz.

To calculate the max-count:

max-count = 24000000 * (1/ required frequency)

VHDL Code for Synthesis:

Main Program: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity sec_clk is Port ( Clk : in std_logic; rst: in std_logic; op : out std_logic ); end sec_clk; architecture RTC of sec_clk is constant max_count : natural := 24; -- I used 24MHz clock begin compteur : process(Clk,rst) variable count : natural range 0 to max_count; begin

if rst = '0' then count := 0; op

uut: sec_clk PORT MAP ( Clk => Clk, rst => rst, op => op ); -- Clock process definitions Clk_process :process begin Clk

Simulation Results:

RTL Schematic:

EXPERIMENT 8

Aim: Modelling a Barrel Shifter

A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one

clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an

implementation the output of one mux is connected to the input of the next mux in a way that

depends on the shift distance.

Barrel shifter takes parallel data input and give shifted output either in left or right direction by a

specific shift amount. When shift_by input is 000 it will place input data at the output without

shifting. For specifying shifting direction shift_lt_rt pin is used. When it is 0 the block will

perform left shift operation and when it is 1, it will perform right operation.

VHDL Code for Synthesis:

Main Program: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity barrel_shifter is port ( d_in : in std_logic_vector(7 downto 0); -- input vector d_out : out std_logic_vector(7 downto 0); -- shifted output shift_lt_rt : in std_logic; -- 0=>left_operation 1=>right_operation shift_by : in std_logic_vector(2 downto 0); -- shift amount clk : in std_logic; -- clock signal rst_a : in std_logic; -- reset signal p_load : in std_logic); -- parallel load

end barrel_shifter; architecture beh of barrel_shifter is begin -- beh p1: process (clk,rst_a,shift_by,shift_lt_rt) variable x,y : std_logic_vector(7 downto 0); variable ctrl0,ctrl1,ctrl2 : std_logic_vector(1 downto 0); begin -- process p1 ctrl0:=shift_by(0) & shift_lt_rt; ctrl1:=shift_by(1) & shift_lt_rt; ctrl2:=shift_by(2) & shift_lt_rt; if(rst_a = '1') then d_out

Simulation Results:

Test Bench for Barrel Shifter: LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY barrel_test IS END barrel_test; ARCHITECTURE behavior OF barrel_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT barrel_shifter PORT( d_in : IN std_logic_vector(7 downto 0); d_out : OUT std_logic_vector(7 downto 0); shift_lt_rt : IN std_logic; shift_by : IN std_logic_vector(2 downto 0); clk : IN std_logic; rst_a : IN std_logic; p_load : IN std_logic ); END COMPONENT; --Inputs signal d_in : std_logic_vector(7 downto 0) := (others => '0'); signal shift_lt_rt : std_logic := '0';

signal shift_by : std_logic_vector(2 downto 0) := (others => '0'); signal clk : std_logic := '0'; signal rst_a : std_logic := '0'; signal p_load : std_logic := '0'; --Outputs signal d_out : std_logic_vector(7 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: barrel_shifter PORT MAP ( d_in => d_in, d_out => d_out, shift_lt_rt => shift_lt_rt, shift_by => shift_by, clk => clk, rst_a => rst_a, p_load => p_load ); -- Clock process definitions clk_process :process begin clk

wait for 300 ns; rst_a