Ic Design Front End Sol

8/3/2019 Ic Design Front End Sol

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IC Design Front-End Solution

Gateway, SmartSpice, and SmartView


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Gateway, SmartSpice and SmartView Agenda

Silvacos Solution for Analog IC Front-End DesignGateway Schematic Capture and EditorSmartSpice Analog Circuit SimulatorSmartView Waveform Viewer and Post-Processor

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Gateway, SmartSpice and SmartView Agenda


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Silvacos Solution for Analog IC Front-End Design

Gateway- Schematic Capture and EditorSmartSpice- Berkeley based SPICE simulatorSmartView- Graphical postprocessorAdvantages

Easy transition from other popular IC design toolsUser-friendly and intuitive design environmentDesign portability between platforms (SunOS, Windows, Linux)PDKs (process design kits) to provide standard pre-built design models, cells,

symbols, schematics for participating foundries

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Analog/Mixed-Signal Design Flow

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Agenda: Schematic Capture and Editor


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Gateway Schematic Capture and Editor

Powerful front-end schematic editor and viewerTightly integrated with Silvacos SmartSpice and Smartview toolsCreates multi-sheet, multi-view, hierarchical, or flat designsImport\export of EDIF 2 0 0 schematics, symbols, and cellsIntuitive left-to-right toolbar implementation to mirror design flowDialog box approach for building SPICE analysis control cardsAnalog environment for ease of saving and plotting vectorsAbility to switch processes and run process variant simulations on the

same schematicGenerate both SPICE netlist and LVS netlist from same schematicHierarchical DC bias for all currents and voltages

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Schematic showing allpaned areas which aremay be moved, resized,

docked, undocked, or

hidden


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Schematic Area may bemaximized for largest

possible drawing area

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Two Modes of Operation Capture

Place Edit Check Save

SimulationCapture mode shown at left

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Two Modes of Operation Capture Simulation

Netlist

Control Cards Setup Analysis Choose Vectors

Save March

Simulate Postprocess

Simulation mode shownat left


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Session area:Reports schematic

editing actions,

warnings, and errors

Reports creation ofinput deck and netlist

Reports simulationfeedback fromSmartSpice

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Hierarchical ascendingand descending in designand simulation modes

View any level or levels ofa design per userconfiguration


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Gateway Editing Instance Attributes

Spreadsheet style editorChanges in a single attribute

dialog may apply to:

Only selected instance

Selected instancesMatching symbol instancesAll instances

Easy to change device models forall devices and generate

subsequent runs

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Gateway Symbol EditorDefine symbol type as:

Primitive MOS, Bipolar, active, passive

Special

GND, power, bus, PARAMSSub-schematic

Descend into circuit and passparameters

Netlist Attach .SUBCKT netlist via file to

symbol

Verilog-A Attach Verilog-A module via file to

symbol

Define symbol pins to have a fixed or non-fixed signal name at instance level

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Gateway Symbol Editor

Define attributes to bechangeable or fixed for the

instance level

Define expressions to bepassed into the SPICE

netlist

Set attribute default valuesand visibilities

Edit SmartSpice andGuardian Strings

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Gateway SmartSpice and Guardian Strings

Schematic Drawings generate two netlists:SmartSpice netlist (represents simulation netlist)Guardian netlist (represents LVS netlist)

Each symbol contains two strings:SmartSpice StringGuardian String

Example: 4 terminal npn device (references a subcircuit definition forSmartSpice and a BJT transistor for LVS)

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SmartSpice String:X_@PREFIX@PATH %C %B %E %VSUB XNPN AREA=@W $M

SmartSpice Netlist:X_Q27 NET8 BANDGAP NET2 GND XNPN AREA=1.5U M=1X_Q28 BANDGAP NET8 NET3 GND XNPN AREA=5U M=1

Guardian String:@PREFIX@PATH %C %B %E %VSUB NPN AREA='(1.25U*AREA)'

Guardian Netlist:Q27 NET8 BANDGAP NET2 GND NPN AREA='(1.25U*AREA)'Q28 BANDGAP NET8 NET3 GND NPN AREA='(1.25U*AREA)'


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Hierarchical design checkingand reporting system

Zoom to error for eacherror found

Automatically opens anylevel with error when error

is selected in report

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Gateway - Customize Settings

Set and save default settings forindividuals or workgroups to file

Choose settings for integrated toolsincluding:

Set versions for SmartSpice andSmartView

Parallel SPICE and marchingwaveforms

Customized initialization filesSchematic and symbol grid settingSheet Border templatesUser-defined shortcuts and bindkeysColor settingsAutosave and recovery

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Gateway Control Deck Builder

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Design Flow

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Gateway Creating Netlists and Input Decks

Netlists and input decks automaticallycreated by Gateway

Netlists can be made as top-down oras .SUBCKT format

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Gateway Pre-Simulation

Choose which analysis to plotSelect what to be plotted:

Voltage markers on nodesCurrent markers on pins

Select what to be savedAll currents and voltagesOnly what is markedSave from control deckParametric data

Plot to:Existing plotCreate new plotOverlay simulation runs

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Gateway During Simulation

Run-time dialogFinal simulation timeCurrent simulation

time

TimestepTemperatureNumber of CPUs

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Gateway DC Bias Current and Voltage

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DC Bias Display When DCOP calculation

is finished

Annotate Voltage Annotate Current Operates through

heriarchy


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Gateway After Simulation

SmartSpice finishessimulation

SmartSpice writes*.raw and *.out files

SmartView is launchedThe *.raw file is loaded

automatically intoSmartView

Ready for cross-probing

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Gateway Running Verilog-A Circuits

Verilog-A modules maybe mapped directly to

symbols

Verilog-A circuits may beas compact models or

as behavioral blocks, or

both

Verilog-A circuits andregular analog primitive

circuits may be mixed

together and simulated

Results from analogprimitive circuit and

Verilog-A can be

measured and overlaid

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Gateway File Handling

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Agenda: SmartSpice Analog Circuit Simulator


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SmartSpice Analog Circuit Simulator

Industry leader in analog IC designsimulation

Berkeley SPICE compatible Superior simulator in speed and

convergence

100% HSPICE compatible for netlists,models, analysis features, and results

Capacity - up to 400 thousand activedevices in 32 bit and 8 million active

devices in 64 bit version

Modular design to include solvers,parsers, models, and engine

Supports latest technologies Supported on Solaris, Linux, and

Windows

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SmartSpice Analog Circuit Simulator

SmartSpice may be run three ways:Batch Mode

Run cell characterization Command line driven Generates HSPICE compatible files (*.tr,

*.mt, *.ac)

Interactive Mode GUI interface Easy access to simulation information and

input deck

Environment to manage designs Integrated to postprocessor

Schematic Mode Run directly from schematic capture

environment

Schematic changes automatically update thenetlist and input deck for up-to-the-minute

simulation environment

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SmartSpice Interactive Mode

Drag and drop input decks Choose an analysis Choose what to save or plot Run Simulation Display Statistics Open vector menu and plot results

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SmartSpice File Handling

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Agenda: SmartView Waveform Viewer and Post-Processor


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SmartView Graphical Post-Processor

Industry driven waveformanalysis tool

Hierarchical or flat vector arrangementPre-filtering of data to streamline results

View histories of concurrent simulations onone plot

Vector Calculator with:Built-in SPICE macros and functionsCapability for user-defined functions

View *.raw, *.ac0, and *.tr0 formatsSupported on Solaris, Linux, and Windows

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User-sizeable areas for plots, lists,and data

Drag and drop capability from vectortree into plot

ToolbarsStandardCustomizableDockable

Merge or delete vectors across singleor split plots

Undo and redo capability

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Various measuring devices View more than one rawfile at a time Simultaneous zooming between

plots

Time synchronized panning andzooming between plots

Changing axis from linearto log

Context sensitive menus for all plotobjects

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SmartView Measurements Tools

Plot to: Cartesian Polar Smith Spectral Density Histogram

Measurement Dialogs: Rise time RMS Min,max (P-P) Delay Period Overshoot Average Derivative Inetgral

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SmartView Analyzing Parametrics

Parametric AnalysisView sweeps mergedView sweeps separate by variable

and value

Ability to combine and split sweepsSweep manager

Manage all sweeps in rawfileChoose which sweeps to displayHandles multiple parametric runs

and secondary sweeps

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Conclusion

AMS Toolflow EnvironmentSchematic, Simulation, and Postprocessor tightly integratedUnified GUI environment for seamless interactionDesigns can be ported easily between platforms

Solaris, Windows, LinuxCompatible with major foundry design kitsEasy transition into Silvaco flow from other vendors

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Date post:	06-Apr-2018
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Ic Design Front End Sol

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