1

IC Process Technologies

ECE222

2

From Ingot to Chip

Film Formation– Epitaxy– Oxidation– Deposition– Sputtering

Silicon crystal ingot Slicing into Silicon Wafers IC Chip Fabricated

Film Patterning– Lithography– Etching– Lift-off

Film Doping– Diffusion– Implantation

Other– CMP– Packaging

3

Wafer, Chip and Device

Wafer Chip Device

4

MOSFET Device Structure

PolysiliconAluminum

5

Modern MOSFET Device Structure

6

(a) Define n-well diffusion (mask #1)

(b) Define active regions (mask #2)

(c) LOCOS oxidation

N-Well CMOS Process

(d) Polysilicon gate (mask #3)

7

Threshold Voltage Adjustment Using Boron Ion Implantation

8

(h) Metallization (mask #7)

N-Well CMOS Process (cont.)

(f) p+ diffusion (mask #5)

(g) Contact holes (mask #6)(e) n+ diffusion (mask #4)

9

n- and p-MOSFET

10

PN Junction Diode

11

Integrated Resistors

12

Integrated Resistors (cont.)

shRWLR =

Sheet resistance

13

Integrated Capacitors

14

Integrated Capacitors (cont.)

MOSCAP PN Junction Capacitor

15

Integrated Inductors

Layout

Cross section

Model

16

Bipolar Transistor Structure

17

Bipolar Process

(e)

(f)

(g)

(h)

18

Self-Aligned Double-Poly Bipolar Transistor

19

Self-Aligned Double-Poly Bipolar Process

20

BiCMOS Process

21

Lateral PNP Transistor

22

p-Base and Pinched p-Base Resistors

23

SiGe BiCMOS Process

24

GaAs MESFET Process

25

Layout

26

Corresponding Cross Section

27Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d), (e), and (f) dark-field masks; (b), (c), and (g) clear-field masks.

Mask

28

Further Reading• Sedra & Smith, A.2, A.3.• S.M. Sze, Semiconductor Devices: Physics and

Technology, 2nd ed., Chp. 14• International Technology Roadmap for

Semiconductors, http://public.itrs.net