ICCAD 2003 Manufacturing-Aware Physical Design Andrew B. Kahng Puneet Gupta (Univ. of Calif. San...

ICCAD 2003http://vlsicad.ucsd.edu

Manufacturing-Aware Physical Design

Andrew B. Kahng

Puneet Gupta(Univ. of Calif. San Diego)


Outline

• Challenges• “DFM Philosophy”• Manufacturing and Variability Primer• Design for Value• Composability• Performance Impact Limited Fill Insertion• Function Aware OPC• Systematic Variation Aware STA• Futures of Mfg-Aware PD


Printing

0.25µ 0.18µ

0.13µ 90-nm 65-nm

Layout

Figures courtesy Synopsys Inc.


Data Volume Explosion

Number of design rules per process node

180nm 130nm 90nm 70nm0

50

100

150

200

250

300

350

ME

BE

S D

ata

Vo

lum

e (G

B)

MEBES Data Volume vs. Technology Node

MEBES file size for one critical layer vs. technology node


RET Layers Explosion


0%

70%

180nm 150nm 130nm 90 nm

Source: TSMC Technology Symposium, April 22 2003

Number of TSMC Mask Layers Using OPC/PSM


Design Rules Explosion


0

100

200

300

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500

600

700

0.35um 0.25um 180nm 150nm 130nm 90nm


Variation: Across-Wafer Frequency


Variation: Leakage• Subthreshold leakage current varies exponentially

with threshold voltage: I exp(-Vth)

• Vth = f(channel length, oxide thickness, doping)

– Most affected by variations in gate length

±10% Ld

±100% Isub

Dennis Sylvester, U. Michigan


Outline

• Challenges• “DFM Philosophy”• Manufacturing and Variability Primer• Design for Value• Composability: PSM and Assists• Performance Impact Limited Fill Insertion• Function Aware OPC• Systematic Variation Aware STA• Futures of Mfg-Aware PD


Symptoms: Routing Rules (1)• Minimum area rules and via stacking

– Stacking vias through multiple layers can cause minimum area violations (alignment tolerances, etc.)

– Via cells can be created that have more metal than minimum via overlap (used for intermediate layers in stacked vias)

• Multiple-cut vias– Use multiple-cut vias cells to increase yield and reliability

• Can be required for wires of certain widths– Multiple via cut patterns have different spacing rules

• Four cuts in quadrilateral; five cuts in cross; six cuts in 2x3 array; …

• With wide-wire spacing rules, complicates pin access– Cut-to-cut spacing rules check both cut-to-cut and metal-

to-metal when considering via-to-via spacing


• Width- and Length-dependent spacing rules– Width-dependent rules: domino effects– Variant: “parallel-run rule” (longer parallel runs more

spacing)– Measuring length and width: halo rules affect computation

• Influence rules or stub rules– A fat wire, e.g., power/ground net, will influence the spacing

rule within its surroundings any wire that is X um away from the fat wire needs to be at least Y um away from any other geometry.

– Example: fat wire with thin tributaries• bigger spacing around every wire within certain distance of the thin

tributaries• ECO insertion of a tributary causes complications• Strange jogs and spreading when wires enter an influenced area

Symptoms: Routing Rules (2)


Example: LEF/DEF 5.5, April 2003


Example: LEF/DEF 5.5, April 2003


• Density– Grounded metal fills (dummy fill*)– Via isodensity rules and via farm rules (via layers must be filled

and slotted, have width-dependent spacing rule analogs, etc.)• Non-rectilinear (-geometry) routing

– X-Architecture: http://www.xinitiative.org/• Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/ , LSI

Logic patents– Landing pad shapes (isothetic rectangle vs.. octagon vs.. circle),

different spacings (~1.1x) between diagonal and Manhattan wires, etc.

• More exceptions– More non-default classes (timing, EM reliability, …)

• Not just power and clock– >0.25um width may be “wide” many exceptions

Symptoms: Routing Rules (3)


Symptoms: Routing Rules

• Degrade completion rates, runtime efficiency

• “Postprocessing” likely no longer suffices – E.g., antennas

• There is no chip until the router is done

• Must / Should / Can tomorrow’s IC routers “independently” address these issues?


• Mask NRE cost ( runtimes shapes complexity)

• BEOL catastrophic yield loss– Deposited copper can infer yield loss mechanisms

• Open faults more prevalent than short or bridging faults• High-resistance via faults• Cf. “non-tree routing” for reliability and yield?

– Variability budget for planarization• Copper is soft dual-material polish mechanisms• Oxide erosion and copper dishing cross-sectional

variability, inter-layer bridging faults, …

• Low-k: thermal properties, anisotropy, nonuniformity• Resistivity at small conductor dimensions

Whose Job Is It To Solve:


The Problem: Evolution• Conflicting goals

– Designer: “freedom”, “reuse”, “migration”– EDA: “maintenance mode”– Process/foundry: “enhance perceived value”

(= add rules) Prisoner’s Dilemma: who will invest in change?

• Fiddling: Incremental, linear extrapolation of current trajectory– “GDS-3”– Thin post-processing layers (decompaction, RET

insertion, …)– Leads to “dark future” (12th Japan DA Show keynote)


0%

20%

40%

60%

80%

100%

Intel IBM Synopsys TUE-Magma

Cadence STMicro

Variability/Litho/Mask/Fab Low Power/Leakage

Power Delivery/Integrity Tool/Flow Enhancements/OA

IP Reuse/Abstraction/SysLevel Design DSM Analysis

P&R and Opt Others (Lotto)

DAC-2003 Nanometer Futures Panel:Where should extra R&D $ be spent?


The Solution: Co-Evolution• Designer, EDA, and process communities cooperate and co-evolve to maintain the

cost (value) trajectory of Moore’s Law – Must escape Prisoner’s Dilemma– Must be financially viable– At 90nm to 65nm transition, this is a matter of survival for the worldwide semiconductor

industry


Today’s Design-Manufacturing Interfaces

Litho/Process(Tech. Development)

Library(Library Team)

Layout & libs (Corner Case

Timing)

Design(ASIC Chip)

Mask: Dataprep(Mask House)

Design RulesDevice Models

Tapeout Layout

(collection of polygons ?)

RET

Guardbanding all the way in all stages!! (e.g. clock ACLV guardband ~ 30%)

What do we lose ?• Performance Too much worst-casing• Turnaround time Huge OPC runtimes, overdesign• Predictability RET is applied post-design• Mask costs Overcorrection• Designer’s intent RET is not driven by design


• Bidirectional design-manufacturing data pipe– Fundamental drivers: cost, value

• Pass functional intent to manufacturing flow– Example: RET for predictable timing slack, leakage, yield

– RETs should win $$$, reduce performance variation

cost-driven, parametric yield constrained RET

• Pass limits of manufacturing flow up to design– Example: avoid corrections that cannot be manufactured

or verified e.g., design should be aware of metrology

N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/

Foundation of the DFM Solution


This Tutorial• Concrete examples of Manufacturing-Driven PD• Deployable today• Topic 1: Composability: PSM and SRAF• Topic 2: Performance impact limited fill insertion• Topic 3: Function Aware OPC• Topic 4: Library-based OPC for predictability • Topic 5: Focus and proximity-effects aware STA• Some ramblings about future: regular layout, robust optimization, leakage saving without multi-Vt

• We will start with a “manufacturing primer” …


Outline

• Challenges• “DFM Philosophy”• Manufacturing and Variability Primer

– Lithography, Masks and Process Variations• Design for Value• Composability• Performance Impact Limited Fill Insertion• Function Aware OPC• Systematic Variation Aware STA• Futures of Mfg-Aware PD


oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic Process


Lithography Primer: Basics• The famous Raleigh Equation:

: Wavelength of the exposure systemNA: Numerical Aperture (sine of the capture angle of the lens, and is a measure of the size of the lens system)

k1: process dependent adjustment factor • Exposure = the amount of light or other radiant energy

received per unit area of sensitized material. • Depth of Focus (DOF) = a deviation from a defined reference

plane wherein the required resolution for photolithography is still achievable.

• Process Window = Exposure Latitude vs. DOF plot for given CD tolerance


Numerical Aperture

•NA=nsin n=refractive index for air, UB =1. Practical limit ≈ 0.93

•NA increase DOF decrease

• Immersion lithography ? n>1 (e.g., water)

Figures courtesy www.icknowledge.com


k1

•k1 is complex process depending on RET techniques, photoresist performance, etc

•Practical lower limit ≈ 0.25

•Minimum resolvable dimension with 193nm steppers = 0.25*193/0.93 = 52nm

Source: www.icknowledge.com


• The light interacting with the mask is a wave• Any wave has certain fundamental properties

– Wavelength ()– Direction– Amplitude– Phase

• RET is wavefront engineering to enhance lithographyby controlling these properties

RET Basics

-4

-3

-2

-1

0

1

2

3

4

-20 0 20 40 60 80 100

B

Amplitude

Direction

Phase

Courtesy F. Schellenberg, Mentor Graphics Corp.


Direction: Illumination

• Regular Illumination • Many off-axis designs (OAI)

– Annular

– Quadrupole / Quasar

– Dipole

+

or


Acceptable

Unacceptable

130 nm lines, printed at different pitches

Quasar illuminationNA=0.7

Iso

late

d

De

nse

OAI: Impact on PD

• Off axis amplifies certain pitches at the expense of the others “Forbidden” pitches– Quasar / Quadrupole

Illumination • Amplifies dense 0°, 90 °

lines• Destroys ±45° lines

– Dipole Illumination• Prints only one orientation• Must decompose layout for

2 exposures

Depth of Focus

Graph reference: Socha et al. “Forbidden Pitches for 130 nm lithography and below”, in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000), 1140-1155.

0

0.5

1

1.5

200 400 600 800 1000 1200 1400

Without SRAF

Pitch (nm)


Amplitude: OPC

• Optical Proximity Correction (OPC)modifies layout to compensate for process distortions– Add non-electrical structures to layout

to control diffraction of light– Rule-based or model-based


OPC: Assist Features

• SRAF = Sub-Resolution Assist Feature ≡ SB = Scattering Bar ≡ Assists

• SRAFs make isolated lines “behave” as dense• SRAF are not supposed to be printed on wafer but exist on

mask

Dense CDwindow

Iso CDwindow

Defocus

Exposur

e

Process Overlap Window

Iso-window after SRAF insertion


Phase: PSM

• Phase Shifting Masks (PSM) etch topography into mask– Creates interference fringes on the wafer

Interference effects boost contrast Phase Masks can make extremely small gates

conventional maskglass Chrome

Electric field at mask

Intensity at wafer

phase shifting mask

Phase shifter


Double-Exposure Bright-Field PSM

0

180180 + =


The Phase Assignment Problem

• Assign 0, 180 phase regions such that critical features with width < B are induced by adjacent phase regions with opposite phases

0 180

<B

shifters


Key: Global 2-Colorability

?180 0

0180 180

180

• Odd cycle of “phase implications” layout cannot be manufactured– layout verification becomes a global, not local, issue


Phase Assignment for Bright-Field PSM• PROPER Phase Assignment:

–Opposite phases for opposite shifters –Same phase for overlapping shifters

Overlapping shifters


F4

F2

F3

F1

Critical features: F1,F2,F3,F4


F4

F2

F3

F1

Opposite-Phase Shifters (0,180)


F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Shifters: S1-S8

PROPER Phase Assignment:– Opposite phases for opposite shifters – Same phase for overlapping shifters


F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Phase Conflict

Proper Phase Assignment is IMPOSSIBLE

Phase Conflict


F4

F2

F3

F1

S1

S2

S3

S5

S4

S6

S7S8

Phase Conflictfeature shiftingto remove overlap

Conflict Resolution: Shifting


F4

F2

F1

S1

S2

S3 S4

S7S8

Phase Conflictfeature widening to turnconflict into non-conflict

Conflict Resolution: Widening

F3


Minimum Perturbation Problem

• Layout modifications–feature shifting–feature widening

area increase, slowing down

manual fixing, design cost increase

• Minimum Perturbation Problem: Find min # of layout modifications leading to proper phase assignment. [Kahng et al. ASPDAC 2001]


Mask Costs(1)

Design Mask

OPC Fracture

Mask Cost Data Volume

OPC, PSM, Fill increased feature complexity increased mask cost

Figure courtesy Synopsys Inc.


Mask Costs(2)

Half of all mask sets used for < 570 wafers (< 100K parts)

Writing-Optical or e-beam

Defect Inspection

Defect Repair

Data Prep.-OPC conversion/e-beam file

Materials

Others

0 10 20 30 40

Weight in Mask Cost (%)

Vector scan: Write cost proportional to feature complexity

Difficult to inspect, verify masks!


• IC manufacturing process affected by random disturbances – different silicon dioxide growth rates, mask

misalignment, drift of fabrication equipment operation, etc….

– These disturbances are often uncontrollable and affect the circuit performance

• Yield: percentage of manufactured products that pass all performance specifications– Parametric yield (process variations)

• What is the performance of the manufactured chips?

– Catastrophic or functional yield (defects)• How many chips work?

Manufacturing Yield


Process Variation Taxonomy

• Spatial scale:– Die-to-Die or Inter-Die. E.g.

Focus, etch– Within-Die or Intra-Die. E.g.

lens aberration, diffraction effects

• Nature:– Random. E.g. batch-to-match

material variation– Systematic. E.g. diffraction-

based proximity effects– Systematic but difficult to

model variations random


Process Variation Sources

• Wafer: topography, reflectivity• Reticle: CD error, proximity effects, defects• Stepper: Lens heating, focus, dose, lens

aberrations• Etch: Power, pressure, flow rate• Resist: Thickness, refractive index• Develop: Time, temperature, rinse• Environment: Humidity, pressure


Simulation of Variation

• Value X for a given parameter for a device i in path j in the kth Monte-Carlo run is given by

– RAN-WID: Random within-die variation– RAN-DTD: Random die-to-die variation– SYS-WID: Systematic within-die variation– SYS-DTD can not be accounted for at die-scale


Simulation of Variation (2)

• (, ) for various components should be correctly reconstructed depending on their initial decomposition at the litho stage

Systematic effects should be correctly accounted for. Treating them as random is an oversimplification


“Ideal” Sampling ?

• RowWID– row = WID

• ColumnDTD– col = DTD

x11 x1n

xm1 xmn

Devices on a die die

/MC

sim

s

s

• Systematic variation, correlationsfurther dependence within rows and columns

• Can such a multi-variate distribution be sampled? Is it even feasible ?

• What is the relation between of various components in this case ?


Distributions: Gaussian ??

• Etch variation is radial– Less die at center than periphery CD variation due to

etch is asymmetric

• Focus based CD variation– Behavior of Isolated and dense lines systematicallydifferent pattern dependentvariation– Post-SRAF insertion, CDdistribution biased towardsdense lines asymmetry– More on this later..


Outline



AMD Processors

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400

450

0 200 400 600 800 1000 1200 1400 1600

Clock Speed (MHz)

Pri

ce

($

)

Athlon MP

Athlon 4 Mobile

Athlon Desktop

Duron

Duron Mobile

Mapping Design to Value: Selling Points


Design for Value (DFV)*

• Mask cost trend Design for Value (DFV)

Design for Value Problem: Given

• Performance measure f• Value function v(f)

• Selling points fi corresponding to various values of f

• Yield function y(f)

Maximize Total Design Value = i y(fi)*v(fi)[or, Minimize Total Cost]

• Probabilistic optimization regime* See "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", IEEE ASIC/SoC Conference,

September 2002, pp. 411-415.


DFV vs. Design for Performance (DFP)

• DFP:

– T = circuit delay – yi = process parameters – xi = design parameters

• DFV:

– Tm = Selling point delay– PT = Cumulative probability (yield)


Example: Repeater Insertion

• 130nm single repeatered 5mm global line with ITRS based Leff variation considered

• Repeater location is varied

• DFP: nominal delay optimized

• DFV: Yield at given threshold delay optimized DFV and DFP

optima are different


DFV: Impact of #critical paths

• DFP optimizationA “wall” of optimized critical pathsincrease in expected circuit delay in presence of variation

• Intentional “under-optimization” ? E.g., [IBM DAC’02]

Timing slackPre-O

pt

Pos

t-O

ptm

anuf

actu

red

#P

ath

s


Statistical Static Timing

• Important component of DFV is a statistical static timing analysis (SSTA)

• Simplest SSTA: Monte-Carlo STA– Sample process parameters from their

distributions– Generate a delay value for every timing arc– Update SDF and run standard STA– Repeat statistically significant no. of times

and generate a circuit delay distribution


SSTA: Other Approaches

• Problem is to compute distribution of maximum of random variables – Intelligent Monte-Carlo [UCSB DAC’02]– Bound-based [UCB DAC’02], [IBM DAC’03],

[UMich TAU’02]

• Problems with current approaches:– Runtime, scalability– Ability to handle correlations– Ability to handle non-Gaussian distributions– Incremental SSTA ?


Outline

• Challenges• “DFM Philosophy”• Manufacturing and Variability Primer• Design for Value• Composability

– PSM and Assists• Performance Impact Limited Fill Insertion• Function Aware OPC• Systematic Variation Aware STA• Futures of Mfg-Aware PD


Conflict Graph for Cell-Based Layouts

• Coarse view: at level of connected components of conflict graphs within each cell master

• each of these components is independently phase-assignable

• can be treated as a single “vertex” in coarse-grain conflict graph

edge in coarse-grain conflict graph

cell master A cell master Bconnected component


Standard-Cell PSM

• Must: Free composability of standard cells

– Exit placer with a phase-shiftable layout

– No loops back into the placer

• RETs may interfere: unique master cell with only one instantiation causes area loss

• Can exploit:

– Multiple phase-shifted versions of master cell

–Version-composability matrix


Taxonomy of Composability

• (Same) Same row composability: any cell can be placed immediately adjacent to any other

• (Adj) Adjacent row composability: any two cells from adjacent rows are freely combined

• Four cases of cell libraries G = guaranteed composability NG = non-guaranteed composability

– Adj-G/Same-G free composability– Adj-G/Same-NG less free– Adj-NG/Same-G painful– Adj-NG/Same-NG non-starter…


Taxonomy of Composability

VDD

VDD

GND

VDD

VDD

GND

VDD

VDD

GND

Adj-G/Same-NG

Adj-NG/Same-G

Adj-NG/Same-NG


Adj-G/Same-NG: Versioning

GIVEN: order of cells in a row

version compatibility matrix

FIND: version assignment such that versions of adjacent cells are compatible

• (BFS) traversal of DAG– nodes = versions– arcs = compatibility


Adj-G/Same-NG: ShiftingGIVEN:

- order of cells in a row (or “optimal” placement)

- version compatibility weighted matrix (weight = #extra sites)

FIND: version assignment minimizing either total # of extra sites or total/max displacement from optimal placement

• Dynamic Programming O(kV) k = max displacement


Assist Features and Variation

• SRAFs are dummy geometries– Improve process window

overlap for dense and isolated features

– Not supposed to be printed– Unavoidable for 90nm poly

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

0.0 0.1 0.2 0.3 0.4 0.5 0.6

SB2 SB1 No SB

2 SB 1 SB W/O SBDOF

CD

SB = Scattering Bar SRAF


Layout Composability for SRAFs

• Feature spacings are restricted to a small set• Two components

– Assist-correct library layouts Inter-device spacing within a standard cells Intelligent library design

– Assist-correct placement space between cells needs to be adjusted Intelligent whitespace management

x+x x

Better than


Assist-Correct Placement

• Change whitespace distribution to make the placement assist-correct

• Can be formulated and solved as a post-placement minimum perturbation problem

• Does not work well with cell layouts having non-preferred direction critical poly

wss1

s2

s3

s4

(s1+s3+ws)2 Assist-Corr.-set

(s2+s4+ws)2 Assist-Corr.-set


Outline



CMP & Area Fill

Area fill feature insertionDecreases local density variation Decreases the ILD thickness variation after CMP

Post-CMP ILD thicknessFeatures

Area fillfeatures

wafer carrier silicon wafer

polishing pad

polishing table

slurry feeder

slurry

Chemical-Mechanical Planarization (CMP)Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step


Fixed-Dissection Regime• To make filling more tractable, monitor only fixed set of w w

windows

– offset = w/r (example shown: w = 4, r = 4)

• Partition n x n layout into nr/w nr/w fixed dissections

• Each w w window is partitioned into r2 tiles

w/r

Overlapping windows

w

n

tile


Density Control Objectives

Objective for Manufacture = Min-Var [Kahng et al., TCAD’02]

minimize window density variation subject to upper bound on window density

Objective for Design = Min-Fill [Wong et al, DAC’00]

minimize total amount of added fill subject to UB on window density variation


Performance-Impact Limited Area Fill (PIL Fill)

• Why?– Fill features insertion increased

capacitance increased interconnect delay and crosstalk

– Post-tapeout fill synthesis Incorrect timing closure ?

Filled layout

General guidelines:• Minimize total number of fill features• Minimize fill feature size• Maximize space between fill features• Maximize buffer distance between original and fill

features


PIL Fill FormulationGiven

• A fixed-dissection routed layout• Design rule for floating square fill features• Prescribed amount of fills in each tile

Fill layout with the following objective:

Max-MinSlack-Fill-Constrained (MSFC) : Maximize minimum post-fill slack over all nets, subject to layout density constraints

[Chen et al, DAC’03]


Capacitance and Delay Models• Interconnect capacitance = Overlap + Coupling + Fringe• Fringe, Overlap require cognizance of multiple layers

Consider fill impact on coupling capacitance only• Elmore delay model incremental additivity of delay with

added parasitic capacitance

top view

buffer distance

fill gridpitch

Activelines

w

– Capacitance between two active lines separated by distance d, with m fill features in one column:

wmd

aCap r

0


Iterated MSFC Fill Approach1.Run STA and sort fill columns in decreasing order

of timing slack

2.Greedily insert fill into columns till1. Fill requirement of tile is met; or

2. No column with slack > LB remains; or

3. Total added delay due to fill > UB

3.Decrease LB, UB. Update parasitics.

4. If fill requirement of tile is not met, goto 1

5.Pick next tile to be filled. Goto 1 UB, LB are iteration variables to control accuracy vs. STA

iterations tradeoff. More details in [Chen et al, DAC’03]


Experiments for MSFC PIL-Fill

Normal fill flow LP/Monte-Carlo (TCAD’02)

Iterated Greedy Approaches for MSFC PIL-Fill

-1000

-500

0

500

1000

1500

2000

2500

1 2 3 4 5 6

Testcases

M i n

i m

u m

S

l a

c k

(p

s)

Orig MinSlack

Normal MinSlack

MSFC MinSlack


Outline

• Challenges• “DFM Philosophy”• Manufacturing and Variability Primer• Design for Value• Composability• Performance Impact Limited Fill Insertion• Function Aware OPC

– Minimizing cost of corrections– Library-based correction

• Systematic Variation Aware STA• Futures of Mfg-Aware PD


DFV at Process Level: Function-Aware OPC

• Annotate features with “required amount” of OPC– E.g., why correct dummy fill?– Determined by design properties such as setup and hold

timing slacks, parametric yield criticality of devices and features

• Reduce total OPC inserted (e.g., SRAF usage)– Decreased physical verification runtime, data volume– Decreased mask cost resulting from fewer features

• Supported in data formats (OASIS, IBM GL-I, OA/UDM)– Design through mask tools need to make, use annotations

• N.B.: General RET trajectory: rules models libraries


DFV in OPC RegimeGiven: Admissible levels of (OPC) correction for each layout feature, and corresponding delay impact (mean and

variance)

Find: Level of correction for each layout feature, such that a prescribed selling point delay is attained

Objective: Minimize total cost of corrections


Variation-Aware Library Models

• Each capacitance or delay value replaced by (,) pair• Variation aware .lib

pin(A) { direction : input; capacitance : (0.002361,0.0003) ; } …timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 ("0.028, 0.044, 0.076"); index_2 ("0.00158, 0.004108, 0.00948"); values ( \ “(0.04918,0.001), (0.05482,0.0015), (0.06499,0.002)", ….


Correction = Mask Cost = CD Control

• Levels of RET = levels of CD control

OPC solutions due to K. Wampler, MaskTools, March 2003

CD studies due to D. Pramanik, Numerical Technologies, December 2002

Type of OPC Ldrawn (nm)

3 of Ldrawn

Figure Count

Delay (, ) for NAND2X1

Aggressive 130 5% 5X (64.82, 2.14)

Medium 130 6.5% 4X (64.82, 2.80)

No OPC 130 10% 1X (64.82, 4.33)

• Levels of RET = Levels of CD control


Generic SSTA-Based Cost of Correction Methodology

• Statistical STA (SSTA) provides PDFs of arrival times at all nodes

• Assume variation aware library models (for delay) are available

• Statistical STA currently has runtime and scalability issues

SSTA

Nominally Correct SP&R Netlist

Min. CorrectedLibrary

Yield Target met

?EXIT

CorrectionAlgorithm

SSTA

All CorrectionLibraries

All CorrectionLibraries

Y

N


MinCorr: Parallels to Gate Sizing

• Assume– Gaussian-ness of distributions prevails

+ 3 corresponds to 99% yield

– Perfect correlation of variation along all paths Die-to-Die variation 1+2 + 31+2 = 1 + 31 + 2 + 32

• Resulting linearity allows propagation of (+3) or 99% (selling point) delay to primary outputs using standard Static Timing Analysis (STA) tools

• (See DAC-2003 paper)


MinCorr: Parallels to Gate Sizing

Gate Sizing MinCorr

Cell Area Cost of correction

Nominal Delay Delay (+k)

Cycle Time Selling point delay

Die Area Total cost of OPC

Gate Sizing Problem:

Given allowed areas and corresponding delays of each cell,

minimize total die area subject to a cycle time constraint

costs of correctioncosts of correction delay (delay (+k+k))

cost of OPCcost of OPC selling point delayselling point delay

MinCorr


• Mapping of area minimization to RET cost optimization• “Yield library” analogous to timing libraries (e.g., .lib)• Synthesis tool (Design Compiler) performs “gate

sizing”– Figure counts, critical dimension (CD) variations derived

from Numerical Technologies OPC tool*– Restricted TSMC 0.13 m library (7 cell masters: BUF, INV,

NAND, NOR)– Approach tested on small combinational circuits

• alu128: 8064 cells• c7552: 2081 cell ISCAS85 circuit• c6288: 2769 cell ISCAS85 circuit

• Up to 79% reduction in figure complexity without any parametric yield impact

MinCorr Methodology (DAC-03)


OPC and Designer’s Intent• OPC applied post-tapeout

– Overcorrection (matching corners) mask cost

– Large runtimes – Impact of OPC on performance unknown

• Designer’s intent: OPC quality metrics– CD (Poly over active)

• Non-critical poly need not be well-controlled

– Contact Coverage• “Perfect” corners unnecessary if there is enough contact overlap


• Historical rule on line end extension

• OPC software assumes the layout is the target, and adds OPC to the old OPC extension

• With model-based OPC, design rules can be much more aggressive

Example Caution: OPCing OPC

Truly desired on wafer Layout according to design rule

OPC on the OPC

Figures courtesy F. Schellenberg, Mentor Graphics Corp.


CD Error Distribution

•Library based correction shows highly accurate average CD


Systematic ACLV• ACLV = Through-pitch variation (50%) + Topography

variation (10%) + Mask variation + Etch, residuals• Current timing analysis (statistical or deterministic STA)

assumes all variation is ‘random’• 50% of ACLV can be predictable by analyzing the layout

“Smile-frown” plots indicate:

1. Through focus variation is systematic

2. Corners for timing analysis are derived from worst-case ACLV tolerance instance specific tolerances are much tighter

Figure courtesy ASML MaskTools


Taming Pattern and Focus Variation

1. Obtain a set of nominal CD (wafer image simulation) for typical environments of the cell in a chip environment specific timing libs (typical ASIC libs very limited set of environments)

2. Run in-context STA (post-placement) with context-specific timing libs accurate nominal timing at zero focus condition

3. Input to output delay modeling based on the iso-ness and dense-ness of transistors in the input to output paths more accurate delay variation analysis in STA

Work done at IBM


Taming..: Timing Results

Testcase

Traditional Timing New “Accurate” Timing

NOM BC WC NOM BC WC

C1355

C2670

C3540

C432

C499

2.15

5.07

6.32

5.77

2.30

1.57

3.74

4.72

4.21

1.66

2.88

6.64

8.34

7.70

3.10

2.15

5.05

6.26

5.70

2.29

1.70

4.04

5.20

4.53

1.79

2.62

5.96

7.35

6.88

2.82

Work done at IBM


Outline


– RDR’s, robust optimization, leakage


Acknowledgements

• The Library-Based OPC and Systematic ACLV based STA work is still unpublished and was done at IBM during Puneet Gupta’s summer internship. We would like to thank Fook-Luen Heng, Daniel Ostapko, Mark Lavin, Ronald Gordon, Kafai Lai and all our collaborators in the work.

• Dennis Sylvester and Jie Yang at University of Michigan were our collaborators for the MinCorr and variability-impact projection work. Yu Chen (Ubitech) was the coauthor for our work on PIL-Fill.

• We would also like to thank Frank Schellenberg (Mentor Graphics Corp.), Tim Yao Wong (CMU) and Dennis Sylvester for letting us use parts of their previous talks.


Notes on Regular Layout• 65 nm has high likelihood for layouts to look like

regular gratings– Uniform pitch and width on metal as well as poly layers Predictable layouts even in presence of focus and dose

variations

• More manufacturable cell libraries with regular structures

• New layout challenges (e.g., preserving regularity in placement)


Regular Layouts• Standard cells

– high performance, high density, low part cost, low power – escalating NRE, TAT, variability

• Programmable devices (FPGA)– regular, predictable, fast TAT, low NRE– low performance, low density, high part cost, high power

• Middle ground: e.g. via programmability (eASIC, CMU)– VPGA – retain regularity, but remove field programmability– Use only a few via masks to configure a circuit

* Courtesy Center for Silicon System Implementation, CMU.


Via Patterning

* Courtesy Center for Silicon System Implementation, CMU.

Connection made

Connection not made

Sample synthesis Results

1.46116875DLX (CLB Array)

1.4429216DLX (VPGA-Lib)

1.5055476DLX (ASIC)

0.80818225ALU (CLB Array)

0.8027800ALU (VPGA-Lib)

0.9505600ALU (ASIC)

Delay(ns)Area (μm2)Design


Stochastic/Robust Optimizations

• Physical design is no longer deterministic

• An example “probabilistic” LP:

• Problem: Too slow and not at all scalable


Example: Robustness Metric for Power Distribution

• Power distribution analysis by solving GV=I– G = Conductance matrix of the power distribution

network– I = Current requirements for sinks– V = IR drop (if Vdd is put to 0)– ||V|| = Peak IR drop (l-1 norm)

• Random variations– G : E.g., width and thickness variation– I : E.g., inaccurate estimation of peak currents


Example: Robustness Metric for Power Distribution (2)

• Perturbation analysis:

– E = random perturbation in G– e = random perturbation in I– V’ = IR drop map after perturbation

• ||G||||G-1|| = condition number = measure of robustness


Leakage: Understanding + Control

• Understanding: variation in chip-level leakage due to intra- and inter-die Leff variation cost-benefit of controlling

relevant variation sources

• Control: Multi-everything (threshold, supply, sizing)


Multi-Lgate Design for Leakage?

• Lgate biasing from 130nm to 140nm

• Leakage benefit = 29%

• Delay overhead = 5% ; Dynamic power overhead = 3.5%

• Potential alternative/supplement to multi-Vt design

• Avoid high variability in low Vt and manufacturing overheads of multi-Vt

• CD variability (as a %) is less for larger Lgate design

Delay

0.00E+00

1.00E-11

2.00E-11

3.00E-11

4.00E-11

5.00E-11

6.00E-11

7.00E-11

8.00E-110

.1

0.1

0.1

1

0.1

1

0.1

1

0.1

2

0.1

2

0.1

2

0.1

2

0.1

3

0.1

3

0.1

3

0.1

4

0.1

4

0.1

4

0.1

5

0.1

5

Lgate

Leakage

0.00E+00

2.00E-08

4.00E-08

6.00E-08

8.00E-08

1.00E-07

1.20E-07

1.40E-07

1.60E-07

1.80E-07

0.1

0.1

0.1

1

0.1

1

0.1

1

0.1

2

0.1

2

0.1

2

0.1

2

0.1

3

0.1

3

0.1

3

0.1

4

0.1

4

0.1

4

0.1

5

0.1

5

Lgate


Conclusions• Designer, physical design, and mask communities must maintain cost (value) trajectory of Moore’s Law

– Wakeup call: Intel 157nm announcement

• Bidirectional design-mfg data pipe driven by cost, value– Pass functional intent to mask and foundry flows– Pass limits of mask and foundry flows up to design

• Examples– Manufacturability and cost/value optimization– Exploitation of systematic variations (e.g., iso-dense)– Composability– Performance impact-limited dummy fill– Intelligent mask data prep, restricted design rules, etc.

• Manufacturing-aware PD: much work lies ahead


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ICCAD 2003 Manufacturing-Aware Physical Design Andrew B. Kahng Puneet Gupta (Univ. of Calif. San...

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