ICECS 2010ICECS 2010

I. Kouretas and V. Paliouras

Electrical and Computer Engineering Dept.,

University of Patras, GREECE

RNS multi-voltage low-power multiply-add unit

The 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece

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Outline

Review of RNS basics Architecture of RNS-based systems

Multi-Vdd RNS architecture Structure of processing units

Relevance to RNS Results Conclusions

Low-power through alternative number representations Sign-magnitude versus two’s-complement

Depends on data (signal) statistics Logarithmic number system

Choice of representation parameters V. Paliouras, T. Stouraitis, “Low-power properties of logarithmic number

system,” IEEE Symposium on Computer Arithmetic, 2001.

Residue representations Numerical properties of RNS Inherently parallel structureT. Stouraitis, V. Paliouras, “Considering the alternatives in low power design,” IEEE Circuits and Devices, 2001.

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RNS basics RNS maps an integer X to a N-tuple of residues xi.

xi =X mod mi and xi is called the i-th residue.

mi is a member of a set of pair-wise co-prime integers

called base. mi is called modulo. Dynamic range: 1

.N

iim

1 2, ,...,RNSNX x x x

1 2, ,..., Nm m m

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RNS architecture vs binary architectureoperands

operands

results

results

Data is processed in L parallel independent channels

Benefit: ni << n

binaryprocessor

n bits n bits

n bitsbin to RNS

RNS to bin

mod mprocessor

1

n bits2

n bits1

n bitsi

n bitsmod mprocessor

2

mod mprocessor

L

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Remarks on RNS architecture

operands results

The conversion issue

Forward and inverse

Implementation of moduli channels is not identical

There are fast channels and slow channels

n bitsbin to RNS

RNS to bin

mod mprocessor

1

n bits2

n bits1

n bitsi

n bitsmod mprocessor

2

mod mprocessor

L

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RNS advantages / disadvantages Advantages

Parallel multiplication or addition Fault tolerance Reduced power dissipation in filters

Disadvantages Difficult comparisons

Overflow detection Sign detection

Division Scaling / Rounding / Truncation

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RNS multi-VDD architecture

operands results

p is the number of moduli channels

Power is quadratically related to voltage

Distiguished moduli channels with Vdd(H) and Vdd(L)

Benefit: Easy to implement

2dyn ,

1i

p

L dd i i ii

P C V f a

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Employed RNS base

Base used in this study:

Cases of common choices in the literature

31 22 ,2 1,2 1 , 2 ,2 1,2 1,..., 2 1nn nn n n n

7 7 5 4 62 ,2 1,2 1,2 1,2 1 30-bits dynamic range

Employed RNS architecture

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Architectures of multiply adders

modulo- 2 1n modulo- 2 1n modulo-2n binary

Multi-voltage areas

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Synthesis tool

Synopsys dc_shell –topographical mode

Universal Power Format (UPF) mode is used

Net complexity is included

Level shifters complexity is icluded

Vdd(H)=1.2V

Vdd)L)=1.0V

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Configuration script

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set domain TOPset primary_power {TOP} HIGH_VDD 1.2 set level_shifter_strategy{TOP} fir_rns5_ls_strategy1set level_shifter{fir_rns5_ls_strategy1} - - selflappend domain LOWset elements {LOW} channel_modulo_2nm1/mac1 channel_modulo_2nm1/mac2 channel_modulo_2np1 channel_modulo_2n flip1 flip2 flip3 flip4 flip5 flip6set primary_power {LOW} LOW_VDD 1.0 lappend domain HIGHset elements {HIGH} channel_modulo_2nm1/mac3 f_convp1X f_convp1A f_convm1X31 f_convm1A31 f_convm1X63 f_convm1A63 f_convm1X127 back_converter f_convm1A127 set primary_power {HIGH} HIGH_VDD 1.2 set create_pst true

Synopsys UPF generator tool

UPF map

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Synthesis result

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Results

Area (μm2) Delay(ns) Power(mw)

Binary (Vdd(H)) 4286 8.7 6.507

RNS (Vdd(H)) 8708 5.5 7.253

Multi-Vdd RNS 9864 5.5 5.635

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20.5% and 17.8% power savings

Conclusions

Multi-Vdd low power technique is suitable for RNS systems.

Application of multi-Vdd further reduces power dissipation in RNS systems.

High and low Vdd channels can be easily determined.

Further investigation on multi-Vdd RNS systems is required

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The End

Thank you for your attention!