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ICT (In Circuit Test)

"#

z !"#$%&'()*+,'(-./&0123&45"#$6

z 789:'(;!

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ICT"#$% Agilent 3070

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ICT"#$% GenRad 228x

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ICT"#$% Teradyne

Spectrum

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PCB

ICT TESTER

ICT&'()*

Fixture

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ICT+,-./01FT2

*F&G$HI

*JKLM

*F&NO

*PQRSTU

*:VW0XYZPQ&[)*

--\]^_

--\]`a

--bc?deR]fOg&:h

--ijk+Ll

--mnopqr

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34ICT+5567

*'(stu6

*vRZ

*'(wx6

*PQRS

*yz{|

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Agilent ICT Tester

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Agilent 307x Series 3 Architecture

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Testhead Layout

BRC:Bank,Row,Column :20378,203178

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Configuring a Four-Module System

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Cards

HybridPlusHybridPlus Pin CardPin Card

Double Density HybridDouble Density Hybrid

ChannelPlusChannelPlus Pin CardPin Card

AccessPlusAccessPlus Pin cardPin cardAnalog Pin CardAnalog Pin Card

Double Density Analog Pin CardDouble Density Analog Pin Card

Serial Test Pin CardSerial Test Pin Card

ASRUASRU -- Rev A,B or CRev A,B or C

ControlControl

ControlPlusControlPlus

ControlXTControlXT

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System config file

PATH:/hp3070/diagnostic/th1/config

testhead name "testhead1"line frequency 50

relay 1 controls vacuum 2,3relay 2 controls vacuum 0,1

bank 1module 0

cards 1 asrucards 2 hybrid advanced ! double densitycards 3 hybrid advanced ! double densitycards 4 hybrid advanced ! double densitycards 5 hybrid advanced ! double density

cards 6 control pluscards 7 hybrid advanced ! double densitycards 8 hybrid advanced ! double densitycards 9 hybrid advanced ! double densitycards 10 hybrid advanced ! double densitycards 11 hybrid advanced ! double densitysupplies hp6624 13 to 16 ! asru channels 1 to 4ports ext7, ext8

end module

module 1.End module

end bankbank 2

end bank

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Board level config filemodule 2

cards 1 asru c revisioncards 2 hybrid standard double densitycards 3 hybrid standard double density

cards 4 hybrid standard double densitycards 5 hybrid standard double densitycards 6 control pluscards 7 hybrid standard double density

!@ cards 8 hybrid standard double density!@ cards 9 hybrid standard double density!@ cards 10 hybrid standard double density!@ cards 11 hybrid standard double densitysupplies 5 to 8

end module

module 3cards 1 asru c revision

!@ cards 2 hybrid standard double density!@ cards 3 hybrid standard double density!@ cards 4 hybrid standard double density!@ cards 5 hybrid standard double density

cards 6 control pluscards 7 hybrid standard double densitycards 8 hybrid standard double density

cards 9 hybrid standard double densitycards 10 hybrid standard double densitycards 11 hybrid standard double densitysupplies 1 to 4

end module

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Short Wire Fixture Architecture

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Command control testhead

Testhead power on

fix lock, fix unlock-----compressed air

faon,faoff ------Vacuum

vacuum well is

faon fbon

Vacuum well a is 2,3 Vacuum wellb is 0,1

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GenRad 2287 tester

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GenRad H ardwar e OverviewGenRad H ardwar e Overview

FixtureFixture

GenRad RECEIVERGenRad RECEIVER

PIN

CARD

PIN

CARD

REFERENCE

REFERENCE

C/S/T

C/S/T

RST

RST

ICA

ICA

Windows NTWindows NT

MXI Bus

UUT PS

IEE-488

MTG

MTG

AFTMC

ARD

AFTMC

ARD

PIN

CARD

PIN

CARD

PIN

CARD

PIN

CARD

PIN

CARD

PIN

CARD

DSM

BOARD

DSM

BOARD

0 1 3 3 4 5 6 31 32 33 34

PIN BAY

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MTG

RTC

CST

AFTM

Reference

ICA

DSM

MXI to GenRad boardFunctional blocks are MXI to GR businterface

Run Time ControllerBus interface for the analog subsystem directs & coordinaes pin

board activities; data transfers between cpu and the digitalsubsystem

Clock/synchronus/trigger board

Privides event timing and event detection

Driver/Sensor referenceSupplies programmed dc reference voltages for the D/S pin

boards

DDeep Serial Memory

Analog Functional Test Module

In-Circuit Analog Module

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Solectron Confi dential

GenRad228x Series

Architecture

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TESTPLANTESTPLAN

call Pre_shorts

call Shorts

.

Call Analog_tests

Call testjet

Call digital

Sub Characterize

learn capacitance on

learn capacitance off

subend

Sub Pre_Shorts

Subend

Sub Shorts

Test !shorts"

Subend

Sub Analog_Tests

Test !analog/c4"

Test !analog/r56"

subend

Sub Digital_Tests

Test !digital/u1"

Test !digital/u2"

subend

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Typical Example ofTypical Example of Analog TestAnalog Test

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disconnect all

connect s to !N1"connect I to !N2"

connect g to !N100"

resistor 10k, 5.5,5,re5,ar0.1

Resistor typical test program:Resistor typical test program:

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1.1. S busS bus

2. I bus2. I bus3. G bus3. G bus

4. A bus4. A bus

5. B bus5. B bus6. L bus6. L bus

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enhancement

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ZZcc=1/2=1/2ffcc C=1/2C=1/2 ffZZcc

Capacitor test:Capacitor test: Inductor test:Inductor test:

ZZLL =2=2ffLL

Capacitor Test

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!!!! 2 0 1 1002945327 0000! IPG: rev B.03.42 Sat Oct 13 11:55:28 2001! Common Lead Resistance 100m, Common Lead Inductance 1.00u! Fixture: EXPRESSon failure

report parallel devicesreport "r1 15.0k"

end on failuredisconnect allconnect s to "GND"; a to "GND"connect i to "TREE__1022"connect g to "+5"capacitor 100n, 13.4, 8.66, fr1024, re3, wb, ar100m, sa, en,nocompoff failure

Capacitor test file

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Diode & Zener Test

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!!!! 2 0 1 885232159 0000! IPG: rev B.02.54 Mon Jan 19 09:49:20 1998! Common Lead Resistance 500m, Common Lead Inductance1.00u! Fixture: EXPRESSdisconnect allconnect s to "VCC"connect i to "$34"diode 728m, 413m, idc5.0m, co3.0, ar828m

Diode Test File

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FET Test Configuration

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!!!! 2 0 1 924217662 0000! IPG: rev B.03.13 Wed Mar 31 11:25:15 1999! Common Lead Resistance 500m, Common Lead Inductance 1.00u! Fixture: EXPRESSon failure

report parallel devices

report "q23 q23:fet 100, 20.0"end on failuredisconnect allconnect s to "TREE89"connect i to "B0"connect g to "VF"nfetr 81.6, 10.0, re1, ar50.0m

FET Test File

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Test OptionsTest Options

am ! amplitude sa !use the A bus to sense the S bus

ar !ASRU range sb !use the B bus to sense the I bus

idc !DC current sl !use the L bus to sense the G bus

comp ---- capacitor compensation en ! enhancement

nocomp----No compensation ed ! extra digit

fr ! frequency co !voltage compliance

re ! reference element ico ! current compliance

wa !wait wb !wideband

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TESTPLANTESTPLAN

call Pre_shorts

call Shorts.

Call Analog_tests

Call testjet

Call digital

Sub Characterize

learn capacitance on

learn capacitance off

subend

Sub Pre_Shorts

Subend

Sub ShortsTest !shorts"

Subend

Sub Analog_Tests

Test !analog/c4"

Test !analog/r56"

subend

Sub Digital_Tests

Test !digital/u1"

Test !digital/u2"

subend

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The parts of a Digital TestThe parts of a Digital Test

! Declaration Section

! Device Type

! assignment section! Timing Section

Details are covered

in Advanced Digital

Class! Vector Definition Section

Vector Initial_State

set Reset to !0"

set CS_bar to !0"

...! Vector Execution section

unit !Test Reset"execute Initial_State

execute Assert_reset

.

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1

2

4

5

9

10

12

13

3

6

8

11

NAND GATE

Input 1 Input2 Output

E1 0 0 1

E1 0 1 1

E1 1 0 1

E1 1 1 0

Truth Table

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Digital libraryDigital library (Declaration Section)! 7400! NAND, 2-Input, Quad! revision A.01.00

combinatorialvector cycle 500nreceive delay 400nassign VCC to pins 14assign GND to pins 7

assign E1_Inputs to pins 1,2assign E2_Inputs to pins 4,5

assign E3_Inputs to pins 9,10assign E4_Inputs to pins 12,13

assign E1_Output to pins 3assign E2_Output to pins 6assign E3_Output to pins 8assign E4_Output to pins 11

power VCC, GND

family TTL

inputs E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputsoutputs E1_Output,E2_Output,E3_Output,E4_Output

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Digital library testDigital library test ((Vector Definition Section)

vector E1_Input_00set E1_Inputs to "00"

set E1_Output to "1"end vector

vector E1_Input_01set E1_Inputs to "01"set E1_Output to "1"

end vector

vector E1_Input_10

set E1_Inputs to "10"set E1_Output to "1"

end vector

vector E1_Input_11set E1_Inputs to "11"set E1_Output to "0"

end vector

vector E4_Input_00set E4_Inputs to "00"set E4_Output to "1"

end vector

vector E4_Input_01set E4_Inputs to "01"set E4_Output to "1"

end vector

vector E4_Input_10

set E4_Inputs to "10"set E4_Output to "1"end vector

vector E4_Input_11set E4_Inputs to "11"set E4_Output to "0"

end vector

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"0# set a logic low on the node.

"1# set a logic high on the node.

"K# keep the previous state.

"T# toggle from the previous state.

"Z# set the device to a high impedance state.

"X# don%t care this receiver.

i i i

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Digital libraryDigital library ((unit section)unit "Element number 1"

execute E1_Input_11execute E1_Input_01execute E1_Input_00

execute E1_Input_10end unit

unit "Element number 2"execute E2_Input_11execute E2_Input_01execute E2_Input_00execute E2_Input_10

end unit

unit "Element number 3"execute E3_Input_11execute E3_Input_01execute E3_Input_00execute E3_Input_10

end unit

unit "Element number 4"execute E4_Input_11execute E4_Input_01execute E4_Input_00execute E4_Input_10

end unit

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Overdrive andOverdrive and BackdriveBackdrive

Vector E1_Input_11

set A to !1"

set B to !1"

set C to !0"

end vector

VCC

A

B

C

VCC

Back drive current

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standard_standard_cmoscmos safeguard filesafeguard file

PATH:/hp3070/standard/safeguard/standard_cmos

!!!! 8 0 1 591688800 0000parameters "standard_cmos"

!! subfamily : standard CMOS!! characteristics : low level output current

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Library level Safeguard FileLibrary level Safeguard File

! Standard Safeguard Template

include "standard_cmos"

use parameters "standard_cmos" for "TL7702AH_1"use parameters "standard_cmos" for "28SCID0490CH_1"use parameters "standard_cmos" for "74ABT244H_3"use parameters "standard_cmos" for "74F08H_1"

use parameters "standard_cmos" for "S02F"use parameters "standard_cmos" for "358H_2"use parameters "standard_cmos" for "74F112H_2"use parameters "standard_cmos" for "74F175H_1"use parameters "standard_cmos" for "74F74H_2"use parameters "standard_cmos" for "74F163H_1"use parameters "standard_cmos" for "74F32H_1"use parameters "standard_cmos" for "10H125P_3"

use parameters "standard_cmos" for "74F38H_1"

S f i

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Board level Safeguard FileBoard level Safeguard File

parameters "standard_cmos"backdrive current of 5m for "0", 50m for "1"bond wire 2540 by 25.4heat source 100 by 10, 1 per outputoperating temperature 40overdrive power 20m, 20m dissipated by heat source

package ceramicthermal resistance 60

end parameters

use parameters "standard_cmos" for "u1"use parameters "standard_cmos" for "u2"use parameters "standard_cmos" for "u3"use parameters "standard_cmos" for "u4"use parameters "standard_cmos" for "u5"use parameters "standard_cmos" for "u6"use parameters "standard_cmos" for "u8"

use parameters "standard_cmos" for "u9"use parameters "standard_cmos" for "u10"use parameters "standard_cmos" for "u11"use parameters "standard_cmos" for "u12"

Di i l il f d h kDi it l il f d h k

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Digital compiler safeguard checkDigital compiler safeguard check

Digital/u15--------------------------------------------------------------

C O M P I L A T I O N S U M M A R Y-------------------------------------

31 vectors executed19 vector Ram slots used ,0% full32 sequence ram slots used,0% full13 directory ram slots used, 0% full

S A F E G U A R D S U M M A R Y--------------------------------safeguard status :Not InhibitedEstimated test time:3.60e-05Safe Test time(device):5.99e-01(u16)

201 lines,0 errers,0 warnings,object produced

The Setup Power Supplies RoutineThe Setup Power Supplies Routine

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The Setup_Power_Supplies RoutineThe Setup_Power_Supplies Routinesub Setup_Power_Supplies

global Pslimit

cps

sps 1,5.00,0.50;optimize |rps 1 ,V,I|print V,I

sps 2,5.00,2.00;optimizePslimit = pslimit

pass device

if Pslimit then

dps

fail device

I=1

for Pscount=1 to 2

if binand(Pslimit,I) then

report !Power Supply Number"report Pscount

report !In Current Limit"

end if

I=2*I

next Pscount

report !------------------------------------"

report !Check for backwards"

report !IC#s or Capacitors."

report !------------------------------------"end if

subend

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Disable issueDisable issue

cs

UUT2

U2

Upsteam

device

U21

UUT1

U1

output

Input

i i i i i

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Disable description in libraryDisable description in library

! QMV288 U21 Library! setup only

! revision A.01.00

vector cycle 500nreceive delay 400n

assign VCC to pins 1,2,3,4,5assign GND to pins 25,26,27,29,30

assign IO to pins 5,6,7,8,9,10,11,12,13,14,15,16assign IO to pins 17,18,19,20,21,22,23,24assign CS to pins 28

family TTLpower VCC,GND

inputs CSbidirectional IO

disable IO with CS to "0"

Di bl iDi bl i t t t

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Disable in execute testDisable in execute test

!U2 executable testassign Disablegroup to nodes "TREE__1343! default "0"

inputs Disablegroup

assign DisableFamilyTTL to nodes "TREE__1343"

family TTL on DisableFamilyTTLinputs DisableFamilyTTL

!IPG: Safeguard will ignore disabled outputsdisabled device "u21" pins 5,6,7,8,9,10,11,12disabled device "u21" pins 13,14,15,16,17,18,19disabled device "u21" pins 20,21,22,23,24!IPG: with pin 28 on node "TREE__1343"

The node TREE__1343(U21 Pin CS) keep at low level during U2 Test

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Analog Functional Resource

s :Source

a:auxiliary source

i: detector high

l: detector low

rcva,rcvb,rcvc:frequency detector

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Resource specification

Source range unit

------------------------------------------------------------

DCV -10 - +10 Vdc

SINE 0 - 7.0 Vrms

SQUARE 0 - 10 Vpk

TRIANGLE 0 - 10 Vpk

Auxiliary source : -10 - +10 Vdc

Frequency detector: 1 - 60 MHz

A l F ti T t Fil

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!IPG: rev B.03.42 Sat Oct 13 11:56:05 2001! Quad TTL-ECL Translator

test powered analogpower pins "8", "9","16"nonanalog pins 6connect l to groundtest "TRANSLATOR1_4"test "TRANSLATOR1_2"

end test!-----------------------------------------------------------------------

subtest "TRANSLATOR1_4"connect s to pins 5connect i to pins 4source dcv, amplitude 2.5, icompliance 1, ondetector dcv, expect -2

measure -1.6,-2wait 50msource dcv, amplitude 0.3,icompliance 1, ondetector dcv, expect -1

measure -0.7,-1

end subtest

subtest "TRANSLATOR1_2"......end subtest

Analog Function Test File

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test powered analogpower pins 7,14nonanalog pins 1test "OUTPUT"

end test

subtest"OUTPUT"

connect rcvc to pins 8detector frequency, expect 49.152M

measure 49.152M * 1.0005,49.152M * 0.9995

end subtest

Frequency Test

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HowHowTestjetTestjet do?do?

Devices HP TestJet HP Connect Check

devices with an internal lead frame

(most digital and hybrid devices) X

devices with an internal ground plane

(usually ceramic packages) X

most Ball Grid Arrays (BGAs)(except ceramic and stadium packages) X

some Ball Grid Arrays (CBGAs)

(ceramic and stadium packages only) X

connectors and sockets X

devices with grounded heat sink X

flip chip devices or chip-on-board (COB) X

dip switches X

pushbuttons X

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HP TestJet Architecture

Remark:The S (source) bus to the pin being tested,the I (input) bus to the HP TestJet probe,and the

G(guard) bus to all other pins on the device.

HP TestJet is an unpowered test of the connectivity from each pin on a

device to the circuit board. The system uses the HP TestJet hardware to

measure the capacitance from a pin of a device to the HP TestJet probe.

The measurement is repeated for each pin on the device, except power and

ground pins. Pins that are tied together are tested as one pin.

The "testjet" File

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jThe "testjet" file is the test file for all devices to be tested with HP TestJet; this

one test file includes the tests for all HP TestJet devices.

default threshold low 200 high 10000default throughput adjustment 1!throughput adjustment 0

device "u101";threshold low100 high 10000test pins 1test pins 2,3test pins 4,5,6! test pins 7 ! Ground pins commented by HP IPG.test pins 8test pins 11;threshold low 20 high 10000test pins 12test pins 13! test pins 14 ! Fixed pins commented by HP IPG.

inaccessible pins 9,10end device

The "default threshold" statement sets the test thresholds for all the devices in the file.

The "default throughput adjustment" statement enables or disables throughput

adjustment for all the devices in the file.

There is a "device/end device" block for each device to be tested. The "device" statement

specifies the device designator. If the device is mounted on the bottom side of the board,

the "device# statement includes the "bottom" keyword.

The "test pins" statement specifies the pin or pins to be tested. Pins that are tied together inthe circuit are specified and are tested together.

The "inaccessible pins" statement declares pins that are not tested because they are not

accessible.This statement always appears at the end of the device block.

T tj t P b A bl

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Testjet Probe Assemble

T tj t P b A bl

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Testjet Probe Assemble

HP TestJet Probe and Mux Card Connections.

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Pin Numbers for the RightPin Numbers for the Right--Angle ConnectorAngle Connector..

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Mux Card Jumpers J4 and J5.

An Example of HP TestJet Wiring in the Top Side of the Fixture.

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TESTPLANTESTPLAN

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call Pre_shorts

call Shorts.

Call Analog_tests

Call testjet

Call digital

Sub Characterize

learn capacitance on

learn capacitance off

subend

Sub Pre_Shorts

Subend

Sub Shortstest !shorts"

Subend

Sub Analog_Tests

Test !analog/c4"

Test !analog/r56"

subend

Sub Digital_Tests

Test !digital/u1"

Test !digital/u2"

subend

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A Short is an impedance, between two nodes, that is less than or equal

to the threshold impedance.

An Open is an impedance, between two nodes, that is greater than the

threshold impedance.

A Shorts Test is testing for unexpected shorts on the board; it requires the

impedance between nodes to be greater than the threshold (open) to give aPASS indication.

An Opens Test is testing for unexpected opens on the board; it requires

impedance between nodes to be less than or equal to the threshold (short)

to give a PASS indication.

Shorts Test fileShorts Test file

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!!!! 9 0 1 974538053 0000!IPG: rev B.03.42 Sat Nov 18 17:00:54 2000threshold 8settling delay 50.00ushort "#:N6" to "#:N90"short "#:2V5" to "#:N142"short "#:N9" to "#:2V5"short "#:3V3" to "#:N4"!short "#:N213" to "#:N7" ! A node is not accessible!short "#:-48V" to "#:N212" ! A node is not accessiblereport phantomsthreshold 1000

nodes "#:-48V"nodes "#:N7"nodes "#:N213"nodes "#:N254"nodes "#:N143"!nodes "#:N146" ! Node not accessiblesettling delay 3.740mnodes "#:5V"settling delay 50.00unodes "#:N10"

!nodes "#:N11" ! Node not accessiblenodes "#:N13"

Shorts Test fileShorts Test file

Open test

Shorts test

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Open test

short "A# to "D#

A

B

C

D

source

detector

S

D

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Shorts test

Detection:Detection selects the first node in the "shorts" file to

connect to a source; it connects all the following nodes in

the shorts list to a detector.

Isolation:If detection find shorts the isolation is invoked to find

the exact shorted nodes by a process of bisection .

Isolate a short

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1.Check node A

2.Check node B

find short

3.isolation

4.find A short to D

Phantom shorts

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Phantom short :detection find short but isolation can%t find

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report netlist

report netlist, common devices

report common devices

report common devices, netlistreport phantoms

report limit

Shorts test report options

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ICT Fixture Software Develop Process

FABMASTER

GC-PLACE

HP3070SOFTWARE

GENRADSOFTWARE

Fixture File &

Test program

TAKAYATest program

CAD File

Gerber File

Collect Material Cad Translate Generate Test Program Debug

S O OC SS

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TEST DEVELOPMENT PROCESSTEST DEVELOPMENT PROCESS

First :First : Gather the materialsGather the materials

((SchemSchem.,BOM,CAD,Datasheet,loaded board).,BOM,CAD,Datasheet,loaded board)

Second:Second: Describe the board to the HP 3070.(Describe the board to the HP 3070.(FabmasterFabmaster,board,board

consultant)consultant)

Third :Third : Let the HP 3070 generate tests and fixture files(Let the HP 3070 generate tests and fixture files(IPG).IPG).

ThirdThird##:: Evaluate the files the HP 3070 generated.Is theEvaluate the files the HP 3070 generated.Is the testtest

sufficient? Are there details omittesufficient? Are there details omitted? Should changesd? Should changesbe made and the Test Generation procbe made and the Test Generation process be reess be re--run?run?

Fourth:Fourth: Build a fixtureBuild a fixture

Fifth :Fifth : Turn on each test.Are there tests that require deTurn on each test.Are there tests that require debug? Ifbug? If

so,debug those tests.so,debug those tests.

Sixth :Sixth : Release test to production.Release test to production.

Seventh:Seventh: Perform an ECO(Engineering Change Order)as needed.Perform an ECO(Engineering Change Order)as needed.

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GatheringGatheringMaterialsMaterials

The MaterialsThe Materials

Schematic DiagramSchematic Diagram

CAD Data(contain xCAD Data(contain x--y information,y information,netlistnetlist))

BOMBOM

Part DatasheetPart Datasheet

Blank PC boardBlank PC board

Loaded PC board(known good)Loaded PC board(known good)

knowledge of Board Test Considerationknowledge of Board Test Consideration

Describing the PC board to the SystemDescribing the PC board to the System

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g yg y

What does the HP 3070 software need and whatWhat does the HP 3070 software need and what

tools are avai lable?tools are avai lable?The software needs a description of theThe software needs a description of the testheadtesthead hardware.hardware.

For the HP 3070 software to accompl ish this, i t needs a clear,conFor the HP 3070 software to accompl ish this, i t needs a clear, concisecisepicture of the PC board.This i ncludes the physi cal characteri stipicture of the PC board.This includes the physical characteri sti cs ofcs ofthe board,the locations of the components on the board,the locatthe board,the locations of the components on the board,the locations ofions ofviasvias andand testpadstestpads.I t al so needs the value of the analog parts on the.I t also needs the value of the analog parts on theboard and the tolerance of each device.The generi c part number oboard and the tolerance of each device.The generi c part number of thef the

digi tal devices on the board i s also needed.Given this i nformatidigi tal devices on the board is also needed.Given this i nformati on,theon,theHP 3070 wi l l create tests for the analog devices and use l ibrariHP 3070 wi l l create tests for the analog devices and use librari es ofes oftests for the digi tal devices.tests for the digi tal devices.

For theFor the testheadtesthead configuration,you wi l l use BTconfiguration,you wi l l use BT--BASIC edi tor to createBASIC editor to createthethe !!configconfig""fi le.This describes thefi le.This descri bes the testheadtesthead hardware to be used whenhardware to be used when

creating the fixture and test fi les for this board.creating the fixture and test fi les for thi s board.

HP Board Consul tantHP Board Consul tant

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even i f a complete descri ption of the PC board is avail able fromeven i f a complete description of the PC board is avai lable fromCADdata,youCADdata,yousti l l need to use HP Board Consul tant to descri be detai ls aboutsti l l need to use HP Board Consul tant to descri be detai l s about the test thatthe test thatCADdata was never intended to i ncl ude.CADdata was never i ntended to i ncl ude.

Board Description ColumnBoard Description Column

i di h i l d

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View/Edi t Physical Board DataView/Edi t Physical Board DataBoard Outl ineBoard Outl ine

Board Tooling HolesBoard Tooling Holes

View/Edi t Board Description entries.View/Edi t Board Description entries.View/Edi t Test SystemDataView/Edi t Test SystemData

Entering a Power NodeEntering a Power Node

Entering a Fixed NodeEntering a Fixed Node

Enteri ng Board Level Di sable/Condi tionsEntering Board Level Disable/Conditions

Enteri ng the Integrated ProgramGenerator Global OptionsEnteri ng the Integrated ProgramGenerator Global Options

Fami ly OptionsFami ly Options

The Fixture OptionsThe Fixture Options

Enter General Purpose RelaysEnter General Purpose RelaysTheThe KeepoutKeepout AreaArea

Enter GroupsEnter Groups

Extra Probing Locati onsExtra Probing Locati ons

Test SystemData Compi le and Veri fyTest SystemData Compi le and Veri fyConfiguration Fi le Instructi onsConfiguration Fi le Instructi ons

Veri fy Fixture TypeVeri fy Fixture Type

Veri fy Configuration Si zeVeri fy Configuration Size

Veri fy Node ProbingVeri fy Node ProbingVeri fy Power ProbingVeri fy Power Probing

Veri fy Ground ProbingVeri fy Ground Probing

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A description of the probe location attributesA description of the probe location attributes

mandatoryThis forces the system software to locate the probe at the specified location.

preferredThis marks the specified location as the one you would like to see probed if there

are no other considerations that would prevent this location from being used.unreliableThis marks the location as one to use but only if no others are available.

no_accessThis flags the given location as being one that cannot be probed.

no_probeThis tells the software that the associated location is prohibited from being a valid

probe location.

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IPGIPG(Integrated ProgramGenerator)(Integrated ProgramGenerator)

InputsInputs OutputsOutputs

board.oboard.o

board_board_xyxy.o.o

l ibrary testsl i brary tests

Running IPGRunning IPG

pi ns fi l epi ns fi l e

analog di rectoryanalog di rectory

di gi tal di rectorydigi tal di rectory

functi onal di rectoryfuncti onal di rectory

mixed di rectorymi xed di rectory

testordertestorder fi lefi le

ipgipg/summary fi l e/summary fi le

ipgipg/detai ls fi l e/detai ls fi le

ipgipg/dependenci es.o/dependenci es.o

ConfigConfig.o.o

Final Compi le/Veri fy &Generate Testabi l i ty ReportFinal Compi le/Veri fy &Generate Testabi l i ty Report

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Save Fi lesSave Fi les

Compi le Fi lesCompi le Fi les

Generate aGenerate a !!testabi l i ty.rpttestabi l i ty.rpt""

The Testabi l i ty Report wi l l summarize al l theThe Testabi l i ty Report wi l l summarize al l theinformation presented so far,makeinformation presented so far,makecompari sons,veri fi cations,check for sourcecompari sons,veri fications,check for sourcefi les,etc.The end resul t wi l l be a summary offi les,etc.The end result wi l l be a summary ofwhat the systemfinds i s missing,incorrect or awhat the systemfinds i s missing,incorrect or apotential problemfor HP IPG Test Consul tant.potential problemfor HP IPG Test Consul tant.

Fixture Fi les StructureFixture Fi les Structure

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FixtureFixture

wires.pwi res.p

wi restopwi restop.p.p

wi reswi res

tracetrace

testjettestj et__muxmuxprobesyopprobesyop.p.p

summarysummary

probes.pprobes.p

insertsinserts

dri l l supdri l l sup

dril ldri l ldetai lsdetail s

dri l l topdri l l top

fixture.ofixture.o

Explanation of all fixture#s files

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details fileThe Details Report contains all the information provided by the Summary

Report with detailed explanations. When the Fixture Generation Software is

run in incremental mode (for ECOs) the Details Reports also contains

information about wiring that needs to be added or deleted from the existing

fixture.

drill fileThe drill files contain drill tool and X-Y coordinate information for the probe

plate . The information is in a common format for numerically controlled

machines.

drillsup fileDrilling information for the support plate.

drilltop fileDrilling information for the top probe plate.

fixture.o fileThe placement is specified in the fixture.o file, and includes the board outline

coordinates, tooling pin hole and locations, board placement specifications,

fixture part number, and fixture options.insert fileThe Fixture Inserts Report contains information for inserting pins, receptacles,

and probes.

Revolutionizing PCB

Testing

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g

WHY

Boundary Scan

PCB Testing is Challenging

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High Density

DeviceComplexity

SMDBGAMCM

Multi-Layer

Traditional In-Circuit Test mandates Test Point for every

net. Test inaccessibility is the major problem. Boundary Scan Test is the only solution.

Power of Boundary Scan Test

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!Engineers turn to technologies like boundary scanwhich don"t need physical access to perform designdebug, manufacturing and field test, as well as in-

system configuration for programmable devices.#

- Bode Enterprises, Inc. A market researchfirm

Boundary Scan Test eliminates TestProbes.

A Bo undary Scan

Device

IEEE 1149.1

Archi tecture

Benefit of Boundary Scan Test

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2664305999Crux

197102482Nimain

16341069932Lennon

Test points may be

reduced

BS ComponentsNetsTest Case

l Reduces test points on board.$ Minimizes board area.

$ Simplifies routing layout.

$ Preserves signal integrity for high speed

communication design.

$ Access complex IC such as BGA.

The Market

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The Market

0

5

10

15

1999 2000 2001 2002 2003

$Billions

The total U.S. demand for printed circuit boards,estimated at $9.194 billion in 1998, is projected to

increase at an annual average growth rate of 7.2% toreach $13 billion in 2003.Source: BUSINESS COMMUNICATIONS CO., INC.,

The Market Continue

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The Market -Continue

0

50

100

150

200

250

300

2001 2002 2003 2004

Boundary Scan Market Growth(%)

The boundary-scan market will grow at more than 40 percenteach year through 2004.Sour ce: Bode Enterpr ises, Inc., a Cali for nia market research f i rm.

Revolutionizing PCB

Testing

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HOW

Boundary Scan

Introduction to Boundary-ScanIEEE Standard 1149.1-1990

Backgro nd

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BackgroundCurrent in-circuit and functional testing techniques are becoming less effective because of node accessproblems and the inability of testers to cover all nodes. Conventional techniques are becoming less

efficient because test development requires longer time investments; time-to-market lengthens and test

costs increase.These problems were viewed with such a concern that, in 1985, several European companies formed a

group called JETAG (Joint European Test Action Group). Later several American companies joined this

group, which was renamed JTAG (Joint Test Action Group). JTAG conceived the boundary-scan technique

to address these problems; it was finally documented in the JTAG Rev 2.0 proposal in 1988.

A proposal to develop this technique was handed off to the Institute of Electrical and Electronics

Engineers (IEEE) and was refined by the IEEE working group. During 1989, IEEE P1149.1 went out to

ballot, and in early 1990 it became IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and

Boundary-Scan Architecture. The standard defines how to design testability features into digital devices,

which will simplify testing. These features can be used in device testing, incoming inspection, board test,

system test, and field maintenance and repair.

What is Boundary-Scan?

B d S i t t t h i th t i l d i d i d ith hift i t l d b t

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Boundary-Scan is a test technique that involves devices designed with shift registers placed between

each device pin and the internal logic as shown in Figure 1. Each shift register is called a cell. These cells

allow you to control and observe what happens at each input and output pin. When these cells are

connected together, they form a data register chain, called the Boundary Register.Boundary-Scan devices have a dedicated port, called the Test Access Port (TAP), that routes input

signals to a controller, called the TAP Controller.

Test Data In (TDI) the serial input for test data and instruction bits

Test Data Out (TDO) the serial output for test data

Test Clock (TCK) an independent clock used to drive the device

Test Mode Select (TMS)provides the logic levels needed to

change the TAP Controller from state to state

Test Reset (TRST*) an optional input signal used to reset the

device (the * indicates that this is an active-low input signal)

The Manufacturing Fault Spectrum and Boundary-ScanBoundary Scan addresses the fault spectrum by providing a variety of test options that focus on

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ScanBoundary-Scan addresses the fault spectrum by providing a variety of test options that focus oneach of the failures mentioned. For example, the mandatory EXTEST provides excellent fault coverage,

which addresses opens, shorts, missing or wrong components, and dead ICs. The optional RUNBIST

instruction checks the internal logic of a device and provides fault coverage for missing or wrongcomponents, dead ICs, and fixture problems. IDCODE checks for wrong devices mounted on the board.

Boundary-Scan In the Circuit (1)

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Boundary-Scan In the Circuit(2)

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(2)

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Boundary-Scan In the Circuit (3)

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Moving Through the TAP Controller StateDiagram

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