IDE ControllerIDE ControllerFeasibility ReviewFeasibility Review

Group MembersGroup Members Brian KuligBrian Kulig Graig PlumbGraig Plumb James PierpontJames Pierpont Saif ShaikhSaif Shaikh

AdvisorAdvisor Arun RamanathanArun Ramanathan

Development of an Ultra DMA Development of an Ultra DMA Module for a Hard Disk ControllerModule for a Hard Disk Controller

Specifications – IDE ATA5 StandardsSpecifications – IDE ATA5 Standards

RTL Description of PIO and Ultra DMA (Direct RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4)Modes 0 to 4)

Behavioral description of the Hard Disk Behavioral description of the Hard Disk InterfaceInterface

Functional and Timing Simulations using Functional and Timing Simulations using Cadence VerilogXLCadence VerilogXL

ArchitectureArchitecture

IDEFSM

IDEFSM

DMAMODULE

PIOMODULE

DMAMODULE

PIOMODULE

To Hard Disk

To Hard Disk

IDE CHANNEL 0

IDE CHANNEL 1

Fifo’s and Rest

of System

Fifo’s and Rest

of System

PIO ModePIO Mode

ResetClk Reset

Rw Cs0, Cs1Start Da0, Da1, Da2Add 4 IordyWdata 16 DiorRdata 16 DiowWdone Data 16Rdone

Piotimingmode 3Piotransfermide

PIOModule(RTL)

Hard Disk(Behavioral)

Programmed I/O Programmed I/O ConstraintsConstraints

Cycle Time(nanoseconds)

MaximumTransfer Rate

(MB/s)

DefiningStandard

Mode 0 600 3.3 ATA

Mode 1 383 5.2 ATA

Mode 2 240 8.3 ATA

Mode 3 180 11.1 ATA-2

Mode 4 120 16.7 ATA-2

PIO DesignPIO Design

5 Modes 0 - 4, used for control signals5 Modes 0 - 4, used for control signals Timer, begins on start pulseTimer, begins on start pulse

• Signals dependent on rw Signals dependent on rw Timer reset at specific timeTimer reset at specific time

• Example mode 0 resets at 67Example mode 0 resets at 67 IORDY can delay system up to 1250 nsIORDY can delay system up to 1250 ns Databus enabled by data writeDatabus enabled by data write

Test BenchTest Bench

It simulates controller for our It simulates controller for our modulemodule

It produces are varying waveforms It produces are varying waveforms for the different modesfor the different modes

Evolve into a hard disk with the Evolve into a hard disk with the implementation of UDMAimplementation of UDMA

PIO Timing SimulationPIO Timing Simulation

Finite State MachineFinite State Machine

Ack Start

UDMA

Wait

PIO

Ultra DMAUltra DMA

ResetClk Reset

Rw Cs0, Cs1Start Da0, Da1, Da2Add 4 DstrobeWdata 16 DmardyRdata 16 StopWdone Data 16Rdone

UDtimingmode 3 Dmarq

Dmack

PIOModule(RTL)

Hard Disk(Behavioral)

Ultra DMA Ultra DMA ConstraintsConstraints

Ultra DMA Mode Cycle Time(nanoseconds)

MaximumTransfer Rate

(MB/s)

DefiningStandard

Mode 0 240 16.7 ATA/ATAPI-4

Mode 1 160 25 ATA/ATAPI-4

Mode 2 120 33.3 ATA/ATAPI-4

Mode 3 90 44.4 ATA/ATAPI-5

Mode 4 60 66.7 ATA/ATAPI-5

Phases of Ultra DMA Data Phases of Ultra DMA Data TransferTransfer

Initiating UDMA Data-In (Out) BurstInitiating UDMA Data-In (Out) Burst Data-In (Out) TransferData-In (Out) Transfer Pausing Data-In (Out) BurstPausing Data-In (Out) Burst Terminating Data-In (Out) BurstTerminating Data-In (Out) Burst

Initiating an Ultra DMA Data-Initiating an Ultra DMA Data-In BurstIn Burst

Sustaining Ultra DMA Data-in Sustaining Ultra DMA Data-in BurstBurst

Host Termination of Host Termination of Ultra DMA Data-In BurstUltra DMA Data-In Burst

Device Termination of Device Termination of Ultra DMA Data-in BurstUltra DMA Data-in Burst

Description of the HostDescription of the Host

The Host Has:The Host Has:• A Read Buffer and a Write BufferA Read Buffer and a Write Buffer• Ability to cycle through and request Ability to cycle through and request

all modes of data transferall modes of data transfer• Ability to Calculate CRC Values as well Ability to Calculate CRC Values as well

as periodically send an error to the as periodically send an error to the controller controller

CRC Error Checking CRC Error Checking DesignDesign

Process:Process:• Both Devices are initialized with 4ABABoth Devices are initialized with 4ABA• Value is modified on every STROBE pulseValue is modified on every STROBE pulse

– using G(X) = X16 + X12 + X5 + 1using G(X) = X16 + X12 + X5 + 1

• Host ---> CRC ---> ControllerHost ---> CRC ---> Controller• Bits 2 & 7 in Error Register go highBits 2 & 7 in Error Register go high• <----- 04 HARDWARE ERROR<----- 04 HARDWARE ERROR• Host Should Retry last commandHost Should Retry last command

Gantt ChartGantt ChartFeb

22-28March

1-8March9-15

March25-31

April1-7

April8-14

April15-21

April22-30

May1-8

Become Familiar withTools

Design PIO Mode

Software to SimulateHDD

Design of UDMA Mode

Simulate EntireOperation

Project Website

Who’s doing What.Who’s doing What.

Saif: Program DMA mode RTL Code, Update Saif: Program DMA mode RTL Code, Update WebsiteWebsite

James: Program DMA mode RTLJames: Program DMA mode RTL

Brian: Implement Error Checking, Describe Brian: Implement Error Checking, Describe Host in Behavioral VerilogHost in Behavioral Verilog

Graig: Interface PIO Mode with DMA, Describe Graig: Interface PIO Mode with DMA, Describe Hardrive in Behavioral VerilogHardrive in Behavioral Verilog

Finishing Everything on Finishing Everything on TimeTime

Our Goal is finishing on May 8thOur Goal is finishing on May 8th

We have all the tools and know We have all the tools and know how to use them.how to use them.

We have all the specifications in We have all the specifications in hand.hand.

All team members know their tasksAll team members know their tasks

ReferencesReferences General IDE Information:General IDE Information:

• pcguide.compcguide.com• hardwarecentral.comhardwarecentral.com

ATA5 Specification: t13.orgATA5 Specification: t13.org

Our Website:Our Website:• www-unix.ecs.umass.edu/~sashaikh/ece559/index.htmlwww-unix.ecs.umass.edu/~sashaikh/ece559/index.html