Identifying PCIe 3.0 Dynamic Equalization ProblemsStephen Mueller – Field Applications EngineerStephen.Mueller@teledynelecroy.com

PCI Express 3.0 – What’s new?

PCI Express 2.0 PCI Express 3.0Bit Rate 5 Gb/s 8 Gb/sEncoding 8B/10B 128B/130BOverhead 20% 1.5625%Effective Bit Rate 4 Gb/s per lane 7.88 Gb/s per laneTransmission Path Same as Gen 1 Same as Gen 1 and 2Receiver Testing Informative RequiredLink Equalization Testing NA Required

PCI Express 3.0 PHY Layer

IC System Board PCIE Connector Plug-In Card IC

Signal degrades over long transmission path and connectors

How does PCI Express 3.0 Work

TxEQ RxEQ

TxEQ – De-emphasis and Pre-shoot

RxEQ - CTLE

RxEQ – DFE

De-emphasis

No Emphasis De-emphasis

TxEQ RxEQ

De-emphasis Simulation

TxEQ

RxEQ

Copyright © 2012, PCI-SIG, All Rights Reserved 7

Presets and Cursors

How does PCI Express 3.0 Work

TxEQ RxEQ

Tx implements a FIR based equalization

1 of 11 presets are used during TxEQ process

Equalization is based on 3 tap (pre cursor + post cursor) to create de-emphasis and pre-shoot

Rx implements a behavior equalization algorithm

Behavorial CTLE

Behavioral DFE

Behavioral CDR

Rx will send TxEQ preset requests to Tx to optimize TxEQachieving Dynamic Equalization through link initialization

LTSSM Walk-Through

Dynamic Equalization Phases

There are 4 steps in the equalization process: Phase 0: Upstream sends Downstream

Transmitter and Receiver presets at 2.5G to be used upon entering 8.0G

Phase 1: 8GT/s link established at E-4 BER or better; Both sides advertise EQ capabilities via FS/LF fields

Phase 2: Downstream component adjusts Upstream TX while adjusting its own RX until achieving optimal settings

Phase 3: Upstream component adjusts Downstream TX while adjusting its own RX until achieving optimal settings

Both Preset and Cursor values can be used to adjust TX Equalization settings There are 10 Presets (pre-defined

combinations of de-emphasis and pre-shoot) legal for request during Phase 0, 2, and 3

There are a minimum of 42 combinations of de-emphasis and pre-shoot available when requesting via Cursor values

Phase 2

System Add-in Card

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Phase 2

System Add-in Card

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lMessage sent from root complex (system) to end point (add-in card)

Message sent from end point (add in card) to root complex(system)

Phase 2

System Add-in Card

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Phase 2

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Phase 2

System Add-in Card

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The Upstream Port requests specific Transmitter Equalization settings from the Downstream Port by specifying a desired preset or cursor values.

Phase 2

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The Downstream port responds in the protocol confirming it has changed it’s Transmit

Equalization settings to the requested preset or cursor value.

Channel

Phase 2

System Add-in Card

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lect

rical

System Add-in Card

TxEQ RxEQ

Phase 2

System Add-in Card

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lect

rical

System Add-in Card

TxEQ RxEQChannel

Phase 2

System Add-in Card

System Add-in Card

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lect

rical TxEQ RxEQChannel

Phase 2

System Add-in Card

System Add-in Card

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rical TxEQ RxEQChannel

Phase 2

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Phase 3

System Add-in Card

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Root complex (system) requests preset 1 TxEQ setting from end point (add in card)

End point (add in card) notifies root complex (system) that it’s TxEQ has been set to preset 1

What Was Accomplished?

Channel

SystemTxEQ RxEQ

ChannelRxEQ TxEQ

Channel

Phase 2

Phase 3

System TxEQ and Add-in Card RxEQ are optimized for the channel

Add-in Card TxEQ and System RxEQ are optimized for the channel

Result: BER < 10-12

Add-in Card

Teledyne LeCroy PCIE Gen3 Line CardPHY Layer Electrical Transmitter Testing

PHY Layer Electrical Receiver Testing Link Equalization Testing

Scope Scope + BERT Scope + PeRT3 + Protosync

PCI Express® ArchitecturePHY Test Specification Revision 3.0

Section 2.1, 2.2, 2.5, 2.6

PCI Express® ArchitecturePHY Test Specification Revision 3.0 Section 2.9,

2.8PCI Express® Base Specification . Section 4.3

PCI Express® ArchitecturePHY Test Specification Revision 3.0 Section

2.3, 2.4, 2.7, 2.10, 2.11

Built-in 3 tap de-emphasis/pre-shoot and Protocol aware for loopback

initialization and SKP filtering

Only Test Solution in the Industryfor compliance testing and characterization of

PCIE Gen3 Link Equalization

Built-in PCIE Gen3 required jitter sources (SJ, RJ, Differential Mode Jitter, Common Mode Jitter)

Proto-Sync PCIE Gen3 decode and trigger for in depth debug and characterization

SEG Compliance Testing for PCI-SIG Certification

Test Setup

Link Equalization with the PeRT

Trigger Generator triggers at selected

state Scope captures waveforms

(see upper right) ProtoSync

Waveforms auto- formatted and exported to protocol analyzer software (see lower right)

User “clicking” packets in protocol trace auto- zooms and highlights waveforms in scope window

Analysis User examines protocol trace

and analog waveforms for anomalous data

Protocol and Electrical Data Using Protosync

Example: Slow Electrical Response

Example: Protocol But No Electrical ResponseEverything appears to be working correctly in the protocol

Protocol request for preset 1

Protocol response confirming change to preset 1

Look at the electrical signal and you see the DUT never actually changed to preset 1

Error: Response to preset/cursor requests must not exceed 500 ns or 1000 ns Caveat: Late electrical responses won’t be caught by protocol test Impact: DUT will fail the Link EQ Compliance Test Purpose: During link equalization late responses may cause devices to train their receivers

improperly

Example: Slow Protocol Response

Example: Timeout at Phase 3 Preset Request

PeRT state machine log identifies timeout during dynamic equalization process.

Choose from PeRT trigger list to capture relevant waveform on scope. Splitters are used to pick off the upstream and downstream signal

DUT Firmware Bug in EQ Settings

PeRT sends request for Preset 4 – DUT attenuates output to 20mV

Error: Measured P8 TxEQ not within spec of de-emphasis of 3.5±1.0dB and preshoot of 3.5±1.0dB

Caveat: Won’t be caught by protocol test since measurement is electrical

Impact: DUT will fail the Link EQ Compliance Test Purpose: Inappropriate P7 or P8 values may result in failure to

operate at E-4 or a breakdown in equalization negotiation

Example: Bad TxEQ Electrical

Error: DUT BER not E-12 or better Impact: DUT will fail the Link EQ Compliance Test Purpose: PCIe assumes a low BER. A high BER can

cause link to fail and re-train at lower speeds.

Example: BER Exceeds E-12

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